10 ANALISIS DE LAS EXPERIENCIAS EN LA PRACTICA PEDAGOGICA:
10.2 ANALISIS DE LA CATEGORIA ENSEÑAR Y EVALUAR
The electrical and control system include all the sensors and the electronics that connects to the sensors, valves, and VSD. As mentioned in the system design chapter, the controller is central to the control of the entire platform. Some circuitry is, however, required between the sensors and actuators, and the controller to translate the control signals. These will
CHAPTER 4. SYSTEM IMPLEMENTATION 38
Table 4.6: Controller specifications
ID Specifications
General purpose input output
Logic inputs >6
Logic outputs >4
Analog in I2C bus, SPI + 1 logic output, or 1 ADC
Analog out I2C bus, SPI + 1 logic output, 1 DAC, or
1 PWM Communication
User interface communication Ethernet, or Serial
GSM modem communication USB, Serial, or SPI
GPS module communication USB, Serial, or SPI
also be considered in detail in this section. All these individual circuits join together in a Printed Circuit Board (PCB) to form a complete solution and will be one of the final aspects considered in this section.
4.3.1
Component selection strategy
Various components are needed to implement all the circuits and for each there are specifications that need to be adhered to. However, there are multiple components that adhere to these specification, and a general selection strategy was used to select the final component. Since the developed platform is a prototype, commercial temperature grade components were selected. For the selection of each component, the following was considered when multiple viable options were available:
• Supplier • Availability • Price
• Package (through hole or surface mount) • Size
4.3.2
Controller
In order to determine which controller to use, more specific specifications are listed in Table 4.6 that will enable compliance to the design specifications. Some other aspects that where considered when selecting the processing platform are listed below:
• Rapid development.
• Simplified internet connectivity. • Significant processing power. • Community support.
To enable rapid development, it is clear that developing everything from a bare microprocessor would not work. Consequently, rapid prototyping platforms as mentioned in Section 2.5.1 were considered. These platforms already have the basic circuitry needed
CHAPTER 4. SYSTEM IMPLEMENTATION 39
for a microprocessor and exposes interfaces to connect further circuitry to it, enabling accelerated development. The three most popular devices were considered, namely RP, Beagle-Bone Black, and Arduino Mega. The main factors considered for the three platforms are tabulated in Table 2.2 on page 12.
When comparing the platforms, there are two types, the single-board computers, and the prototype board. The single-board computers, the RP, and Beagle-Bone Black, has an OS which makes internet connectivity much easier, since the OS manages the connection. The single-board computers also have USB ports, making it simpler to connect a cellular modem and GPS unit. The ease of providing internet connectivity enables Specification 5.2 to be easily satisfied, releasing more development time for other functionalities. They also support virtually any programming language, making them highly flexible. The Arduino, on the other hand, is more limited, but has other ways to provide network and internet connectivity. Therefore, for easiest connectivity, simplified USB connections to cellular modem and GPS, and more software language options, it was decided to use a single-board computer.
When considering the RP versus the Beagle-Bone Black, the Beagle-Bone Black has the benefit of having an analog input, known as an ADC, while the RP does not. The RP on the other hand has better community support, something many has found to be an important consideration. It is also relatively simple to add an ADC to the RP using Inter-Integrated Circuit (I2C) or Serial Peripheral Interface (SPI) communication standards. It was therefore decided to use the RP and to reconsider only if unforeseen problems arose.
4.3.2.1 Raspberry Pi
Some important thing to know about the RP is the it operates on 3.3 V logic, but also has access the 5 V on the board. This is important when designing circuits to interface with it.
4.3.3
Valve control
To control the three different valves, the 24 VAC supply to each one has to be controlled. The 24 VAC can be supplied via a transformer from 220 VAC of the generator, but needs to be switched in a manner isolated from the rest of the control circuit. The simplest way to do that is with a relay, a mechanical switch triggered with a small applied DC voltage. The trigger voltage can be controlled using one of the RP’s output pins and a transistor. Since the relay coil is an inductive load, a flyback diode is needed to protect the transistor from a sudden voltage spike when power is removed.
The specifications to be considered for the various components are listed in Ta- ble 4.7. These specifications are derived from the specifications of a typical solenoid valve which will be the load. The implemented circuit is shown in Figure 4.4. When the CTRL_VALVE_OUT signal is pulled high by the RP, the transistor is switched on and connects the relay coil terminal to ground, enabling current to flow from the 5 V source to ground. The transistor is biased to allow the maximum current of between 160 to 400 mA, large enough for the inrush current of the relay, but also limiting enough to protect the rest of the circuit. The circuit allows the coil to be powered by 5 V, while the signal uses 3.3 V. The schematic also shows the 24 VAC supply terminal, T13, and the valve terminal, T3. This enables a single supply terminal and three separate valve terminals, ensuring simple connections.
CHAPTER 4. SYSTEM IMPLEMENTATION 40
Table 4.7: Relay circuit specifications
Attribute Specification
Relay
Rated voltage >24 VAC
Maximum load current >0.3 A
Rated load current >0.1 A
Coil voltage 5 V
Coil power <0.2 W max
BJT
Ic maximum > 80 mA
Diode
Maximum peak forward current >0.1 A
Maximum DC blocking voltage >5 V
24VAC in FINDER_RELAY BC817-25LT1 GND 2.5k 10 k +5V GS 1A U3 A $1 A$2 U3 12 14 11 Q3 R1 R2 D3 T3G$1 T3G$2 T13G$1 T13G$2 CTRL_VALVE_OUT VALVE_OUT
Figure 4.4: Relay circuit schematic
4.3.4
Pump control
The pump is controlled using the VSD supplied and already connected to the pump motor. Two aspects of the pump need to be controlled, the start/stop, and the speed. The Grundfoss VSD provides a logic terminal connection pulled high to 5 V, that when pulled to ground, starts the motor. When the signal is released from ground, the pump stops again. The pump speed can be set using an analog signal ranging from 0.5 to 3.5 V. The VSD also has two feedback signals by means of relays that indicates the status. These feedback signals are set to respectively indicate if the pump is running or not, and if an error has occurred. The VSD ensures the pump operates safely and can bypass the start/stop signal to protect the pump. Therefore, the feedback from the VSD is important to monitor. Three different circuits are needed for these three different signals and will be designed separately, but keeping in mind that signal wires will connect the entire control circuit to the VSD circuit.
4.3.4.1 Interface
The interface between the control circuitry and VSD drive consists of four different signals, start/stop, speed, pump running, and pump error. The section on the discussion of the pressure transducer indicates why the transducer is powered from the VSD. All these
CHAPTER 4. SYSTEM IMPLEMENTATION 41 28V Setpoint GND Start N.O.C C N.O. Relay1 Relay2 Analog out Analog in Reader1 Reader 2 OptoCoupler Pressure Transducer PCB VSD Case
Figure 4.5: Control circuit and variable speed drive wiring interface
signals need to be considered as a whole, since if wired incorrectly, noise could be introduced in the signals. Since non-differential analog signals are used, the grounds of the control circuit and VSD need to be connected. This connection will only be made by the analog signals that are connected with shielded twisted pair cables. Since these ground wires are part of the same bundle, ground loops will not form. The logic signals will be triggered and read in an isolated manner not requiring a connection to the other circuit’s ground, thereby eliminating ground loops. The wiring interface is illustrated in Figure 4.5.
Analog noise reduction The two analog signals, the pump speed signal and pressure transducer signal, are the most sensitive to noise. Therefore, shielded twisted pairs are used for their wiring. This is also indicated in Figure 4.5. There are different ways in which to connect the grounding with different arguments for the benefits for each method. Initially, the wire shielding was only connected to the pump case, and not to the VSD or control circuit ground. The pressure analog signal had too high a level of noise, prompting further investigation. The noise source is mostly the induced noise from the VSD that uses Pulse Width Modulation (PWM), a known noise source.
Different remedies were tested and compared in order to reduce the noise level. Fig- ure 4.6 shows the analog signal measured using an oscilloscope before remedies were applied. An indication of the noise level is the Vrms value, which is 33.5 mV before remedies. The most effective remedy was to connect the VSD ground to the case, reducing the Vrms value to 14.9 mV, as shown in Figure 4.7. Other remedies included connecting the shield to the control circuit ground as well, and using a low impedance ground wire. Neither one of these remedies reduced the noise when measured. To remove the remaining high frequency noise, a Resistor Capacitor (RC) filter was implemented using a 100 nF capacitor with a 160 Ohm resistor, resulting in a time constant of 16 µSeconds. The resulting analog signal can be seen in Figure 4.8.
CHAPTER 4. SYSTEM IMPLEMENTATION 42
Figure 4.6: Analog pressure signal before remedy
Figure 4.7: Analog pressure signal after VSD ground and case connected
Figure 4.8: Analog pressure signal with RC filter imple- mented
Table 4.8: Opto-coupler circuit specifications
Attribute Specification
Opto-coupler
Collector current maximum >5 mA
Collector current minimum <3 mA
Maximum collector-emitter voltage >5 V
Forward voltage <5 V
BJT
Collector current maximum >20 mA
BC817-25LT1 GND 10k 10 k +3V 3 210 Q4 R7 R2 5 T1G$1 T1G$2 R26 CTRL_PUMP_START PUMP_START
Figure 4.9: Opto-coupler circuit schematic
4.3.4.2 Start/stop signal
As mentioned, the start/stop signal is a signal pulled up to 5 V that needs to be pulled to ground to switch. To minimise ground loops, this needs to be done in an isolated manner. A simple cost effective option is to use an opto-coupler, a transistor switched on by a Light Emitting Diode (LED), all within a small four pin package. Table 4.8 shows the specifications for the opto-coupler based on the VSD signal specifications. Figure 4.9 shows the schematic of the implemented circuit. From the schematic it is clear to see that the terminal for the start/stop signal is isolated from the rest of the circuit. When the CTRL_PUMP_START signal is pulled high by the controller, the Bipolar Junction Transistor (BJT) is switched on, connecting the BJT’s cathode to ground, allowing current to flow. The LED in turn switches on the light sensitive transistor, connecting the two terminal points, the start signal to the VSD’s ground.
CHAPTER 4. SYSTEM IMPLEMENTATION 43
Table 4.9: Analog output circuit specifications
Attribute Specification DAC Resolution >=7 bit VDD 3.3 V Communication I2C OpAmp
Supply voltage Single supply
VDD 5 V
Maximum output voltage >3.5 V
Minimum output voltage <2.3 V
Output short circuit current >0.1 mA
4.3.4.3 Pump speed signal
The pump speed is controlled using an analog voltage signal ranging 0.5 V to 3.5 V corresponding to 0% to 100% speed. Design Specification 3.2 states that the speed must be controlled between 60% and 100%. This means that the control circuit only has to generate a signal ranging between 2.3 and 3.5 V. Design Specification 3.1 states that a minimum resolution of 0.5% of full speed is needed, corresponding to maximum increments of 15 mV.
Two design options exits to generate an analog signal from a digital platform. Option 1 is to use PWM and control the duty cycle to adjust the average voltage. The signal generation is completed by applying a low pass filter that effectively outputs the average voltage. To be certain of the generated voltage level, it is best to measure it and adjust the duty cycle accordingly, effectively closing the control loop. Option 2 would be to use a DAC that communicates with the controller via I2C or SPI protocol. These converters are accurate and their characteristics are known. The communication protocol and circuit is also relatively simple to implement and therefore does not pose a risk. Since the RP’s logic level is 3.3 V, the output of the DAC will have to be amplified to reach 3.5 V, or the DAC will have to operate at a higher voltage, requiring logic level converting from the RP’s 3.3 V. The option of using a DAC with a higher output voltage is a more complicated and risky solution, because of the logic level conversion. Therefore, it will not be further considered. Of the two design options, option 2 was selected, since it seemed simpler to implement, especially since no feedback loop is required, and since the output voltage accuracy is better guaranteed.
As mentioned, option 2 requires amplification of the DAC output to reach the require 3.5 V. The amplification circuit also allows for an offset to be added to the output signal, which can be used to lift the minimum output voltage to the 2.3 V level, removing the dead band of 0 to 2.3 V. This means that the DAC only needs to have 80 steps to divide the 2.3 to 3.5 V into 15 mV increments and any more steps will lead to improved resolution. The specification for the DAC and Operational Amplifier (OpAmp) to achieve this design, is listed in Table 4.9.
For the amplification and offset, a non-inverting summing amplifier circuit is required. The circuit amplifies the weighted average of multiple signals. The output of the DAC must be added to an offset and amplified. The amplification circuit together with the DAC schematic is shown in Figure 4.10. POT1 is a potentiometer and allows for the offset
CHAPTER 4. SYSTEM IMPLEMENTATION 44 GN DA +3V 3 1u 1u 0.1u 0.1u 3k6 6k49 MCP601 + - +VS -VS GN DA +5V 10 k 10k GN DA 10k 10k 4k7 GN DA GNDA 0.1u 1u VREF VDD GND SDA SCL DAC-OUT VOUT NC C6 C8 C5 C7 R2 0 R2 1 OPAMP 3 4 1 2 5 R2 3 R24 POT1 POT2 R2 2 C9 C10 T8G$3 T8G$4 SDA SCL 2V1 SETPOINT TC1320
Figure 4.10: Analog output schematic with DAC and non-inverting summing amplification circuit.
to be adjusted. POT2 is also a potentiometer and allows the weighting of the DAC signal relative to the offset signal to be adjusted. When these two potentiometers are calibrated, the set-point signal will range from 2.3 to 3.5 V, condensing the full resolution of the DAC into the operating range. The gain of the amplifier is set by R24 and R23. These two resistors have been selected for a gain of 2, doubling the weighted average of the two inputs.
The selected DAC has a 10-bit resolution, surpassing the 7-bit specification. The voltage reference of the specific DAC has a maximum of VDD-1.2, equivalent to 2.1 V. R20
and R21 are inserted in the design to implement a voltage divider to set the reference voltage to 2.1 V. The resistors used has an accuracy of 1%. The capacitors included in the circuit are to ensure stable voltages at critical signals. If there are noise on these signals, they will manifest at the output signal. The values of the capacitors are what is recommended in the ADC’s application circuit, and are used in this circuit as well. The SDA and SCL signals are part of the I2C communication standard and connects to the RP’s SDA and SCL signals.
4.3.4.4 Pump status signals
The VSD provides feedback of the pump status by switching two internal relays on or off, and exposing their outputs so that it can be measured. The one relay is set to indicate whether the pump is running or not, and the other is set to indicate whether there is an error or not. To read the status of these relays, they have to be connected to logic input pins of the RP. The VSD’s data sheet specifies that the relays should have a minimal load of 5 VDC and 10 mA. This is to ensure a reliable status read. To connect a load of these specifications and translate it to a logic signal for the RP, the schematic in Figure 4.11 was designed. One circuit is implemented per relay. R8 is a 470 Ohm pull-up resistor to 5 V. This ensures that the required 10 mA flows through the relay when closed. Resistor R8 and zener diode Z1 translates the 5 V pull-up voltage to 3.3 V that can be read by the RP logic input from IN_READER1. Terminal T1 connects to the relays as shown in Figure 4.5.
CHAPTER 4. SYSTEM IMPLEMENTATION 45 4k7 47 0 +5V 3v3 R9 R8 Z1 T1G$4 T1G$5 READER1 IN_READER1 GND GND
Figure 4.11: Pump status reading schematic
Table 4.10: Pressure measurement sensor and circuit specifications
Attribute Specification
Pressure transducer
Measuring range minimum 0 kPa
Measuring range maximum >=1000 kPa
Accuracy <=0.5%
ADC
VDD 3.3 V
Resolution >=10 bit (Assuming max pressure of
1000 kPa)
Sample rate >=10 samples per second
Communication I2C
4.3.5
Pressure measurement
A pressure transducer is needed to measure the pressure. The hydraulic design already considered the placement of the sensor. The design specifications specify a pressure range, accuracy, resolution, and frequency for the pressure measurement in Specification 2.6 to 2.9. These design specifications result in the component specifications listed in Table 4.10. The electric signal from the pressure transducer can be either a voltage signal, or a current signal, but both of these can be converted to a readable voltage level for the ADC input, and is therefore not specified.
The pressure transducer used is the one that was supplied with the pump. It complied with the specifications and was therefore used instead of procuring another model. The transducer has a maximum rated pressure reading of 1000 kPa and transmits a current signal ranging from 4 to 20 mA. For readings larger than 1000 kPa the linearity of the output signal is not guaranteed. As mentioned in Section 4.3.4.1, the transducer is powered from the VSD since it requires 28 VDC. Figure 4.12 shows the schematic for the ADC