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Isolation and partitioning refer to the physical separation of components, circuits, and planes from other functional devices, areas, and subsystems.

Allowing RF currents to propagate to different parts of the board by radiated or conductive means can cause problems not only in terms of EMI, but also functionality.

CMOS and bipolar digital components create large transient current flow under three conditions:

1. Current flows directly from power to ground (internal power absorption).

2. Current flows from the power pin, through the chip, to the output pin (driving high, sourcing current to the loads).

3. Current flows into the output pin, through the chip, to its internal ground pin (driving low, sinking current from the loads).

The current flow pattern for item (1), for most small-scale (SSI) and medium-scale (MSI) integrated components, is by far the smallest of the three transient current conditions.

For situations (2) and (3), the chip creates large transient current loops that involve output pins, external loads, and the power and ground planes

surrounding the chip. For example, suppose the chip is connected to a long, 50-ohm trace, and further suppose that the trace is routed on a layer adjacent to a reference plane. When the driver forces current into and out of that trace, an equal and opposite current flows on the reference plane, directly underneath the trace. This reaction current (or returning signal current) reenters the driver through either the power or the ground pin, depending on whether the driver is switching high or low, respectively.

A more general-purpose method of preventing digital currents from

circulating into the analog ground plane would be the following (typical of layouts used with A/D converters in excess of 20 MHz with more than 8 bits). This design technique is called moating.

1. Partition the PCB. Divide into analog, digital, and I/O regions.

2. Isolate all plane layers along this partition line with absence of copper between regions. This absence of copper area is identified as a moat.

3. For power and ground planes, use a 0.010 in. (0.25 mm) minimum wide moat.

4. Tie analog ground and digital ground at one and only one point. This section of the ground plane will be the "bridge" that goes across the moat.

5. Locate the analog portion of analog components exactly in the middle across the bridge.

6. Permit no signals whatsoever to cross the moat in any location under any condition.

7. Ensure that any signals that must pass between the analog and digital sections travel only through the bridge, and do so on a layer adjacent to the bridge (maintain RF return current path).

8. Provide filters for analog power and phase lock loop circuits. This filter provides a digital noise-free analog power source.

Isolation is created by an absence of copper laminate on all planes.

Absence of copper is created using a wide separation (typically a 10 mil minimum) from one section to another. In other words, an isolated area is an island in the middle of the board similar to a castle surrounded by a moat. Only those traces required for operation or interconnect can travel to this separate area. The moat serves as a keep-out zone for signals and traces unrelated to the area interface. Two methods exist to pass traces, power, and ground planes to this island, described in the following section.

Method 1 uses isolation transformers, optical isolators, or common-mode data line filters. Method 2 uses a bridge. Isolation is also used to separate high-frequency bandwidth components from lower bandwidth circuits, in addition to maintaining low-EMI bandwidth I/O in terms of the RF spectrum.

When using this partitioning layout technique, a serious problem with implementation may occur. We have now divided the PCB into regions, digital and analog, providing one connection between them, the bridge. It is mandatory to exclude all other interground current pathways. No other connection must exist that would permit current to circulate between the digital and analog ground. If any current path exists, or if any other

interground connection is present besides the one bridge, RF currents will circulate from digital ground, through the second interground connection (traveling across the moat) to the analog ground. This digital RF current will then return through the analog ground filter located across the bridge,

returning to digital ground. This is exactly what we do not want.

5.2.1 Method 1: Moating

Method 1 involves use of an isolation transformer, optical isolators, or data line filters. The I/O area is thus 100% isolated from the rest of the PCB. A metal I/O connector, if provided, must be RF bonding to chassis ground through a low-impedance path, not to digital or isolated ground. Use of bypass capacitors from shield ground (or braid) of I/O cables to chassis ground is sometimes needed in lieu of a direct connection when required by the interface specification. Shield ground (or drain wire) refers to a discrete pin or wire that connects the internal drain wire of the I/O cable to the PCB.

There are two areas of concern for selecting components used in I/O circuits for isolation purposes:

1. Proper bandwidth filtering.

2. Peak surge voltage capabilities for electrostatic discharge protection.

For example, Ethernet or telecommunication circuits require use of an isolation transformer for compliance with interface specifications to physically isolate the network from the system (computer) in case an abnormal fault develops, thus maintaining network integrity. Common-mode data line filters, or chokes, may be used in conjunction with isolation transformers. Common-mode data line filters (usually toroidal in

construction) may be used for both analog and digital applications. These filters remove undesired common-mode RF energy on signal traces exiting through I/O cables. If power and ground are required in the isolated area, (e.g., +5 VDC), the moat must be crossed with a ferrite bead for the power trace and a single solid trace for ground, three time the width of the power trace. The secondary short-circuit fuse (required for product safety) can be located on either side of the ferrite bead. Sometimes, decoupling is

required to remove digital switching noise from filtered I/O power. Both power and ground trace are routed adjacent to each other to prevent potential RF ground loops that will be developed if both power and ground traces are located on opposite sides of the moat from each other (Fig. 5.2).

Figure 5.2: Using isolation with a moat—method 1.

There is an absence of copper area between the data line filter (DLF) and the I/O connector. This is a design technique not easily recognized. The concern for RF return current to have a return path physically adjacent to the signal line can be waived for this application. Common-mode RF energy is removed from the interface by the filter, preventing radiated RF energy from getting onto the cable. The cable interconnect provides a discontinuity in the return path, in addition to the fact that many cables provided by users are unshielded.

The DLF prevents RF energy from leaving the unit. What is not observed is what happens when an externally induced event occurs, such as ESD, conducted susceptibility, or an electrically fast transient burst. Externally induced energy is injected onto the signal cable. The cable brings the energy into the PCB. If an image plane is provided between the DLF and I/O interconnect, radiated coupling of high-energy levels of crosstalk may develop between signal lines and the plane. The plane will then recouple this energy to the input of the DLF, thus defeating its purpose and use. The item to remember is to keep undesired energy from coupling between

filtered and unfiltered circuits. Mixing two circuits, at different potential levels, will result in serious functionality problems or permanent damage owing to component failure. This is useful only for a differential/balanced interface/line.

5.2.2 Method 2: Bridging in a Moat—Partitioning

Method 2 uses a bridge between a control section and isolated area. A bridge is a break in the moat at only one location, where signal traces, power, and ground cross (see Fig. 5.3). Violation of the moat by any trace not associated with the isolated area will cause serious problems. An RF loop current will be developed (Fig 5.4). RF currents must image back along their trace route, or common-mode noise will be generated between the two separated areas. Unlike Method 1, the power and ground planes are directly connected between the two areas.

Figure 5.3: Partitioning I/O using a bridge in a moat—method

2.

Figure 5.4: Violating the concept of moating.

Sometimes only the power plane must be isolated and the ground plane connected through the bridge. This technique is common for circuits where a common ground plane is needed, or separately filtered and regulated power is required. In this case, a ferrite bead is needed to bridge the moat for filtered power only. If analog or digital power is not required in an

isolated area, this unused power plane can be redefined as a second ground plane, referenced to the main ground plane by vias within the isolated area.

When using bridging Method 2, both ends of the bridge should be bonded to chassis, or frame ground. This is highly recommended if multipoint grounding is provided in the chassis and system-level design. Grounding the entrances to the bridge performs two functions:

1. Grounding removes high-frequency common-mode RF components in the ground planes (ground-noise voltage) from coupling into the

partitioned area.

2. Grounding minimizes eddy currents (for improved ground loop control) that may be present in the chassis or card cage. A much lower impedance path to ground is provided for RF currents (within the PCB) that would otherwise find their way to chassis ground through other paths, such as an I/O cable.

Grounding both ends of the bridge also increases electrostatic discharge immunity. If a high-energy pulse is injected into the I/O connector, this energy may travel to the main control area and cause permanent damage.

This energy pulse must be sunk to chassis ground through a very low-impedance path to prevent component disruption or damage.

Another reason to ground both sides of a bridge is to remove RF ground-noise voltage created by voltage gradients that appear between the

partitioned area and main control section. If common-mode noise contains high-frequency RF components, decoupling capacitors should be provided at each chassis ground stitch connection.

Figure 5.5 illustrates how traces are to be routed when using digital and analog partitions. Because power plane switching noise may be injected into the analog section from digital components, isolation and/or filtering is required, especially on the power plane. All traces that travel from the digital to analog section must be routed through a bridge. For analog power, a ferrite bead must be used to cross the moat. A voltage regulator may also be required. The analog power moat is usually 100% complete around the entire partition. Certain analog components will want analog ground to be referenced to digital ground, but only through a bridge, detailed in Fig. 5.5. Many analog-to-digital and digital-to-analog devices connect the "AGNDS" and "DGNDS" (indicated on the pin designation) together in the device lead frame. When such is the application of a partition, with one ground reference, digital signal currents will not return efficiently to their source, causing noise and EMI. AGNDS and DGNDS should be moated away from each other only when the circuit devices themselves provide AGND to DGND isolation.

Figure 5.5: Digital and analog partitioning.

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Table of Contents

5.4: LOCAL AREA NETWORK I/O LAYOUT

5.5: VIDEO 5.6: AUDIO REFERENCES

Chapter 5 - Interconnects and I/O

Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers, Second Edition by Mark I. Montrose

IEEE Press © 2000 Recommend this title?