The control algorithm was implemented in C and compiled/assembled/linked using the Code Composer software. The program is listed in section C.5. Figure 5.4, which was explained in section 5.2.1, is the flowchart for the program. The program starts by configuring the firmware modules and devices used in the application.
The configuration word which was used for the ADCs (which is defined in table 3.2 in sec- tion 3.3.3), is 0x0000. In short it configures the ADCs to sample at high speed, using the external +4.096V voltage reference and disables the channel auto-scan feature. With the auto- scan feature disabled, each ADC obtains the next sampling channel number from the Chan-
nel Generator module in FPGA Analog as explained in section 4.3.2. The eight channel num-
ber inputs of this module was set as follows: 0 1 2 1 0 1 2 1, because this module outputs the channel numbers provided by the channel number inputs in sequence from input number 0 to input number 7. It then starts again at input number 0. The effective sampling sequence is thus: 0 1 2 1 0 1 2 1 0 1 2 1 0 ...
CHAPTER 5 — TEST IMPLEMENTATION: CONTROL OF AN ACTIVE POWER FILTER 105
Configuring the PWM outputs involves setting input parameters of the PWM Ctrl module im- plemented in FPGA Analog. This module is discussed in detail in section 4.3.4. The switching frequency is determined by two of the input parameters. The first is the maximum value of the triangular waveform generated in the module and the second is the frequency scale factor. By setting the maximum of the triangular waveform to 750 and the frequency scale factor to 1, a switching frequency of 5kHz is obtained. The switch deadtime is set to 8s by setting the dead-
time input parameter to 60. The final parameter which have to be set is the parameter which determines when the Compare Down trigger will be triggered. This trigger is the signal to the DSP to stop sampling the input channels and to start the calculation of the PWM reference sig- nals for the next switching cycle. The trigger must therefore occur long enough before the end of the current switching cycle to allow enough time for the DSP to complete the calculation of the references before the cycle ends. It must be kept in mind that the shorter the time allowed for the calculation of the references, the more accurate the references will be. The time taken by the DSP to calculate the references was measured to be 13.6s. The Compare Down Value input
parameter was thus set 120 providing a period of 16s for the DSP to calculate the references.
The next step in the program is to enable the ADCs and to obtain the average value sampled by each channel. When the compensator operates, these values will be subtracted from the sampled data received from the ADCs for each channel before calculating the actual values of the currents and voltages represented by the samples.
After the offset values had been calculated, the compensator is activated by enabling the PWM module in FPGA Analog. The program then enters the main loop. One iteration of the loop corresponds to one switching cycle. The first step is to enable the interrupts generated by the ADCs and the Compare Down interrupt of PWM block 0 by setting the appropriate bits in the
interrupt enable register of FPGA Analog. Both these interrupts trigger external interrupt 0
of the DSP. When external interrupt 0 is triggered, the DSP executes the associated interrupt routine, int0. This routine reads the interrupt register of FPGA Analog to determine the source of the interrupt. For each of the interrupts implemented in this application there is a section in this routine. The program is in state number 0 at this point and waits for the compute new refs flag to change to a nonzero value. This flag is set to a nonzero value in the int0 routine when the DSP receives an interrupt generated by the PWM module while the program is in state number 0. At this point in the program the only interrupt of PWM block 0 which is activated, is the Compare Down interrupt. When an interrupt is received from the ADCs, the section in the int0 routine responsible for handling interrupts generated by the ADCs, is executed. Since the interrupt register only has one bit representing all three ADCs, it is not possible to know which one of the three ADCs generated the interrupt. Therefore, the 13-bit data word containing the 3-bit channel number and the 10-bit data sample of all three ADCs is read from FPGA Analog. After the channel numbers had been masked off, the data samples are stored. When the Compare Down trigger occurs and the compute new refs flag changes to a nonzero
CHAPTER 5 — TEST IMPLEMENTATION: CONTROL OF AN ACTIVE POWER FILTER 106
value, the program disables all the interrupts generated by FPGA Analog by writing the value 0x0000 to its interrupt enable register. The program is now in state number 1. In this state the PWM references are calculated. The first step is to convert all nine data samples to the voltages and currents they represent. Figure 5.26 is a diagram showing the different stages involved in measuring the supply voltages. The voltages are measured with the voltage probes discussed in section 5.4.1. The probes convert the input voltages of between +160V and -160V to a voltage between +4.096V and 0V which is sampled by the ADCs of FPGA Analog. The sampling process effectively multiplies the input voltage by 250 in order to provide the sampled data which is an integer between 0 and 1024. Using this diagram a formula for calculating the value of the supply voltage from the data sample received from the ADC was derived. This formula is given by eq.5.29. adc data adc data (5.29)
Figure 5.27 is a diagram showing the different stages involved in measuring the current supplied to the load. A LEM current transducer module is used to measure the current. It outputs a current which is a scaled replica of the measured current. These scaled currents generated by the LEM modules are measured with the current probes, as discussed in section 5.4.1. The LEM modules and current probes convert the measured current of between +10A and -10A to a voltage between +4.096V and 0V which is sampled by the ADCs of FPGA Analog. Using this diagram a formula for calculating the value of the supply current to the load from the data sample received from the ADC, was derived. This formula is given by eq.5.30.
adc data adc data (5.30)
Figure 5.28 is a diagram showing the different stages involved in measuring the current injected into the system by the inverter. A LEM current transducer module which is located on the in- verter, is used to measure the current. The output of the LEM module is converted by additional circuitry of the inverter to a voltage of between 0V and 5V. These voltages are then sampled by the ADCs of FPGA Analog. Using this diagram a formula for calculating the value of the the currents injected into the system by the inverter from the data sample received from the ADC was derived. This formula is given by eq.5.31.
# adc data adc data (5.31)
CHAPTER 5 — TEST IMPLEMENTATION: CONTROL OF AN ACTIVE POWER FILTER 107
[+10V ; -10V]
Voltage Scaling & Offset
x 250 ADC FPGA Analog [+4.096V ; 0V] [1024 ; 0] PEC33 Voltage Probe Voltage Divider Vx: [+160V ; -160V]
Figure 5.26: Diagram of the Signal Conversions Involved in Measuring the Supply Voltage
LA 205-S Ix: [+10A ; -10A]
0.0005.(10.Ix):
[+0.05A ; -0.05A] [+5V ; -5V]
Voltage Scaling & Offset
x 250 ADC FPGA Analog [+4.096V ; 0V] [1024 ; 0] PEC33 Current Probe Current-to- Voltage Converter
Figure 5.27: Diagram of the Signal Conversions Involved in Measuring the Current Supplied
to the Load
LTS 25-NP Iconvx: [+16A ; -16A]
x 250 ADC FPGA Analog [1024 ; 0] PEC33 [+5V ; 0V] Current-to- Voltage Converter Inverter
Figure 5.28: Diagram of the Signal Conversions Involved in Measuring the Current Injected
CHAPTER 5 — TEST IMPLEMENTATION: CONTROL OF AN ACTIVE POWER FILTER 108
After the measured currents and voltages had been calculated, they are converted to their equiv- alents in the -plane using the Clarke transform given in eq.5.4. The next step is to calculate
the instantaneous real, p, and instantaneous imaginary, q, powers using eq.s 5.7 and 5.8. Next the alpha and beta components of the reference current, of the current injected into the system by the inverter, is calculated. In order to do that, the AC component of the instantaneous real power is needed. This is accomplished by constructing a large circular FIFO array, p arr, which contains the previous n values of p. Each time the PWM references are to be calculated, the oldest value of p is removed from the array and subtracted from a variable, which is the sum of all the p values in the array, namely p tot. The latest value of p is then inserted into the array into the position of the oldest value and added to p tot. To calculate the current AC compo- nent of p, p ac, p tot is simply subtracted from p. The reference currents for the inverter are calculated, using eq.5.12. In order to be able to apply space vector pulse-width modulation, the reference currents are converted to reference voltages by eq.5.3. Subsequently the sector in which the voltage reference is located in the -plane, is calculated. Using the sector number
and the reference voltage as input, the space vector pulse-width modulation theory is applied to calculate the duty cycles of the three phase arms. The duty cyles which each have a value between 0 and 1, is multiplied by the maximum value of the triangular waveform counter in the PWM block to calculate the references to be applied during the next switching cycle. After the new references had been calculated, the program enters state number 2. In this state the Counter
Zero trigger is activated. This trigger is triggered when the value of the triangular waveform is
equal to zero. This corresponds to the start of a new switching cycle. The DSP then outputs the references to FPGA Analog and enables the interrupts of the ADCs. The program then returns to the beginning of the loop and state number 0.