Table 10-1 lists and summarizes sample designs that are useful in learning to design with PLDasm and the Altera PLDs supported by PLDshell Plus. All examples are included with PLDshell Plus in your installation directory. Some of these files are used as illustrations in this manual.
Table 10-1 Example Filenames
Filename Description File/Language Examples
TEMPLATE.PDS Template file containing blank fields and major keywords. Can be used to get a design started. This is a reference file only, not a working design. SUMMARY.PDS Summary file showing examples of main
PLDasm syntax elements in a meaningful context. This is a quick reference file only, not a working design.
Boolean Equations
4COUNT.PDS 4-bit synchronous counter in Boolean equations. Target device is an EP224. Illustrates basic registered circuit design using Boolean equations. 4ERROR.PDS Same design as 4COUNT.PDS, but with an
intentional error in the QA equation. Target device is an EP224. Used to illustrate the on-line error help feature. See “Getting Started.”
PS2POS.PDS Programmable Option Select for PS/2 Adaptor card in Boolean equations. Target device is an EP312.
CASCADE.PDS Large XOR function in Boolean equations. Target device is an EP220. Illustrates how to distribute large equations across macrocells to help fit designs.
16COUNT.PDS 16-bit binary counter in Boolean Equations. Target device is an EP910.
24COUNT.PDS 24-bit binary counter in Boolean Equations. Target device is an EP910. Illustrates use of Toggle flip-flops to simplify counter design.
Truth Tables
7SEG.PDS 7-segment decoder in Truth Table format. Target device is an EP220. Illustrates Truth Table use for a simple combinatorial design.
Sample Designs
Table 10-1 Example Filenames (Continued) Filename Description
TCOUNT.PDS Counter implemented in Truth Table format and converted to T-type flip-flops. Target device is an EP610. Illustrates how to use Truth Tables to im- plement counters.
State Machine Designs
2BIT.PDS 2-bit Up/Down Counter in State Machine format. Target device is an EP220. Illustrates use of State Machine syntax in a simple design.
BUSCON1.PDS Simple Bus Controller circuit in State Machine format. Target device is an EP224. Illustrates State Machine format for a simple design.
DOUBLCNT.PDS Two 4-bit counters, one synchronous, one asyn- chronous in State Machine format. Target device is an EP610. Illustrates use of State Machine syn- tax in a more complex design. Also illustrates asynchronous clocking of state machines.
EXMEALY1.PDS Mealy State Machine example in State Machine format. Target device is an EP224. Used to illus- trate Mealy outputs in a state machine.
Application Examples (Mixed Format)
UPDOWN.PDS Up/down counter in State Machine format and Boolean equations. Device-independent design. Can be fitted to a variety of devices. Used to illus- trate the differences between device-independent and device-specific design.
STATEDEC.PDS State machine feeding a decoder in State Machine format and Boolean equations. Target device is an EP600.
MEMCONT.PDS Shared memory controller for EISA add-in card in State Machine format and Boolean equations. Target device is an EP610.
PULSE1.PDS Pulse generator examples in State Machine for- mat and Boolean equations. Target device is an EP312.
EX16R6.JED JEDEC file for a 16R6 design. Used to illustrate JEDEC disassembly/conversion to Altera PLDs. Target device is an EP220.
Disassembly/Conversion Examples
EX20L8.JED JEDEC file for a 20L8 design. Used to illustrate JEDEC disassembly/conversion to Altera PLDs. Target device is an EP224.
Sample Designs
EX20V8.JED JEDEC file for a 20V8 design. Used to illustrate JEDEC disassembly/conversion to Altera PLDs. Target device is an EP224.
.ADF/.SMF Translation Examples
SAMP1.ADF Sample 4-bit store and increment circuit written in .ADF format. Target device is an EP312. Used to illustrate the .ADF-to-.PDS translation utility. MANYMACH.SMF Multiple state machine file in .SMF format. Tar-
get device is an EP312. Used to illustrate the .SMF-to-.PDS translation utility.
MACFILE.SMF State machine and TTL macro circuit in .SMF for- mat. Target device is an EP600. Used to illustrate the .SMF-to-.PDS translation utility.
EPX780 Design Examples
BYTEMAP1.PDS A sample design for mapping 32-bit CPU data in 8-bit blocks using the EPX780.
SRAM.PDS MUXCOMP.PDS WTPTR.PDS RDPTR.PDS FIFO1.VEC FIFO1.PDS
Four files that can be merged into a 128x9-bit wide FIFO. RDPTR = Read Pointer, WTPTR = Write Pointer, MUXCOMP = Multiplexer/Com- parator, SRAM = SRAM Definition. FIFO1.VEC is a simulation vector file that can be appended to the merged design for simulation. FIFO1.PDS is also installed to show the final merged design. 3BIT.PDS
1OF8.PDS WIGGLE.VEC
Two files that can be merged into a simple pattern generator. 3BIT = 3-bit state machine, 1OF8 = 1 of 8 decoder. WIGGLE.VEC is a simulation vec- tor file that can be appended to the merged design for simulation. WIGGLE.PDS is also installed to show the final merged design.
80TCNT.PDS 80-bit counter using Toggle flip-flops.
PCIARB1.PDS PCI bus arbiter design using a fixed-priority arbi- tration supporting 10 masters.
2BXOR.PDS 2BCMPR.PDS HIGATE1.PDS HIGATE2.PDS
Example files for illustrating modular design syn- tax. HIGATE1.PDS calls 2BCMPR.PDS, which in turn calls 2BXOR.PDS. HIGATE2.PDS com- bines the same functionality into a single source file.
PATGEN1.PDS Serial pattern generator that stores a default pat- tern in SRAM. Consecutively reads 10 bits of data from SRAM, serializes it, and shifts the data out.
Language Summary
PLDshell Model
Program