Reflexiones críticas sobre la utilidad del ejemplo italiano en perspectiva comparadaperspectiva comparada

Alexis DeVos and his group have built several VLSI chips in (adiabatic) CMOS that

realize reversible logic circuits. These chips are reversible both logically and physically,

which means the logic input signals can be given to physical outputs and obtained as

logic outputs on physical inputs and vice versa. Professor Perkowski’s students simulated

all these circuits and found decreased power consumption when compared with standard

CMOS technology gates. The simulations proved the physical reversibility of all gates

built by DeVos not only the logical reversibility. (a gate is physically reversible if it

works correctly both ways from outputs to inputs and vice-versa). They have done similar

work also for other adiabatic CMOS technologies, therefore I have a trust in the

71 In other words there are no clear distinction between input and output ports in De Vos

technology, which is not true for some other reversible technologies in which the

reversibility is only “logical” but not “physical”. All my methods from chapters 4 – 6 are

for both variants of reversibility, but “physical reversibility” can find additional

applications in circuit design.

We present first the Fredkin gate in this technology. The notation of Fredkin gate in

Double-rail Switch-based technology of DeVos is shown in Figure 3.3.1. Realization of

functions Q and Q’ (symbols used in some papers as counterparts of Q2 and Q1,

respectively) is given in Figure 3.3.2. Symbol “a” represents the naturally (statically)

open and symbol “ a’ “ the naturally closed switch. Similarly double-rail functions R1

and R2 are realized, where R = (R1, R2). This schematic is not shown. We will use both

notations in this dissertation, Q’ or Q2, but some of them are more convenient in certain

explanations. The notation with R and R’ is confusing as it has no symbol for single-rail

logic symbol corresponding to the pair of negative and positive values. 3.3.1 Fredkin Gate P Q R c a b

72

Fig. 3.3.1: Realization of Fredkin gate. This gate uses the notation for De Vos double-rail

technology from Figure 3.3.2.

a a c b c Q Q b Q=c’a+cb Q’=c’a’+cb’

Figure 3.3.2. Realization of function Q in Fredkin gate using De Vos technology. Similarly

function R from Figure 3.3.1 is realized.

The function for R’ (R2) is the negation of the function realized for R (R1). Observe that

in Figure 3.3.3 there are two functions built from switches, F and F’, where function F is

replicated twice, on top and on bottom, and function F’ is also replicated twice, once on

left and once on right. The same property is true in Figure 3.3.4, but with different

functions F. This way, every function can be realized as reversible by EXOR-ing it with a

variable. The exoring is done by the dual construction that uses a variable and its

73 Observe however, that Fredkin gate from Figure 3.3.2 is different, as the upper branch is

the negation of the left branch and the right branch is the negation of the lower branch.

Both styles of De Vos gate design require repeated switches for variables and its

negation. a b a b c p

a

Fig. 3.3.3: Realization of Toffoli gate in double-rail DeVos technology. As we see, this is a kind

of double-rail technology, with wires a and a’ representing signal a, and so on for signals b, c

and P.

The function realized in Figure 3.3.3 for output p is c’ ab in upper branch controlled by

c’ and c (a’ + b’) controlled by c in the right branch. Thus the function realized for p is

the following: 3.3.2 Toffoli Gate.

74 p = c’ ab + c (a’ + b’) = c’ (ab) + c (ab)’ = ab ⊕ c

Similarly, the function realized for negation of p, denoted by p’ is c’ (a’ + b’) (controlled

by c’) and (ab) c controlled by c. Thus the function for negated p, denoted by p’ is the

following:

p’ = c’ (a’ + b’) + (ab) c = c’ (ab)’ + (ab) c = [ ab ⊕ c ]’ = p’ (negation of signal p).

In this way, any reversible gate can be built from switches as a function p and its

complement p’. a

a

a

75 Realization of CNOT (Feynman gate) is shown in Figure 3.3.4. We can check that Q = c’a + c a’ = c ⊕ a. Similarly signal Q’ = c’ a’ + c a = (c ⊕ a) which is Q’ from definition. 3.3.3 Feynman Gate. a b a b a b a b P C C P

Fig. 3.3.5: DeVos CMOS circuit layout for pass-transistor diagram from Figure 3.3.3.

Figure 3.3.5 presents another way of drawing pass-transistor realization of 3*3 Toffoli

gate. This way of drawing the gate emphasizes regularity of design and the double-rail

principle of realization. Similarly all other reversible gates can be drawn and next the

whole schematic of the circuit can be drawn using this layout. The switches in De Vos

technology are realized using CMOS switches, but they can be also optical, fluidic or

other ON/OFF switches (closed/open switches).

De Vos logic implementation illustrates that we can realize an arbitrary reversible gate in

76 *3 Fredkin, 4 *4 Fredkin, and all other binary quantum gates from chapter 3. Thus the

binary circuits that result from all methods from subsequent chapters can be realized

using De Vos switch-based no-clock reversible circuits.

Observe that using DeVos open/close switches, I can realize double-rail CNOT. From

two such CNOTs I can realize quadruple-rail Toffoli. Similarly other quadruple-rail gates

can be built.

As we see, the De Vos technology can create gates CNOT and Fredkin for the Double-

rail technology from section 3.2. Big gates have been also realized and simulated by de

Vos and also simulated at PSU.

Concluding, De Vos technology allows to realize every reversible gate from “open/close

switches”, and is a double-rail technology. Particularly, Fredkin, Feynman, Toffoli, Peres, Miller, Kerntopf and Margolus gates can be realized this way. Although it is more than

10 years from the first introduction of De Vos gates, and although the De Vos gates were

shown by several studies to reduce power, they are not competitive and not used much

commercially. But hopefully, when realized with other type of open/close switches, for

example, in fluidic or optical technologies, these gates will become very power-

competitive. This is a hope of researchers in Y-gate technology, for example. Additional

77 circuits, as presented in papers of Hayes and Markov and the M.S Thesis of Jeff Allen at

PSU.