3.4. REQUERIMIENTOS DEL PROYECTO DE MEJORAMIENTO
3.4.2. REQUERIMIENTOS DE PERSONAL DEL PM
The EEPROM control register is a 32-bit entity at offset 0Ch of the CSR space. They are used to read from and enable writes to an external EEPROM component.
Table 20. Dump Wake-up Data Structure
Dword Offset D31 D0
0 Reserved Status Word (A000h)
1 Reserved Byte Count
2:n Wake-up Packet
46 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual The serial EEPROM or equivalent integrated circuit (IC) stores configuration data for the
controller and the adapter. The EEPROM is a serial in and serial out device. Serial EEPROMs range in size from 16 to 256 registers of 16 bits per register. All accesses, read or write, are preceded by a command instruction to the device. The command instructions begin with a logical 1 as the start bit, two opcode bits (indicating read, write, erase, etc.), and n-bits of address. The address field varies with the size of the EEPROM and is 6 bits for a 64 register EEPROM and 8 bits for a 256 register device. The end of the address field is indicated by a dummy 0 bit from the EEPROM, which indicates the entire address field has been transferred to the device. A command is issued by asserting the chip select signal and clocking the data into the EEPROM on its data input pin relative to the serial clock input. The chip select signal is de-asserted after the completion of the EEPROM cycle (command, address and data).
6.3.4.1 CPU Accesses to the EEPROM
The EEPROM access port is shown below. This register is located at offset 0Eh in the device Control register block. The CPU directly manipulates these bits to read to or write from the EEPROM. There should be no other local bus activity at this time.
Table 21. EEPROM Control Register Locations
Upper Word (D31:D16) Lower Word (D15:D0) Offset
SCB Command Word SCB Status Word Base + 0h
SCB General Pointer Base + 4h
PORT Base + 8h
EEPROM Control Register Reserved Base + Ch
Figure 12. EEPROM Control Register
23 22 21 20 19 18 17 16
X X X X EEDO EEDI EECS EESK
Table 22. EEPROM Control Register Bits Definitions
Bit Symbol Description
23:20 Reserved.
19 EEDO Serial Data Out. This bit contains the value read from the EEPROM when performing a read operation on the EEPROM.
18 EEDI Serial Data In. The value of this bit is written to the EEPROM when performing write operations.
17 EECS
Chip Select. Setting this bit to 1 enables the EEPROM. Setting the bit to 0 disables the EEPROM. This bit must be set to 0 for a minimum of 1 µs between consecutive instruction cycles.
16 EESK
Serial Clock. Setting this bit to 1 drives the serial clock line to the EEPROM high.
Setting this bit to 0 drives the serial clock line low. Toggling this bit high and then low clocks data in or out of the EEPROM. The serial EEPROM specifies a minimum clock period of 4 µs. The minimum period that the clock can be high or low is 1 µs. If the clock is driven high for only 1 µs, then it must followed by a low period of 3 µs to meet the minimum clock frequency specification.
Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual 47
6.3.4.2 Software Determination of EEPROM Size
To determine the size of the EEPROM, software may use the following steps.
Note: This algorithm will only work if the EEPROM drives a dummy zero to EEDO after receiving the complete address field.
1. Activate the EEPROM by writing a 1 to the EECS bit.
2. Write the read opcode, including the start bit (110b), one bit at a time starting with the most significant bit (1):
a. Write the opcode bit to the EEDI bit.
b. Write a 1 to EESK bit and wait the minimum SK high time.
c. Write a 0 to EESK bit and wait the minimum SK low time.
d. Repeat steps 2.a through 2.c for the next two opcode bits.
3. Write the address field, one bit at a time, keeping track of the number of bits shifted in, starting with the most significant bit.
a. Write the address bit to the EEDI bit.
b. Write a 1 to the EESK bit and wait the minimum SK high time.
c. Write a 0 to the EESK bit and wait the minimum SK low time.
d. Read the EEDO bit, looking for the dummy 0 bit.
e. Repeat steps 3.a through 3.d until the EEDO bit equals 0. The number of loop iterations performed is the number of bits in the address field.
4. Read a 16-bit word from the EEPROM one bit at a time, starting with the most significant bit, to complete the transaction (but discard the output).
a. Write a 1 to the EESK bit then wait the minimum SK high time.
b. Read a data bit from the EEDO bit.
c. Write a 0 to the EESK bit then wait the minimum SK low time.
d. Repeat steps 4.a through 4.c an additional 15 times.
e. De-activate the EEPROM by writing a 0 to the EECS bit.
Table 23. EEPROM Opcode Summary (64-register EEPROM)
Instruction Start
Bit Opcode Address Data Comments
Read 1 10 A5A4A3A2A1A0 Read register A5A4A3A2A1A0 Write 1 01 A5A4A3A2A1A0 D1:D0 Write register A5A4A3A2A1A0 Erase 1 11 A5A4A3A2A1A0 Erase register A5A4A3A2A1A0
EWEN 1 00 11xxxx Erase/write enable
EWDS 1 00 00xxxx Erase/write disable
ERAL 1 00 10xxxx Erase all registers
WRAL 1 00 01xxxx D15:D0 Write all registers
48 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual
6.3.4.3 Software Read Access from the EEPROM
To read from the EEPROM, software is required to perform the following steps. The example is a read from address 02h (0000 0010b).
Note: Since the address field is written most significant bit first, software must know the address field size prior to starting a read or write access.
1. Activate the EEPROM by writing a 1 to the EECS bit.
2. Write the read opcode, including the start bit (110b), one bit at a time, starting with the most significant bit (1):
a. Write the opcode bit to the EEDI bit.
b. Write a 1 to EESK bit then wait the minimum SK high time.
c. Write a 0 to EESK bit then wait the minimum SK low time.
d. Repeat steps 2.a through 2.c for the next two opcode bits.
3. Write the address field, one bit at a time, starting with the most significant bit.
a. Write the address bit to the EEDI bit.
b. Write a 1 to EESK bit then wait the minimum SK high time.
c. Write a 0 to EESK bit then wait the minimum SK low time.
d. Read the EEDO bit (looking for the dummy 0 bit).
e. Repeat steps 3.a through 3.d until the EEDO bit equals 0, indicating that the address field has been completely written.
4. Read a 16-bit word from the EEPROM, one bit at a time, starting with the most significant bit.
a. Write a 1 to the EESK bit then wait the minimum SK high time.
b. Read a data bit from the EEDO bit.
c. Write a 0 to the EESK bit then wait the minimum SK low time.
d. Repeat steps 4.a through 4.d an additional 15 times.
5. De-activate the EEPROM by writing a 0 to the EECS bit.
Figure 13. EEPROM Read Timing Diagram
AA10 EECS
EESK
EEDI
EEDO
A5 A4 A2
D15 D0
READ OP code
A3 A1 A0
Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual 49
6.3.4.4 Software Write Access to the EEPROM
Write access to the EEPROM is similar to the read access outlined above, with the differences of a write opcode and step 4:
1. Activate the EEPROM by writing a 1 to the EECS bit.
2. Write the read opcode, including the start bit (110b), one bit at a time, starting with the most significant bit (1):
a. Write the opcode bit to the EEDI bit.
b. Write a 1 to EESK bit then wait the minimum SK high time.
c. Write a 0 to EESK bit then wait the minimum SK low time.
d. Repeat steps 2.a through 2.c for the next two opcode bits.
3. Write the address field, one bit at a time, starting with the most significant bit.
a. Write the address bit to the EEDI bit.
b. Write a 1 to EESK bit then wait the minimum SK high time.
c. Write a 0 to EESK bit then wait the minimum SK low time.
d. Read the EEDO bit (looking for the dummy 0 bit).
e. Repeat steps 3.a through 3.d until the EEDO bit equals 0, indicating that the address field has been completely written.
4. Write a 16-bit word to the EEPROM, one bit at a time, starting with the most significant bit (write a data bit to the EEDI bit):
a. Write a 1 to the EESK bit then wait the minimum SK high time.
b. Write a 0 to the EESK bit then wait the minimum SK low time.
c. Repeat steps 4.a through 4.c an additional 15 times.
5. De-activate the EEPROM by writing a 0 to the EECS bit.