Rio Cesar

Digital VLSI Design, ECE Dept.SET,JU. Page 14

Silicon on insulator process:

Silicon on insulator (SOI) CMOS processes has several potential advantages such as higher density, no latch-up problems, and lower parasitic capacitances. In the SOI process a thin layer of single crystal silicon film is epitaxial grown on an insulator such as sapphire or magnesium aluminate spinel. The steps involves are:

1) A thin film (7-8 μm) of very lightly doped n-type Si is grown over an insulator. Sapphire is a commonly used insulator.

2) An anisotropic etch is used to etch away the Si except where a diffusion area will be needed. 3) The p-islands are formed next by masking the n-islands with a photoresist. A p-type dopant

(boron) is then implanted. It is masked by the photoresist and at the unmasked islands. The p- islands will become the n-channel devices.

4) The p-islands are then covered with a photoresist and an n-type dopant, phosphorus, is implanted to form the n-islands. The n-islands will become the p-channel devices.

5) A thin gate oxide (500-600Å) is grown over all of the Si structures. This is normally done by thermal oxidation.

6) A polysilicon film is deposited over the oxide.

7) The polysilicon is then patterned by photomasking and is etched. This defines the polysilicon layer in the structure.

8) The next step is to form the n-doped source and drain of the n-channel devices in the p- islands. The n-island is covered with a photoresist and an n-type dopant (phosphorus) is implanted.

9) The p-channel devices are formed next by masking the p-islands and implanting a p-type dopant. The polysilicon over the gate of the n-islands will block the dopant from the gate, thus forming the p-channel devices

10) A layer of phosphorus glass is deposited over the entire structure. The glass is etched at contact cut locations. The metallization layer is formed. A final passivation layer of a phosphorus glass is deposited and etched over bonding pad locations.

Digital VLSI Design, ECE Dept.SET,JU. Page 15 Due to the absence of wells, denser structures than bulk silicon can be obtained.

Low capacitances provide the basis of very fast circuits. No field-inversion problems exist.

No latch-up due to isolation of n- and p- transistors by insulating substrate. As there is no conducting substrate; there are no body effect problems Enhanced radiation tolerance.

But the drawback is due to absence of substrate diodes, the inputs are difficult to protect. As device gains are lower, I/O structures have to be larger. Single crystal sapphires are more expensive than silicon and processing techniques tend to be less developed than bulk silicon techniques.

Digital VLSI Design, ECE Dept.SET,JU. Page 16

CMOS Process Enhancements

Note:(In this topic just know this and if question asked in exam just head lines are enough)

a) Using Multiple Threshold Voltages and Oxide Thicknesses b) Silicon on Insulator (SOI)

c) Using High-k Gate Dielectrics

 MOS transistors need high gate capacitance to attract charge to the channel. This leads to very thin SiO2 gate dielectrics (e.g., 10.5–12 Å, merely four atomic layers, in a 65 nm process)

 Gate leakage increases unacceptably below these thicknesses, which brings an end to classical scaling

 Simple SiO2 has a dielectric constant of k = 3.9, so gates could use thicker dielectrics and hence leak less if a material with a higher dielectric constant are available

 Example, Hafnium oxide (HfO2) has k 20.

d) Using Higher Mobility

 Increasing the mobility (u) of the semiconductor improves drive current and transistor speed. One way to improve the mobility is to introduce mechanical strain in the channel. This is called strained silicon.

e) Using Plastic Transistors

 MOS transistors can be fabricated with organic chemicals. These transistors show promise in active matrix displays, flexible electronic paper, and radio-frequency ID tags because the devices can be manufactured from an inexpensive chemical solution.

f) Using High-Voltage Transistors

 High-voltage MOSFETs can also be integrated onto conventional CMOS processes for switching and high-power applications. Gate oxide thickness and channel length have to be larger than usual to prevent breakdown.

g) Interconnect

 Interconnect has advanced rapidly. While two or three metal layers were once the norm, CMP has enabled inexpensive processes to include seven or more layers. Copper metal and low-k dielectrics are almost universal to reduce the resistance and capacitance of these wires.

Digital VLSI Design, ECE Dept.SET,JU. Page 17 i. Copper Damascene Process While aluminum was long the interconnect metal of choice; copper has largely superseded it in nanometer processes. This is primarily due to the higher conductivity of copper compared to aluminum.

 Copper atoms diffuse into the silicon and dielectrics, destroying transistors.  The processing required to etch copper wires is tricky.

 Copper oxide forms readily and interferes with good contacts.

 Care has to be taken not to introduce copper into the environment as a pollutant.

 Barrier layers have to be used to prevent the copper from entering the silicon surface. A new metallization procedure called the damascene process was invented to form this barrier.

ii. Low-k Dielectrics SiO2 has a dielectric constant of k = 3.9–4.2. Low-k dielectrics between wires are attractive because they decrease the wire capacitance. This reduces wire delay, noise, and power consumption.