Se sustituye el Título XI, «Tesoro Nacional», por el siguiente, con el rubro:

Prototyping

The VHDL/PLD design methodology can be used for proof-of-concept to rapidly prototype and implement a system in small quantities to prove its viability. If the system is successful, the same kind of PLDs can be used for large production runs. When a design is well proven and needs to be produced in very large quantities, it may be economical to create an application-specific integrated circuit (ASIC) instead of using PLDs. The same VHDL description used to implement a design targeted to a PLD can be used as the design description from which an ASIC is created.

1 . 1 3 V H D L’S D E V E L O P M E N T

VHDL is an acronym for VHSIC (Very High Speed Integrated Circuit) Hardware Description Language. VHDL has its origins in a research project funded in the early 1980s by the U.S. Department of Defense (DoD).

IEEE Std 1076 In 1985 the DoD released VHDL for public use. To encourage widespread adoption, a proposal was made to the IEEE to make VHDL a standard. A modified version of the original VHDL became IEEE Std 1076-1987. “Std” is the IEEE’s abbreviation for “Standard.” The standard’s number is 1076. The number following the hyphen is the date that the standard was issued or revised.

The document that defines the precise syntax and simulation semantics of VHDL is the IEEE Standard VHDL Language Reference Manual (LRM). Revised versions of this standard are dated 1993, 2000, and 2002.

1 . 1 4 V H D L F O R S Y N T H E S I S V E R S U S V H D L

F O R S I M U L A T I O N

VHDL was originally designed to be used for description, simulation, and documen- tation of digital systems, but not for synthesis. It was later adopted as a design description language for synthesis.

Learning VHDL for the purpose of synthesis involves more than just IEEE Std 1076. Related IEEE standards, such as IEEE Std 1164, IEEE Std 1076.3, and IEEE Std 1076.6, also need to be utilized so that we can make our VHDL designs as portable and “standard” as possible. These supporting standards are also discussed in this book. The Bibliography lists applicable VHDL standards.

VHDL for Synthesis

As previously stated, some VHDL constructs are not synthesizable. Therefore, it is possible to write a VHDL description that can be simulated, but not synthesized.

For a design description to be synthesizable, we must use only those constructs that are acceptable to our synthesis tool. A synthesis tool infers the logic it synthe- sizes from the context in which specific constructs appear in a design description. If

the VHDL code is physically meaningless or too far removed from the hardware it attempts to describe, it may not be synthesizable.

Use of the term design description in this book is restricted to synthesizable VHDL programs. For brevity, design description will often be shortened to either design or description.

IEEE Std 1076.6 Prior to 1999 there was no standard that specified which VHDL language constructs a synthesis tool must be able to synthesize. As a consequence, the subsets of VHDL constructs that could be synthesized differed from one synthesis tool to the next. This limited the portability of VHDL descriptions that were to be synthesized.

In 1999, the IEEE issued IEEE Std 1076.6-1999, IEEE Standard for VHDL Register Transfer Level (RTL) Synthesis. This standard described a subset of IEEE Std 1076 suitable for RTL synthesis. It also described the syntax and semantics of this subset with regard to synthesis. The purpose of this standard was to have all compliant RTL synthesis tools produce functionally equivalent synthesis results, just as IEEE Std 1076 ensures that all compliant simulation tools produce equivalent simulation results. A revision of this standard was issued in 2004.

Example design descriptions in this book are written to be compliant with IEEE Std 1076.6-2004. These descriptions have been simulated and synthesized and should be synthesizable by most recent synthesizer tools, whether IEEE 1076.6 compliant or not.

VHDL for Simulation

Testbenches are written to apply stimulus to a UUT and to verify the UUT’s output values during simulation. Testbenches are not synthesized. Accordingly, there are no constraints on which VHDL constructs we can use in a testbench. All testbenches in this book have been simulated using Aldec’s Active-HDL simulator. They should be capable of being simulated on any IEEE Std 1076-1993 or later compliant VHDL simulator.

1 . 1 5 T H I S B O O K ’S P R I M A R Y O B J E C T I V E

Providing you with the necessary fundamentals to use VHDL for description, verifi- cation, and synthesis of digital systems that are to be implemented using PLDs is this book’s primary objective. Therefore, using VHDL for synthesis and using VHDL for simulation are both focuses of this book.

In this book, the presentation of fundamental concepts is ordered so that you can accomplish complete designs of simple systems as early as possible, while still in the process of learning VHDL.

Problems 41

P R O B L E M S

1.1 For each phase in the VHDL/PLD design methodology design flow in Figure 1.1.1 give a brief description (one or two sentences) of what is accomplished.

1.2 What important descriptive feature of HDLs is not common to conventional high-level programming languages?

1.3 In terms of a signal, what is an event?

1.4 What happens to the traditional design tasks of minimizing the number of gates and flip-flops when the VHDL/PLD design methodology is used?

1.5 Describe some advantages of using a PLD as opposed to fixed-function ICs to implement a digital system.

1.6 What is the advantage, if any, of having the specification for a system originate in VHDL form rather than in a natural language form?

1.7 If you have a system specification that originated in VHDL form, can you simply synthesize it directly?

1.8 Write a brief requirements definition and specification for a 1-bit half subtractor.

1.9 What is a concurrent signal assignment statement and when is it executed? Does the textual order of concurrent signal assignment statements in an architecture body make any difference?

1.10 If you have a function expressed as a Boolean equation, should you attempt to simplify it before using it in a signal assignment statement in a VHDL description? Explain your answer.

1.11 Design a half adder using the traditional approach. From the truth table in Figure 1.3.1 create a Karnaugh map for each output. From the Karnaugh maps, determine the simplified sum-of- products expression for each output. Draw a logic diagram for two implementations of the circuit, one using AND, OR, and NOT gates and the other using only NAND gates.

1.12 Draw a flowchart showing the design flow for the traditional method of designing a half adder followed in Problem 1.11. Show each phase involved. Compare your flowchart with the one in Figure 1.1.1 for the VHDL/PLD design methodology. In particular, for corresponding phases of the two methodologies, comment on the relative time each approach would take. Also, discuss how this time might increase at each phase for the application of each approach to the design of a much more complex system.

1.13 Compare the traditional implementation of a half-adder physical prototype using SSI NAND gates (74HC00) with that of a 22V10 PLD implementation using the VHDL/PLD methodo- logy. Qualitatively compare component cost, construction time, printed circuit board space, power consumption, reliability, and ease of modification if an error were made in the logical design.

1.14 Using the half-adder description in Listing 1.3.1 as a template, write a description of a half subtractor that subtracts b from a and produces a difference (a - b) output named diff and a borrow output named borrow. It might be helpful to start by developing a truth table for your half subtractor.

1.16 What is the difference between a static semantic error and a dynamic semantic error? Which tool is used to detect each type of error?

1.17 Using the half-adder description in Listing 1.3.1 as a starting point, write a description of a full adder. The full adder has inputs a, b, and carry_in and produces outputs sum and carry_out.

1.18 What kind of simulation is used to logically debug a design and why?

1.19 If you needed to verify that your synthesizer is correctly generating logic for a particular design, what type of simulation must you perform? What kind of VHDL model must you simulate and what would be the source of that model? If you found that the logic synthesized is not correct, how would you remedy this problem?

1.20 If you needed to verify that a particular design would be fast enough when targeted to a specific PLD, what type of simulation must you perform? What kind of VHDL model must you simulate and what would be the source of this model? If you found that the design was too slow when targeted to the specified PLD, how might you remedy this problem?

1.21 If you developed an algorithm to perform the logical operations required in a system’s specification, what type of simulation should you perform to verify the algorithm? What kind of VHDL model would you simulate and what would be the source of the model? If you found an error in the algorithm, how would you remedy this problem?

1.22 What is a testbench and what is the relationship of a design entity to its testbench? Can the same testbench be used for each of the three kinds of simulations?

1.23 What is a UUT?

1.24 What are the primary advantages of using a testbench for simulation rather than preforming an interactive simulation or a command–line–driven simulation?

1.25 Why does a testbench not require inputs or outputs?

1.26 Modify the half-adder testbench in Listing 1.5.1 to create a testbench for the half subtractor of Problem 1.14.

1.27 Examine the testbench in Listing 1.5.1. Create a table listing, in order, the stimulus values applied and the expected output values for each stimulus value.

1.28 Draw the waveform that you would expect from the functional simulation of the half subtractor of Problem 1.14 assuming that the stimulus values are the same as in Listing 1.5.1.

1.29 What is a programmable logic device? What are the three major classes of programmable logic devices?

1.30 Make a copy of Figure 1.7.1(a) and mark it to represent the programming of this device so that output 0₁ is the equality function.

1.31 What is a product line? What is a sum line?

1.32 Using a copy of the PLD logic diagram in Figure 1.7.1(a), mark it to represent the programming of this device to implement the half subtractor of Problem 1.14.

1.33 What is an erasable PLD?

Problems 43