Session 13 Introduction to Field Effect Transistors (FET)

Session 13

Introduction to Field Effect

Transistors (FET)

Electronic Components and Circuits

Field Effect Transistors

FET

OBJECTIVES

•

To know the structure of the device and the transistor

•

To know the structure of the device and the transistor

effect

•

To know and distinguish different FET transistor types

•

To understand the current-voltage characteristic of the

device

•

To identify the operating regions

Cut-off, Saturation, Ohm (triode)

Cut-off, Saturation, Ohm (triode)

•

To analyze FET circuits basic cases in DC

Field Effect Transistors (FET)

Types

Mode

Channel

MOSFET

(Metal-Oxide Semiconductor FET)

Enhancement/ Accumulation

Channel N (or N-MOS) Channel P (or P-MOS)

Depletion Channel N (or N-MOS)

Channel P (or P-MOS)

JFET

(Joint FET)

Junction Channel N

Channel P

Unipolar: only one carrier type (electrons in N-channel and holes in P-channel)

Basic characteristics

channel)

Control of Current (I) through Voltage(V) (BJT devices control I through I) Three terminals:

Structure of Channel-n

Enhancement MOS Transistor

D G S

Metal Oxide (SiO₂)

W

Drain (D)

Gate (G) Source (S) Metal _Oxide

(SiO₂)

n+ Channel _n+

region

L p-type

substrate (Body) B

p-type substrate (Body) Drain region

Source region

n+ _n+

Channel region

L

D

S

B G

D

S

B G

D

S G

D

S

G B

n-MOS Transistor Operation

G

D S _V

GS

induced

n-type

channel

p-type substrate

B

GND

e

-e- _e

-e

-+

u _u +

G D

S VGS

V_DS

i_{D i}

G= 0 _i

S=iD

p-type substrate

B

GND induced

n-typechannel

+

u _u +

n-MOS Operation:

Triode region

i_D (mA)

0,4

0,3

v_GS= V_t+2 V

v_GS= V_t+1,5 V

G D

S VGS

V_DS (small)

i_{D i}

G= 0 _i

S=iD

v_DS (mV)

0,2

0,1

0 50 100 150 200

vGS≤ Vt

v_GS= V_t+0,5 V v_GS= V_t+1 V

p-type substrate

B

GND induced

n-typechannel

+

u _u +

n-MOS Operation:

Saturation region

i_D

Saturation Triode

v_DS<v_GS- v_t v_DS≥ v_GS - v_t

G D

S VGS

V_DS

i_D

i_G= 0

i_S=i_D

v_DS

v_GS > v_t

v_DSsat = v_GS - v_t

p-type substrate

B

GND n-channel

+

u _u +

Current-Voltage Characteristic

V_DS +

-i_D

i_G= 0

Saturation region Triode

region

v_DS<v_GS - v_t v_DS≥ v_GS - v_t

i_D (mA)

2,0 _{v = V +2,0}

Triode region

[

2

]

−

−

=

V_GS +

-i_D= i_S vDS= vGS- vt

v_DS(V) 1,5

2,0

1,0

0,5

0 1 2 3 4

v_GS≤ V_t (cutoff) v_GS= V_t+0,5

v_GS= V_t+1,0 v_GS= V_t+2,0

v_GS= V_t+1,5

[

2

]

)

(

2

_{GS t DS DS}

D

K

V

V

V

V

i

=

−

−

2

)

(

_{GS t}

D

K

V

V

i

=

−

Saturation region (I

_D

does not depend on V

_DS

)

L

W

C

K

µ

_{n ox}

Output Characteristics: Saturation

i_D (mA)

2,0

1,5

1,0

0,5

0 0,5 1 1,5 2 2,5 3

v_DS≥ v_GS- v_t

2

)

(

_{GS t}

D

K

V

V

i

=

−

Saturation region (I

_D

does not depend on V

_DS

)

v_GS (V)

Current-Voltage Characteristic

Saturation region Triode

region

i_D

v_GS= V_t+2,0V

Slope = 1/ro

v_DS

vGS≤ Vt (cutoff)

v_GS= V_t+0,5V v_GS= V_t+1,0V v_GS= V_t+1,5V

-V

_A

= -1/

λ

)

1

(

)

(

_{GS t} 2 _DS

D

K

V

V

V

i

=

−

+

λ

V

_{A is the channel modulation voltage, producing a similar effect to the Early voltage in BJT}

devices.

If we consider this effect then:

p-channel MOSFET (P-MOS)

Drain (D)

Gate (G) Source (S) Source (S) _{Gate (G)} Drain (D)

Polysilicon Gate Oxide

Thick

In

enhancement p-mos

there is a

channel if:

V

≤

V

<

0

p

+

_p

+

p-type body

S

B G

S

B G

S

G

n

+

_n

+

n-well

Thick SiO₂ (isolation)

channel if:

triode region

saturation region

0

<

≤

_t

GS

V

V

t GS

DS

V

V

V

≥

−

t GS

DS

V

V

V

≤

−

S S D D

D

Depletion MOSFET

Equivalent behavior to enhancement MOSFET devices, except for

Manufactured channel:

When V

_GS

<0 channel is reduced (e

-

_{leave Gate region)}

When

V

≤

V

<

0

channel disappears (

cut-off

region)

When

V

_GS

≤

V

_t

<

0

channel disappears (

cut-off

region)

D

S

B G

D

S G

Saturation region Triode

region

v_DS= v_GS- v_t

v_DS<v_GS- v_t vDS ≥ vGS - vt

i_D (mA)

24 32

20 28

v_GS= 2V (V_t+6)

v_GS= 1V (V_t+5) 36

S D

G B

v_DS (V)

16

8

0 4 8 12

v_GS≤ -4 V (V_t)

v_GS= -3V (V_t+1)

2 6 10 14

12

4 vGS= -2V (Vt+2)

v_GS= 0V (V_t+4)

Summary

In

enhancement

n-MOS there is a

channel if:

in triode region

in saturation region

0

>

≥

_t GS

V

V

t GS

DS

V

V

V

≤

−

t GS

DS

V

V

V

≥

−

In

enhancement

p-MOS there is a

channel if:

in triode region

in saturation region

0

<

≤

_t GS

V

V

t GS

DS

V

V

V

≥

−

t GS

DS

V

V

V

≤

−

in saturation region

t GS

DS

V

V

V

≥

−

in saturation region

t GS

DS

V

V

V

≤

−

i_D

0 vGS

n-channel enhancement p-channel enhancement p-channel depletion n-channel depletion

In

depletion

n-MOS there is a

channel if:

in triode region

in saturation region

0

,

<

≥

_{t t}

GS

V

V

V

t GS

DS

V

V

V

≤

−

t GS

DS

V

V

V

≥

−

In

depletion

p-MOS there is a

channel if :

in triode region

in saturation region

0

,

>

≤

_{t t}

GS

V

V

V

t GS

DS

V

V

V

≥

−

t GS

DS

V

V

V

≤

−

Junction Field Effect Transistor (JFET)

N channel

P channel

Drain Gate p -t y p e G a te n-type C h a n n e l Drain Gate n -t y p e G a te p-type C h a n n e l Drain Gate Gate Drain 2 2

/

,

)

(

_{GS p DSS p}

D

K

V

V

K

I

V

i

=

−

=

2

1

_















−

=

p GS DSS D

V

V

I

i

Source Source Gate Source

Saturation region

Triode region

v_DSsat= v_GS - v_p

v_GS0 = 0

v_GS1 = V_GS0

Saturation

I

_DS

I

_DS

Source

v_GS4 < V_P

v_GS3 < V_GS2

v_GS2 = V_GS1

Cutoff region

Saturation

region

Triode

region

v

_GS

v

_p

V

_DS

Cutoff region

DC bias point:

Load line

Saturation Triode

I_{D v = V}

V_DD

v₁

+

v_o= v_DS

v_GS=v₁

-R_D

Saturation Triode

I_D

I_DQ

Q

Load line slope = -1/RD

v = V

v_GS= V_1B

v_GS< V_1B v_GS> V_1B v_GS= V_DD

B C

v_GS=v₁

-v_DS=v_o 0 VOB=VIB-VIt

v_GS= … v_GS= V_1Q

A

FET transistor as amplifier:

V_DD

v

_o

Q₁ in triode region Q₁in

saturation Q₁

cutoff

A

V_DD

Q

B

C X

Time VOQ=VOQ

VOB

V

v_O Slope at Q = voltage gain

V_DD

VOC

V_t V_IQ V_IB=V_OB+V_t

_v

i

Small-signal model

+

v

_gs

g

_m

v

_gs

G

_D

+

v

_gs

g

_m

v

_gs

G

_D

r

_o

Saturation Triode

i_D

vGS= Vt+2,0V

Saturation Triode

v_DS= v_GS- v_t

v_DS<v_GS- v_t v_DS≥ v_GS- v_t

i_D (mA)

1,5

2,0 vGS= Vt+2,0

-v

_gs

g

_m

v

_gs

S

-v

_gs

g

_m

v

_gs

S

r

_o

Slope = 1/ro

vDS

vGS≤ Vt

(cutoff) vGS= Vt+0,5V

vGS= Vt+1,0V

vGS= Vt+2,0V

vGS= Vt+1,5V

-V_A= -1/λ

v_DS= v_GS- v_t

v_DS(V) 1,5

1,0

0,5

0 1 2 3 4

v_GS≤ V_t(cutoff)

vGS= Vt+0,5

vGS= Vt+1,0

Small-signal parameters

+

-v

_gs

g

_m

v

_gs

G

_D

r

_o

)

(

2

_{GS t}

V v GS D

m

K

V

V

V

i

g

DSQ ds

−

=

∂

∂

=

=

In MOSFETs

In JFETs

-S

i_D I_D An almost

linear segment Slope = g_m

i_d t Q

















−

−

=

∂

∂

=

= p GS p DSS V v GS D m

V

V

V

I

V

i

g

DSQ ds

1

2

In JFETs

0 _{v vGS}

t

v_gs

v_OV

Small-signal parameters

+

v

g v

G

_D

r

A D D

DS D

o

V

I

I

v

i

r

∂

≈

=

∂

=

λ

1

+

-v

_gs

g

_m

v

_gs

S

r

_o

Saturation Triode

Slope = 1/r

i_D

vGS= Vt+2,0V

D A o

I

V

r

=

Slope = 1/ro

vDS

vGS≤ Vt

(cutoff) vGS= Vt+0,5V

vGS= Vt+1,0V

vGS= Vt+1,5V

Exercise:

Operation regions. Saturation

EXAMPLE

|V

_t

| = 2 V

L=10um

W=100um

λ

=0

2

/

20

uA

V

C

_ox

n

=

µ

V

_DD

= 10 V

V_D R I_D

a) Design the circuit in order to obtain a I

_D

=0.4mA

Exercise:

Operation regions. Triode region

EXAMPLE

V

_DD

= 5 V

K = 0.5 mA/V

2

|V

_t

| = 1 V

V

_DD

= 5 V

V_D= 0,1 V R

I_D

a) Design the circuit for obtaining V

_D

=0.1V

Proposed exercise

Example

V_DD= +10V

K = 0.5 mA/V

2

|V

_t

| = 1 V

R_G2= 10 MΩ

R_G1= 10 MΩ

R_S= 6 kΩ

R_D= 6 kΩ

a) Analyse this circuit and calculate the voltage in every node and

the current in every line