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Electrical Parameters Extraction of CMOS Floating-Gate Inverters

Extracción de parámetros eléctricos de inversores

CMOS de compuerta flotante

Molinar-Solís J.E.

Universidad Autónoma del Estado de México E-mail: Jemolinars@uaemex.mx

Ponce-Ponce V.H.

Centro de Investigación en Computación Instituto Politécnico Nacional, México

E-mail: vponce@cic.ipn.mx

R.Z. García-Lozano

Universidad Autónoma del Estado de México E-mail: zolagarcia@yahoo.com

Díaz-Sanchez A.

Instituto Nacional de Astrofísica, Óptica y Electrónica INAOE Tonantzintla, Puebla

E-mail: adiazsan@inaoep.mx

Rocha-Pérez J.M.

Instituto Nacional de Astrofísica, Óptica y Electrónica INAOE Tonantzintla, Puebla

E-mail: jmr@inaoep.mx

(Recibido: septiembre de 2008; aceptado: julio de 2009)

Abstract

This work provides an accu rate meth od ology for extracting the floating-gate gain factor g , of CMOS floating-gate inverters with a clock-driven switch for accessing tempo rarilly to the floating-gate. With the meth od ology proposed in this paper, the

gfactor and other para sitic capac i tances coupled to the floating-gate can be easily extracted in a mismatch-free approach. This param eter plays an impor tant role in modern analog and mixedsignal CMOS circuits, since it limits the circuit perfor mance. Theo ret ical and measured values using two test cells, fabri cated in a stan -dard double poly double metal CMOS AMI-ABN process with 1.2mm design rules, were compared. The extracted param e ters can be incor po rated into floating-gate PS pice macromodels for obtaining accu rate elec trical simu la tion.

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Resumen

En es te tra ba jo se brin da una me to do lo gía pre ci sa pa ra la ex trac ción del fac tor de ga nan cia g

de la com puer ta flo tan te en in ver so res CMOS, que cons tan de un in te rrup tor pa ra ac ce der tem po ral men te a la com puer ta flo tan te. Con la me to do lo gía pro pues ta, el fac tor g y otras ca pa ci tan cias pa rá si tas aco pla das a la com puer ta flo tan te pue den ser ex traí das. Estos pa rá me tros son de mu cha im por tan cia, ya que jue gan un pa pel im por tan te en el de sem pe ño de cir cui tos ana ló gi cos y de se ñal mix ta. La com pa ra ción en tre cálcu los teó ri cos y si mu la cio nes es he -cha uti li zan do dos cel das de prue ba fa bri ca das de tec no lo gía AMI ABN de 1.2mm, a tra vés de la or ga ni za ción MOSIS. Los pa rá me tros ex traí dos pue den ser in cor po ra dos a macromodelos en PSpice para obtener simulaciones más precisas.

Des crip to res: in ver sor de com puer ta flo tan te, NeuMOS, com puer ta flo tan te.

Intro duc tion

The CMOS float inggate in vert ers with mul ti ple in puts have be come a use ful cir cuit block in mod ern an a

-log and mixed-sig nal cir cuit de sign. A CMOS float

-ing-gate in verter is a typ i cal CMOS in verter with two or more in put ca pac i tances cou pled to the float ing gate (FG), which is com mon to both N and P chan nel en -hance ment MOSFET tran sis tors which are con nected in the drain mode. The po ten tial in duced in the FG can

be con trolled as a weighted lin ear sum, in volt

-age-mode, of all in put sig nals. The po ten tial of the FG

es tab lishes the on-off state of the CMOS in verter

(Shibata et al., 1992-1993).

Dis charg ing of the FG is com monly re quired but also, for many ap pli ca tions, it is de sir able to pre-charge

the FG to a given bias volt age. Dis charg ing and

pre-charg ing the FG can be achieved by us ing an an a log switch that con nects tem po rally the FG to an ex ter -nally ap plied po ten tial (VRES). By us ing an ex ter nal volt -age VRES = 0V, the FG can be dis charged and the typ i cal UV eras ing tech nique can be avoided (fig ure 1). This con cept has been in tro duced first in (Kotani et al.,

1995-1998) and was named as clocked-con trolled

NeuMOS in verter, but it will be re ferred as clock

-ed-con trolled FG-CMOS in verter.

The FG gain fac tor g, de ter mines the max i mum in -put con tri bu tion to the FG po ten tial. For n ca pac i tive in puts it is expressed as:

g = C

C i i

n

T =

å

1 (1)

Where CT is the to tal ca pac i tance in clud ing par a sitic ca pac i tances. The phys i cal char ac ter iza tion of the FG

gain fac tor g, also known as the ca pac i tive cou pling co -ef fi cient, and the par a sitic ca pac i tances cou pled to the FG, is a fun da men tal step in the de sign of high per for mance FGCMOS based cir cuits, since the de vice be -hav ior strongly de pends on these val ues. The strat egy fol lowed in this work con sists in com par ing some fea tures of the tran sient be hav ior in the “re set” and “eval u -a tion” pe ri ods. One -ad v-an t-age of this -ap pro-ach is th-at the ex trac tion of the above men tioned pa ram e ters can

be done to the FG in verter with out the use of a

“dummy cell” (Mondragón et al., 2000), re sult ing in an

ac cu rate mis matchfree tech nique, and whose eval u a

-tion will be dem on strated by comparing theoretical

and measured results in the next sections.

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Clock-contro lled FG-CMOS inverter

Elec trical charge and poten tial in the FG using an ideal analog switch

The elec tri cal equiv a lent cir cuit for the FG in verter show ing the con trol and rel e vant par a sitic ca pac i tances is shown in fig ure 2.

Ac cord ing to fig ure 1, the to tal charge stored in the FG, QFG is given by:

QFG =CFSN(VRES-VSN)+CFBN(VRES-VBN)+CFDN

(VRRES -VDN +CFSP(VRES -VSP)+CFBP(VRES -VBP)

+CFDP(VRES-VDP)+COXN(VRES-fSN -VBN)+COXP

(VRES SP VBP) C (VRES Vx) C Vi( RES Vi)

i n

poly

- - + - +

-=

å

f

1

(2)

where Ci, is the ca pac i tance be tween the FG and the in -put node i, Vi is the ithin put volt age, VDN, VDP, VSN, VSP and VBN, VBP are the drain, source and sub strate volt -ages for the NMOS and PMOS tran sis tors, re spec tively. From now on, the right side sub scripts N and P will de

-note NMOS and PMOS, re spec tively. CFDN, CFDP and

CFSN, CFSP are the over lap ca pac i tances be tween the FG and the drain or source, re spec tively. CFBN and CFBP are the over lap ca pac i tances be tween the FG and the bulk

along the edge of the chan nel, COXN and COXP are the

gate ox ide ca pac i tances, CDEPN and CDEPP in fig ure 2, are

the de ple tion layer ca pac i tances, which can be ne

-glected af ter the chan nel be gins to form un der the

float ing gate (Shibata et al., 1993). Po ten tials fSN and fSP rep re sent the sur face po ten tial of the sil i con sub -strate. Cpoly is the par a sitic ca pac i tance be tween the FG (polysilicon back-plate) and the be low sub strate layer tied to a Vx po ten tial. In this case, for a P- sub strate Vx =

GND. Po ten tial VRES is the volt age trans ferred to the FG through the switch. All volt ages in (2) are rel a tive to sub strate.

It is as sumed that no charge in jec tion and no charge leak age oc cur dur ing de vice op er a tion. Then, from the charge con ser va tion law on the FG, (2) can be sim pli fied and re ar ranged to ob tain an ex pres sion for the po

-ten tial on the FG, VFG, when the ini tial net charge is

zero, this is given by:

V

C C V V C

FG

T i i

N

i i FPD

(t+ )= é (t+ )- ( )t

ë ê

ù û ú+ =

å

1 1 1

1

[VDP(t+ )-VDP( )]t +CFDN[VDN(t+ )-VDN( )]t ù û ú

1 1 +

VRES( )t (3)

where the po ten tials at the re set pe riod are rep re sented by (t), this is, when the re set switch is closed, and the po ten tials at the eval u a tion pe riod rep re sented by (t+1), when the switch is open. In (3), Vi(t+1)rep re -sents the ith in put volt age dur ing the eval u a tion pe -riod, and Vi(t) is the ith in put volt age ap plied dur ing the re set pe riod. The re main ing po ten tials terms, cou -pled to the FG do not con trib ute with charge in both

(4)

pe ri ods, but their as so ci ated ca pac i tances con trib ute to form CT, which is de fined as the sum of all ca pac i tances cou pled to the FG as fol lows.

CT Ci C C C C C C

i n

FSN FBN FDN FSP FBP FDP

= + + + + + +

=

å

1

+COXN +COXP (4)

Poten tial in the FG using a real analog switch

For prac ti cal im ple men ta tions, a sin gle N-chan nel

MOSFET can be used in stead of the SW el e ment as

shown in fig ure 2. In fig ure 3, an equiv a lent cir cuit for the FG in verter us ing a real switch is in tro duced.

If the ac cess switch tran sis tor (SW) is ni cut off re -gion, a sim plest elec tri cal equiv a lent cir cuit for the FG po ten tial can be ob tained (Ramírez et al., 2004), fig ure 4, where all the in puts are tied to gether and form a sin -gle in put ca pac i tor CIN, CIN = C1+…+Ci+…+Cn. Ca -pac i tance COUT rep re sents the sum of CFDP and CFDN. The Cpi ca pac i tor is the ith par a sitic ca pac i tance that cou ples the FG to a DC volt age VDCi.

Here, the ideal di ode el e ment mod els the N+/P par a

-sitic drain-bulk junc tion, as so ci ated to the ac cess switch tran sis tor (SW) in cut off and Rleakis an ap prox i

-ma tion to the non-linear leakage resistance of this

junction.

The in put VIN volt age con tri bu tion to the FG po ten -tial can be ob tained through the so lu tion of a sim pli fied cir cuit (fig ure 5a).

Rleak VDCn

VDC1

FG VDCi

Cp1 Cpi Cpn

CFDN CFDP

VDD

VOUT

V1 C1

Vi Ci

Cn

Vn Ideal

Diode

COUT

VOUT CIN

Rleak FG

VIN

VDC1 VDCi

Cp1 Cpi

VDCn

Cpn

Ideal Diode

Figure 3. Equi va lent circuit for a multiple-input FG-CMOS inverter using a N-channel MOSFET as a real analog switch

(5)

where the ca pac i tance CT’ is de fined as CT’=CT - CIN. By con duct ing a Thevenin re duc tion to the cir cuit, the clamp ing cir cuit in fig ure 5b is ob tained. For any pe ri od i cal and con tin u ous volt age sig nal ap plied to the cir -cuit, VIN =AIN f1(t+nT) with am pli tude AINand pe riod

T, such that T << RleakCT, fig ure 5c, the FG po ten tial due only to this in put-sig nal, fig ure 5d, will be given by:

V C C V C C A FG input IN T IN IN T IN

| = + . (5)

The same anal y sis holds for the cor re spond ing con tri bu tion on the FG po ten tial as a func tion of a pe ri od i -cal out put sig nal VOUT=AOUT f2(t+nT), cou pled to the

FG through COUT, as follows:

V C C V C C A FG output OUT T OUT OUT T OUT

| = + . (6)

For the DC con tri bu tion, the fol low ing an a lyt i cal time-do main ex pres sion for the FG po ten tial is ob tained:

V t C V

C V e

FG DC VRES

pi DCi

T

RES i

n

t Rle

( )| , ( / =æ + è ç ç ö ø ÷ ÷ =

1

akCT). (7)

The global ex pres sion that mod els the FG po ten tial will be ob tained by sum ming equa tions (5), (6) and (7), this is:

VFG =VFG VIN| +VFG VOUT| +VFG DC VRES| , (8)

Dur ing the eval u a tion pe riod, the terms as so ci ated

to DC po ten tials cou pled to the FG, van ish for

t>>RleakCT. This means that the in duced DC-charge on the FG at cir cuit startup and the re set-charge due to

VRES, will be swept out dur ing the eval u a tion pe riod, af -ter sev eral cir cuit-time con stants RleakCT. There fore, in steady-state, the FG po ten tial will be:

V C C V C C V C C A C C A FG IN TOT IN OUT TOT OUT IN TOT IN OUT TOT OU

= + + + T

(9)

By de riv ing equa tion (9)with re spect to time, the fol low ing ex pres sion is ob tained

d d d d d d V t V t V t FG IN par OUT

=g +g , (10)

where, g=CIN/CT is the FG gain fac tor and gpar=

COUT/CT would cor re spond to a par a sitic FG gain fac tor due to the feed back of the FGMOS in verter’s out put volt age on the FG.

In re set mode, ap ply ing a di rect sig nal to the FG, i.e. a sawtooth, the slope of the in verter trans fer char ac ter -is tic as so ci ated to the cir cuit shown in fig ure 6a, -is given by: CT Rleak FG C C IN T Ide al Diode VIN CIN Rleak FG VIN Ideal Diode

C ´T

a) b)

V

IN

t

A

IN

V

FG

t

A

IN CIN CT CIN CT

(VIN+AIN)

c) d)

(6)

A V t

t V VR

OUT

FG =d ×

d d

d .

(11)

In a sim i lar way, as il lus trated in fig ure 7a, the slope of the trans fer char ac ter is tic, when the cir cuit op er ates in the eval u a tion pe riod, is given by

A V

t t V VE

OUT

IN =d ×

d d d

(12)

Now sub sti tut ing (11) and (12) in (10), the fol low -ing re la tion is ob tained:

g= A -g

A A

VE

VR

par VE

(13)

Where, the slopes AVE and AVR can be eas ily mea -sured in or der to ex tract the pa ram e ters g and gpar.

Figure 6. Measu re ment in the reset period. (a) Applying a saw-tooth voltage signal (VIN) directly to the FG

terminal by using the access switch. (b) Graph of the inver ter’s output tran sient response

Figure 7. Measu re ment in the evalua tion period (SW in cut off). (a) Applying a saw-tooth voltage signal (VIN) to all input

capa ci tors. (b) Graph of the inver ter’s output tran sient response

VDD

VOUT C1

C2

C3

VIN

SW VDD=5V

HIGH GAIN REGION LOW GAIN

REGION

vd dt o ut

vd dt IN

vd dt OUT

VDD

VOUT C1

C2

C3

VIN

SW VDD=5V

a) b)

HIGH GAIN REGION LOW GAIN

REGION

vd dt

o ut

vd dt

IN

vd dt

OUT

(7)

Extrac tion metho do logy

The ba sic idea that sup ports the ex trac tion meth od ol ogy con sists in com par ing the in verter tran sient re -sponse ob tained in the re set pe riod with that ob tained dur ing the eval u a tion pe riod. The ex trac tion meth od ol -ogy is pre sented next as a se quence of six steps:

Step 1. A mea sure ment dur ing the re set pe riod of

AVR is taken around a fixed point in VIN which cor re -sponds to a low-gain slope of the out put char ac ter is tic (VOUT), (fig ure 6b).

Step 2. A mea sure ment dur ing the eval u a tion pe riod of AVE is taken around the same point of step 1, (fig ure 7b).

Step 3. Pa ram e ter g is cal cu lated us ing (13). The sec -ond term of the right side of this equa tion is neg li gi ble in the low-gain re gion due to gpar<g and since AVE is small, then, g ap proaches to

g » A A

VE Step

VR Step |

|

2

1 (14)

Step 4. A mea sure ment dur ing the re set pe riod of AVR is taken at a fixed point VINnear the switch ing-point of

the in verter, which cor re sponds to a high-gain slope of the out put char ac ter is tic, (fig ure 6 b).

Step 5. A mea sure ment in the eval u a tion pe riod of

AVE is taken at the same point of step 4, see fig ure 7b.

Step 6. From (13), gpar is cal cu lated us ing the val ues ob tained in the steps 3, 4 and 5, by us ing

gpar g

VR Step

Step

VE Step

A A

= 1

-4

3

5

|

|

| . (15)

Expe ri mental results

Two test cells were fab ri cated us ing a dou blepoly, dou

-ble-metal CMOS pro cess with 1.2mm de sign rules,

avail able through MOSIS ser vices (run: T2AH-BJ and T48S-AM). The mi cro pho to graph of each test cell is shown in fig ure 8. The first test cell cor re sponds to the cir cuit in tro duced in fig ure 6a. The sche matic di a gram for the sec ond test cell is not shown, but is a six-in put FG-CMOS in verter.

The test cells were mea sured us ing the de scribed meth od ol ogy pre sented in sec tion 3. The small-sig nal slopes were com puted by us ing a lin earfit ap prox i ma tion from data points ob tained by means of a dig i tal os -cil lo scope. Ta ble 1, shows the the o ret i cal and ex tracted val ues for g and gpar, us ing a 100 kHz saw-tooth sig nal

Table 1. Test cells elec trical charac te ris tics and theo re tical and measured floa ting-gate gain factors

Test Cell Num. Inputs Input

capacitance Aspect RatioTransistor

Measured Theoretical

g gpar g gpar

1 3 0.256 pF P=27mm/1.2mm,

N=9mm/1.2mm 0.837 6.71´

10-3 0.85 7.55´10-3

2 6 0.35 pF P=16.8mm/3mm

N=6mm/3mm 0.923 - 0.926

-Test-cell Num.2

Figure 8. Microp ho to graph of the fabri cated cells

(8)

with 5V peak-to-peak and a 2.5V off set. The pe riod of this sig nal (T=10ms) is smaller than the in trin sic cir -cuit-time con stant which nor mally is in the or der of sec onds.

Discus sion

Although the the o ret i cal ca pac i tance val ues can be cal -cu lated us ing the pro cess pa ram e ters given by the foundry, the phys i cal dif fer ences of the in put ca pac i -tances can lead to an im por tant de vi a tion of g fac tor and thus af fect ing sig nif i cantly the cir cuit op er at ing point. As an ex am ple, two iden ti cal CMOS in vert ers were sim u lated through PSpice, one of them with an in put ca pac i tance de vi a tion of 5% (fig ure 9a).

The in vert ers out puts are shown in fig ure 9b. The switch ing op er at ing point (Ja cob et al., 1998) of the in -vert ers as shown, is shifted near by 60mV with re spect the in put volt age Vin , this con di tion is un de sir able for many an a log and mixed sig nal ap pli ca tions since the re -cent low-volt age trends re quires high ac cu racy. The meth od ol ogy pre sented in this work fo cuses on CMOS float ing-gate cir cuits with a clock-driven switch at the

FG, and rep re sents a good choice when the g fac tor

must be de ter mined ex per i men tally for high ac cu racy re quire ments.

Acknow led ge ments

Mex ico State Au ton o mous Uni ver sity (CU

UAEM-Ecatepec), In ter dis ci plin ary Pro fes sional School

of En gi neer ing and Ad vanced Tech nol o gies (UPIITA-IPN) and Na tional In sti tute for As tro phys ics, Op tics and Elec tron ics, INAOE.

Refe rences

Shibata T., Ohmi T. A Func tional MOS Tran sistor Featu ring Gate-Level Weighted Sum and Thres hold Opera tions. IEEE Trans. on Elec tron Devices, 39(6): 1444-1455, 1992. Shibata T., Ohmi T. Neuron MOS Binary-Logic Inte grated

Circuits Part I: Design Funda men tals and SoftHard -ware-Logic Circuit Imple men ta tion. IEEE Trans. on Elec -tron Devices, 40(3):570-576, 1993.

Kotani K., Shibata T., Imai M., Ohmi T. Clocked- Neuron-MOS Logic Circuits Emplo ying Auto-Thres hold-Adjust ment. On: IEEE Inter na tional Solid-State Circuits Confe rence ISSCC95, 1995, pp. 320-322.

Kotani K., Shibata T., Imai M., Ohmi T. Clock-Contro lled Neuron-MOS Logic Gates. IEEE Trans. on Circuits and Systems- II: Analog and Digital Signal Proces sing, 45(4): 518-522, 1998.

Mondragon-Torres A., Shneider M., Sanchez-Sinencio E. Extrac tion of Elec trical Para me ters of Floa ting Gate Devices for Circuit Analysis, Simu la tion, and Design. On: The 2002 45th Midwest Sympo sium on Circuits and Systems, 2002.MWSCAS-2002, Vol. 1, 2000, pp. 311-314. Shibata T., Ohmi T. Neuron MOS Binary-Logic Inte grated Circuits Part II: Simplif ying Tech ni ques of Circuit Con -fi gu ra tion and their Prac tical Appli ca tions. IEEE Trans. on Elec tron Devices, 40(5):431-434, 1993.

Time

0s 2.5us 5.0us

V(C1:1) V(Q1:d) V(Q2:d) V(Q6:g)

0V 2.5V 5.0V

Vpulse

Vin

Vout1

Vout2

a) b)

(9)

Ramirez-Angulo J., Lopez-Martin A., Gonzalez-Carbajal R., Muñoz-Chavero F. Very Low-Voltage Analog Signal Proces sing Based on Quasi-Floa ting Gate Tran sis tors. IEEE Journal of Solid State Circuits, 39(3):434- 442, 2004. RamirezAngulo J., GonzálezAlta mi rano G., Choi S.C. Mode

-ling Multiple-Input Floa ting-Gate Tran sis tors for Analog Signal Proces sing. On: Inter na tional Sympo sium On Cir -cuits and Systems ISCAS’97, Vol. 3, 1997, pp. 2020-2023.

Guan H., Tang Y.S. Accu rate and Effi cient Models for the Simu la tion of Neuron MOS Inte grated Circuits. Inter na -tional Journal of Elec tro nics, 87, 2000, pp. 557-568.

Jacob-Baker R., Li H.W., Boyce D.E. CMOS Circuit Design, Layout and Simu la tion. IEEE Press series on Microe lec tronic Systems. USA. 1998.

About the authors

Jesús Ezequiel Molinar-Solis. Was born in Chihuahua, Mexico, in 1976. He received the elec tro nics engi nee ring degree from the Tech no lo gical Insti tute from Ciudad Guzman (ITCG), Jalisco, in 1999. He obtained the M.Sc. and Ph.D. degrees in elec trical engi nee ring at the Center for Research and Advanced Studies (CINVESTAV-IPN), Mexico City, in 2002 and 2006 respec ti vely. He is currently working as a Titular Professor with the Mexico State Auto no mous Univer sity (UAEM) at Ecatepec, Estado de Mexico, his research inte rests are related to analog circuits, neural networks and vision chips.

Victor Hugo Ponce-Ponce. Received the B. Tech. degree in elec tro nics engi nee ring from the Supe rior School of Mecha nical and Elec trical Engi nee ring (ESIME) of the National Poly technic Insti tute (IPN) of Mexico, in 1993, and the M. of Sc. and Ph.D. degrees in elec trical engi nee ring from Center for Research and Advanced Studies (CINVESTAV-IPN) at Mexico City, in1994 and 2005, respec ti vely. He is currently working as Professor at the Computer Research Centre CIC-IPN. His research inte rests include CMOS design circuits and vision sensors.

Rodolfo Zola Garcia-Lozano. Was born in Mexico City, Mexico in 1973. He received the elec tro nics engi nee ring degree from Tech no logic of Advanced Studies from Ecatepec (TESE), Mexico in 1996. He obtained the Ph.D degree in Elec trical Engi nee ring at the Center of Research and Advanced Studies (CINVESTAV-IPN), Mexico City, in 2005. He is currently working as a Titular Professor with the Mexico State Auto no mous Univer sity (UAEM) at Ecatepec, Estado de Mexico. His research inte rests are related to elec tro nics circuits and thin film devices appli ca tion.

Alejandro Díaz-Sánchez. Received the B.E. from the Madero Tech nical Insti tute and the M.Sc. from the National Insti tute for Astroph ysics, Optics and Elec tro nics, both in México, and the Ph.D. in Elec trical Engi nee ring from New Mexico State Univer sity at Las Cruces, NM. He is actually working as Full Professor at the National Insti tute for Astroph ysics, Optics and Elec tro nics, in Tonant zintla, Mexico. His research concerns analog and digital inte grated circuits, high perfor mance computer archi tec tures and signal proces sing.

Figure

Figure 1. Elec trical Diagram of a Clocked-Contro lled FG-CMOS Inverter
Figure 2.  Elec trical equi va lent circuit for a FG-CMOS inverter with an ideal analog switch (SW)
Figure 3. Equi va lent circuit for a multiple-input FG-CMOS inverter using a N-channel MOSFET as a real analog switch
Figure 5. (a) Simpli fied circuit. (b) Thevenin reduc tion. (c) Perio dical input. (d) V IN  contri bu tion to the FG poten tial, V FG
+4

Referencias

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• FPD: Field-Programmable Device: Also known as PLDs (Programmable Logic Devices), the FPDs are integrated circuits utilized to implement digital hardware with the

y la mujer sentada en la proa del barco. de la mujer con los ojos cerrados. Al comienzo de Limite, todas las imágenes se encadenan a través de fusiones y este encadenamiento refle-