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Implementación de un conformador de haz tipo delay-and-sum sobre un dispositivo FPGA

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Academic year: 2017

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Figure

Figure 1.1: Estimation of the intensity of the signal in a fixed point, by means of the delay-and-sumbeam-forming algorithm.
Figure 2.1: System Arquitecture: Data Acquisition module with 4 microphones and filters, a 4-channel ADCwith SPI interface, Beamformer modules, TFT-Display to visualize the estimation of the intensity of thesound waves.
Figure 2.2: Overall system architecture and external peripherals, the blocks in blue correspond to FPGAimplemented blocks, and the blocks in green correspond to external peripherals
Figure 3.1: Implementation of the beamforming algorithm. sprocessed. Oncecorresponding channel n of the ADC,n[k] are the sampled data obtained from the δ0i is the delay that indexes over the buffer the datum that has to be s(p)[k] is obtained, it is multiplied by the corresponding hi coefficient of the filter and thenaccumulated until i=L-2, when the 9 most significant bits address the corresponding color in the colorlook-up table to store it in an external double buffer.
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