PRESENTA EL INFORME CORRESPONDIENTE

UNIVERSIDAD AUTONOMA METROPOLITANA

DIVISION

DE

CIENCIAS BASICAS

E

INGENIERIA

I N G L U I S

CASTRO CAREAGA.

COORDINADOR DE

LA

CARRERA

DE

I NGENI ERI A EN ELECTRON1 CA

POR MEDIO DE LA PRESENTE, LOS SUSCRITOS

DESEAN

HACER

DE

S U CONOCIMIENTO

QUE

EL C.

ARTURO NOGUERA

VELAZQUEZ

,

ALUMNO DE

LA

CARRERA

DE

I N G E N I E R I A

EN

ELECTRONICA,

CON

ESPECIALIDAD

EN

COMPUTACION. ASESORADO POR

C.

PROFESOR J U A N CARLOS SANCHEZ

GARCIA,

PRESENTA EL INFORME CORRESPONDIENTE

A LA SEGUNDA PARTE

DEMON1 NADO

"PROGRAMADOR

UN1

VERSAL

D E MEMORIAS EPROM"

CON ACREDITACI ON

A

LA MATER1

A

DE

PROYECTO

DEL PROYECTO

TERM1 NAL

I I

PARA

LO CUAL

,

EN

S U OPORTUNIDAD

,

NOTIFICAMOS A ESA COORDI NACION.

AGRADECIENDO DE ANTEMANO

S U

ATENCION

Y

SI

N

M A S

POR

EL MOMENTO, NOS

E S

GRATO EXTENDERLE

UN CORDIAL SALUDO.

A S E S O R

ARTURO NOGUERA

VELAZQUEZ

C .

C. PROF J U A N CARLOS SANCHEZ

GARCI A. PROFESOR ASESOR

C. C. INTERESADO.

_I

_?

P

R

O

Y

E

C

T

O

T

E

R

M

I

N

C

I

L

I

1

A P E N D I C E

A

M A G R A M A E L E C T R I C O D n _ ~ A R € I ~ ~ .

PRWRAMAD~R

UNIVERSAL

DE EPROMS

NOVASOFT

89

c

VERSION 1 . 2

~~

+

T

-

A P E N D I

C E

B

t " E C N C A S D E L A P I A M C 6 8 2 l

PERIPHERAL INTERFACE

ADAPTER C

P I A >

MC6821

MOTOROLA.

@

MOrOROLA

FIGURE 18 - EXPANDED BLOCK DIAGRAM

C A I

C A l

P A 0

P A 1

P A 2

P A 3 P A 4

P A 5

P A 6 P A 7

1 4 P B 4

1 5 PB5

t 16 P B 6

17 P B l

I I

MC6821

.

MOS

IN-CHANNEL, SILICON-GATE. DEPLETION LOAD1

PERIPHERAL INTERFACE ADAPTER

CERAMIC PACKAGE L SUFFIX CASE 715

P SUFFIX PLASTIC PACKAGE

CASE 711

A P E N D I C E

C

HOJASTECNCASDEL4SFEMOWASEPROMDELAFAMUAIMEL

__ .

-

. . P R O G R A M M ~ O P t R A l I O N l l M l N G DIAGRAM

MCM2716

J

I

MOS

IN-CHANNEL. SILICON-GATE1

2 W 8 x S B l T '

UV ERASABLE PROM

PIN ASSIGNMENT

3 8

. .

VPPU- vpp VPPL-

PROGRAMMING INSTRUCTIONS

Before programmrng. the memory should ta submitted lo

a lull ERASE operatton to ensure every bit In the devics ir in

the "1" stale Irepresented by Output Highl. Data ara enlered

bv programmrng zeros IOutput Low1 inlo the required bits. opmatton A progtamrned "O' can only be changed lo a "1"

?he words ere addtessed the same way es in (he READ by ulwavoolel ImJhl erasure.

To set the memory up for Program Mode, Iha Vpp input

IS the sama as lor !he Read operelion and t i t et VIH. Pro-

l P m 211 should be rolsed to

+ 25

V . The V c supply voltage

gtammlng data is entered In 0bi1 words through the dala out 1001 termonels Only "O S" will be programmed when "O's"

and " 1 S" are enrered in the 8brl data word.

V l ~ l 19 applved to the ElProgr input. A program pulse is ap-

After address nnd _{cata setup. a} program pulsa (VIL to plmd to each address location to be programmed. To

minlmlza programming l i m e . a 2 ms pulse width is rocom-

mended. Th4 marrmum program pulsa width is 55 ms;

lherelora. programmkg musl not be attompled with a dc

srgnal applied to the ElProgr input.

Multiple MCM2716s may be programmed in parand by connecting tyether hka inputs and applying the propiam pulse to the ElProgr inputs. Dillerenl dala may be program- med Inlo multlplo M C M 2 7 l k connrc1.d In paralld by uslng

the PROGRAM INHIBIT mode. Except I w the f?/Progr pin.

a11 ltka inputs lrncluding Output Enable) m y be common.

The PROGRAM VERIFY mode with V p p et 25 V is used IO

determlne the! all programmed bits were wrrecllv program- med.

READ OPERATION

k

moda. With llable system addr-. effectivdy h t N K -

,

Alter IWIS time. date ir valid et the outputs in t h e READ

w time can be obtained by gating t h e dala onlo the bo,

with Output Enable.

dissipalion. The outputs are In the high impedancs Stat@

The Standby moda is available lo r e d u c e activa

Porn,

when t h e ElProgr input pin is high IVIH) independen1 of t h .

Outpur EneMe input.

ERASING INSTRUCTIONS

The MCM2716 can be erasad by exposure to hiQh iotm.dV-

shortwave ultraviolel light. m t h a wovelength of 2537

sngs~roms. The recommended mtsgrated do- li .e.. UV- intensity X arposurs time) is 15 W s l u n 2 . A S an e ~ ~ n p b , vt

ing the "Model UV-Eraser ITumer Designs. Mow+

lain View. C A 9 4 0 4 3 ) the ERASE-ttma is 36 minutes. The lamps should be usad without shortwave lillen and th. MCM2716 should be posilioned about one inch w a y f r o m

I h e u v - c u b .

RECOMMENDED OPERATING PROCEDURES Altar efasura and faprogramming of the EPROM. ¡I U tocommended that the quam window be cowred with an opsqua ~ e l f - e d h & w cover. It is important t h a t r h e s e l f -

& h a o w cover n o t bnw any residua on the quartz if il ir

removed to allow anothm er~sufa. RECOMMENDED PROGRAMMING OPERATING CONDlTlONS '

PU" _S- Mh Horn M u ur*

S u d v Vd- VCC.VPPL 4

=

50. 5 2s V

VppH 24 15

m

tnpul Hvh Vdtaps lor Det.

Y o 0

-

-0,l

VIL Input Corr Volupa for Oat.

v vcc + t - I ? VIH

AC PROGRAMMING OPERATINO CONDITIONS AND CHARACTERISTICS

2732A

32K

(4K

, . - , : .

x 8)

UV

ERASABLE

PROM

I

200'ns'(2732A-2) Maxlmum

Access

. , * B

Industry Standard Pinout..

.

JEDEC

.

Tíme

.'

I.

HMOs*-E Technology

.

', 1

'

', .

Approved

. : I . { ' ,

, 1 : . ..* I,.' . ' .I. ,

I

Compatible with High-speed 8mHz

=

Low Standby Current

...

30.

mA

Maxlmum

N o

Llne Control

I

Compatibie with 12 MHz 8051 Famiiy

.

IAPX

186

...

Zero WAIT

State

,

, .

# S . , * '

.

m

~ 1 0 " / V ~ ~ T o i e r a n c e A v a i i a b i e ~ . : - ~ ! ~

.-

:.'*

Int,ligent IdentifierTY Mode

.. .'

-

.

.

.

.

.-

-

m

TTL

Compatible

.-

r * * , _

. . .

The Intel 2732A Is a 5V only, 32,768 bit ultraviolet erasable and electrically programmable read-onlymemory (EPROM). The standard 2732A access time is 250 ns with speed selectlon (2732A-2) available at 200 ns.The access time is compatible wlth high performance microprocessors such as the 8

MHz

IAPX 186. i n these systems, the 2732A allows the microprocessor to operate wlthout the addition of WAIT states.

An Important 2732A feature is the separate output control, Output Enable(=), from the Chip Enable con-! troi

(m).

The =control eliminates bu$ contention in microprocessor systems. Intel's Application Note:

AP-72 describes the microprocessor system implementation of the

m

and

m

controls on Intel's. EPROMs. AP-72 is available from Intel's Literature Department.

The 2732A has,a standby mode which reduces power consumption without increasing access t h e . The: maxlmurn active current Is 125 mA, while the maximum standby current is only 35 mA, a 70% savlng.The standby mode is selected by applying the TTL-high slgnai to the

m

Input.

~.

The 2732Ais fabricated with H M O s - E technology, Intel's high-speed N-channel MOS Silicon GateTechnoiogy.'

, . . . . -. . _{. - . I}

.

_.

s .

. .

. I

. . . . .I

.

. .

vcc,- DATA OUTPUTS 0 0 - 0 7

T

I

J

. .

. "~~ . Flgure 1. Block Dia!aram---.".

,GRAMMINO WAVEFORMS

NOTE%

I ALL 71uEs SHOWN IN I ARE MINIMUM AND IN rdEC UHLEJS OTHERWISE SPECIFIED.

2. TllE INPVT TlUlNQ REFERENCE LEVEL IS O 8V FOR A VIL ANO N FOR A VIH.

I

. -

i t

2764

64K (8K

x

8) UV ERASABLE PROM

1

ns (2764-2)

Maximum

Access

m

Intellgent

Programmlng'" Algorithm

le

. .

.

HMOs*-E

Technology

.

.

industry

Standard

Plnout

.

.

$EDEC

mpatlble with High-speed 8mHz

Approved

'X

186

...

Zero

WAIT

State

LOW

A c h e

Current

...

lOOmA Mew:

o

Llne Control

I

Compatible

to 27128

EPROM

. I

TTL

Compatible

. : I

*

*'

'

, , ,

, . _{. .}

I2764 is a 5V only, 65.536-bit ultraviolet erasable and electrlcally programmable read-only memory (EPROM). The I2764 access time Is 250 ns wlth speed selection available at 200 ns. The access time is compatible with high- mce microprocessors such as Intel's 8 mHr IAPX 186. In these systems. the 2764 allows the microprocess?r to

wllhout the addltion of WAIT states. The 2764 Is also compatible wlth the 12 MHz 8051 lamily.

riant 2764 feature Is the separate output control, Output Enable

(m)

from the Chlp Enable control

(m).

The eliminates bua contention In micro rocessor systems. Intel's Appllcatlon Note AP-72 describes the bcessor system implementation of the

h

and

m

controls on Intel's EPflOMs. AP-72 Is avaliable from Intel's

e Department. I . , " 5

i has a standby mode whlch reduces power consumptlon~wlthout increasing access time. The maximum acllve

S 100 PA, whlle the maximum slandby current is only 40 mA. The standby mode is selected by applying a TTL- ?al to the input. - .

:c

tolerance is available as an alternative to the standard ~ 5 X V C ~ ~ t o l e r a n c i for the2764. This can allow the system more leeway with regard to his power supply requirements and other system parameters. . .

.Is fabricated with HM0S'-E technology. Intel's hlgh-speed N-channel MOS Slllcon Gate'lechnoiogy.

.

_.

.

. . . .

2764

,

UD'*

m , U M p l l Y Y l r " . I I I I . m ~ ~ ~ , ~ ~ " ~

Figure 1. Block Diagram . - N . # L v n m 7 ~ n m m

.

. . . . .

. .

MODE SELECTION Figure 2. Pin Configurations . . . "

.

- - - . ..

\

4 P R W R L M _VERIFY c

..

e,

-

, ..

b..

. , V.., L

MORESSE8

_.

_.., AODREBB 6TABLL

1 DATA W VALID

V. t

-

h

-

. . ___c

"

I on b VIH OT VIL

h" . . -

'n

-

12mt O d V 1. ,.- I .1 ,, DATA

DATA IN SIABLE Hbh I DNA OUT VALID ,

'

.

"""

-

- .

u, t "

-h-

*h-

4 " 3 " )

I

(DFP Ax

;

:

_ .

v,

.

: v"-c[$-

. .

y. _{.. -...}

a K

. I '

..

- 9 -

.

I .

I.

~ .

V,

FQX4

Y :

.

, . . V,

- .

6s

. -. Y . . "" . - -. -.

1 . ALL TIMES SHOWN IN 1 ]ARE MINIMUM AND IN pSEC UNLESS OTHERWISE SPECIFIED. 2. THE INPUT TIMING REFERENCE LEVEL IS .BV FOR VIL AND 2V FOR A VIH

3. IOE AND t ~ARE CHARACTERISTICS OF THE DEVICE BUT MUST BE ACCOMMODATED ~ p BY THE PROGRAMMER

4 WHEN PROGRAMMING THE 2764, A O.lpF CAPACITOR IS REOUIRED ACROSS Vpp ANO GROUND TO SUPRESS \

SPURIOUS VOLTAGE TRANSIENTS WHICH CAN DAMAGE M E D M C E .

271

20

128K

(16K

x

8)

UY.ERASABLE

PROM

IARD PROGRAMMING WAVEFORMS

250 ns Maxlmum

Access Time..

.

H

Industry Standard Pinout.. .

JEDEC

,

HM0S'-E Technology

i .

Approved

. .

Compatlbie with Hlgh-Speed 8 MHz

'

10%

Vcc

Tolerance Available

. .

,

.

\.

L .

IAPX 186

...

Zero WAIT State

H

TwoLlne Control

Low

Active Current..

. l o 0

mA

Max.

1 1

Pin Compatible

to 2764 EPROM

lnteligent ProgrammlngTy

Algorithm

The Intel

27128

is a 5Vonly,

131,072-bit

ultraviolet erasable and electrically programmable read-only memory (EPROM). The standard

27128

access time is

250

ns which is compatible with high-performance microprocea-

sors such as Intel's

8

MHz iAPX

186.

In these systems the

27128

allows the microprocessor to operate withoul the addition of WAlTstates. The

27128

is also compatible with the

12

MHz

8051

family.

AAimportanJ

27128

feature is the separate output control. Output Enable

(a)

from the Chip Enable control

(CE). The OE control eliminates bus contention in microprocessor systems. Intel's Application Note AP-72 describes the microprocessor system implementation of tne

OE

and CE controls

on

Intel's EPROMs. AP-72 is

avallable from Intel's Literature Department.

The

27128

has standby mode which reduces the power consumptlon without increaslng access time. The maximum actlve current Is

100

mA, while the maximum standby current is only 40 mA. The standby mode is selected by applying a lTL-high signal to the Input.

*lo%

VCC tolerance is available as an alternative to the standard ? 5 % Vcc tolerance for the

27128.

This

CB?

1 allow the system designer more leeway with regard to his power supply requirements and other,systern

parameters. - <

The

27128

is fabricated with HMOs*-E technology, Intel's high-speed N-channel MOS Silicon'GateTechnology.

, ,

..,

.

, .

,.

.?- .

27128

NOTE INTEL UNNERSN SITE COMPAIIBLE EPROM PIW CUNFGURAlWNS ARE SUWfh W T I Y BLOU(SAIUACEN1 TOTHE 27128 PINS

Flgure 2. Pln Conflguratlons /

. .

-,

'

27256

256K

(32K

x 8).UV

ERASABLE

PROM

Yare Carrler Capablllty

Industry Standard Plnout

. . .

JEOEC

i

IS

Maxlrnum'Access Time

. '

Approved

Line Control

=

Low Power

-100

rnA max. Active

igent Identifier" Mode

-

40

rnA max. Standby

Sompatible

-Fastest EPROM Programrnlng

' i ' I .

' I

!I 27256 is a 5V only, 262,144-bit ultraviolet Erasable and Electrically Programmable Read Only (EPROM). Organized as 32K words by 8 bits. individual bytes are accessed in under 250ns. This is

ble with high performance microprocessors, such as the Intel 8MHz IAPX 186. allowing full speed In without the addition of performance-degrading WAlTstates. The 27256 i s a l s . directly compati-

Intel's 8051 family of microcontrollers. j, i ::

.

. . '

56 enables implementation of new, advanced systems with firmware intensive architectures. The stion of the 27256's high density, cost effective EPROM storage, and new advanced microproces- uing megabit addressing capability provides designers with opportunities to englneer user-

high reliability, high-performance systems. : ( . I

56s large storage capability of 32K bytes enables it to function as a high density software carrier. Entire g syslems, diagnostics, high-level language programs and specialized application software can reside in I EPROM directly on a system's memory bus. This permits immediate microprocessor access and ,n of software and eliminates

the

need

lor

time consuming disk accesses and downloads.

-

,

advanced features have been designed into the 27256 that allow for fast and reliable programmlng Ileligent identifier'" mode and the lnleligent Programming" Algorithm. Programming equipment.

es advantage of these innovations will electronically identify the 27256 and then rapidly program it n efficient programming method. .

3 control and JEDEC-approved. 28-pin packaging are standard features

of

all Intel hiah-density

Is.

This assures easy microprocessor interfacing and minimum design efforts when upgrading, or choosing between nonvolatile memory alternatives.

!56 is manufactured using Intel's advanced HMOS'II-E technology.

Itomated

operations

Intellgent ProgrammingTu Algorithm

, I

I. , . . .

.

.

. . .

A P E N D I C E

D

usTADosDELospRoGRAMAsDELsIsIEMk

" ... "

...