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Microsoft Word - Thesis v21

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Fig. goldtemperature1.2. (a) AFM image and (b) Schematic of the first CNTFETs with a semiconducting SWNT lying over two   electrodes.  (c)  I–Vbias curves  for  various values  of  the  gate  voltage  (Vgate).  Data  were  taken at  room  and in vacuum (10‐4 mbar), with the voltage applied to contacts 1 (drain) and 2 (source). Inset, conductance at Vbias = 0 as a function of Vgate. Adapted from (4). 
Figure Adapted1.3. Schematic illustrations of a top‐gated CNTFET resembling the conventional MOSFET structure. from (7). 
Figure oscillatorinput1.4. (a) AFM image of a single‐nanotube transistor where a semiconducting nanotube is contacted bytwo Au electrodes and an Al wire, covered by a few‐nanometers‐thick oxide layer, is used as a gate. (b)Schematic side view of the device. (c)Demonstration and schematics of the electronic circuits of one‐, two‐,and three‐transistor logic circuits with CNTFETs such as (A) an Inverter, (B) a NOR gate for the four possible  states  (1,1),  (1,0),  (0,1)  and  (0,0),  (C)  a  SRAM  cell  composed  of  two  nanotube  FETs  and  (D)  a  ring (11). 
Fig. (54)2.9. Cone structure of the energy dispersion relation at low energies at the six Brillouin zone corners. 
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