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Pipeline Registers Vulnerability Framework Oriented on Instruction Set Architecture Reliability Analysis

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Academic year: 2020

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Figure 5.2 – Bits in the pipeline registers, categorized by their purpose (control, data and instruction bits)
Figure 5.4 – Average vulnerable bits per pipeline register. In this group we include: and, eor, orr, bic, tst , teq, cmp, cmn
Figure 5.14 – Average vulnerability bits per pipeline registers. Instructions in this group are b, bl, swi, swap, swapb
Figure 5.15 – Average vulnerability bits per pipeline register. This graph is calculated from all the tested instruction formats
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