Charge trapping dynamics associated to MOSFET degradation: an experimetal approach with magnetic fields

(1)

(2)

Abstract

The evolution of semiconductor industry and material science has proven to be of great importance in most aspects of contemporary society. Metal-Oxide-Semiconductor (MOS) transistors in Integrated Circuits (IC) have assumed a central position in modern electronic devices as the brick units that build this gigantic industry. The integration density has grown exponentially since their introduction in the 1960s with the aim of increasing their performance. Gordon Moore identified this trend in 1965, predicting the doubling of compo-nents in each technological generation in what we know as the Moore’s Law, leading to uninterrupted and stringent efforts to comply with it. To keep track with the roadmap, we have observed technological innovations such as the shrinking of the device dimensions from the micrometer to the nanome-ter scale, the introduction of new mananome-terials in the fabrication steps and the progressive abandonment of the planar design in favor of three-dimensional (3D) structures. Regrettably, the long-term reliability of the transistor perfor-mance was compromised with the introduction of these advances. On top of that, the fundamental physical background behind the transistor’s detrimental performance is still not entirely understood but the general agreement on the explanation is defect generation during the device operation over time, partic-ularly in the semiconductor-oxide interface. These oxide charges and interface traps dynamically interacting with the semiconductor charge contribute sig-nificantly to the electrical degradation. Eventually, the simulation, modeling, and characterization of defects degrading the transistor performance became an unavoidable subject of study. In the past, as purely electrical characteri-zation techniques could not entirely explain the complex phenomena affecting either the gate-oxide or the interface between the gate-oxide and the silicon substrate, some studies have employed a second variable additionally to the electrical techniques to fill the gaps in the comprehension of trapping effects (e.g. temperature, radiation). This thesis has focused on experimentally study-ing the trappstudy-ing/de-trappstudy-ing dynamics in the semiconductor-oxide interface by

(3)

iv

introducing a second-order effect applying magnetic fields. The two main types of defects, slow (or deep) and fast (or shallow) traps, are addressed through this novel experimental approach. The coupled magneto-conductivity effect may help to gain insight in the trapping effects that lead to the degradation in the performance of the transistor, and subsequent implication in the circuit reliability.

(4)

Resumen

La evolución en la industria de semiconductores y ciencia de materiales ha probado ser de gan importancia en muchos aspectos de la sociedad con-temporánea. Los transistores Metal-Óxido-Semiconductor (MOS) en circuitos integrados (IC) han asumido un papel central en dispositivos electrónicos mod-ernos como las unidades básicas que construyen esta industria. La densidad de integración de estos dispositivos ha crecido exponencialmente desde su intro-ducción en los años sesenta, con el propósito de incrementar su rendimiento. Gordon Moore identificó esta tendencia en 1965, donde predijo el incremento de componentes al doble en cada nueva generación tecnológica, en lo que cono-cemos como la Ley de Moore, y que requiere esfuerzos constantes y rigurosos para cumplirla. Para continuar con la hoja de ruta, hemos observado algunas innovaciones tecnológicas como la reducción de las dimensiones de los disposi-tivos desde la escala micrométrica a la nanométrica, la introducción de nuevos materiales en los procesos de fabricación y el abandono gradual del diseño planar hacia estructuras tridimensionales. Lamentablemente, la fiabilidad a largo plazo del rendimiento del transistor se vio afectada con la introducción de estos avances tecnológicos. Por si fuera poco, aun no se comprende del todo la física fundamental responsable de la deficiencia del rendimiento del transis-tor, aunque hay un acuerdo general en que la explicación está relacionada a la generación de defectos durante la operación del dispositivo a lo largo del tiempo, particularmente en la interfaz óxido-semiconductor. Estas cargas en el óxido y trampas en la interfaz que interactúan constantemente con la carga en el semiconductor contribuyen a la degradación eléctrica. Era de esperar que la simulación, el modelado y la caracterización de defectos que desgastan el rendimiento del transistor se volvieran temas de estudio. Anteriormente, debido a que las técnicas de caracterización puramente eléctricas no podían explicar completamente el fenómeno que afectaba tanto al óxido de compuerta como a la interfaz con el sustrato de silicio, algunos estudios utilizaron una segunda variable adicional a la caracterización eléctrica para llenar los hue-cos que existían en los efectos de atrapamiento (temperatura, radiación, etc.).

(5)

vi

Esta tesis se enfoca en estudiar de manera experimental la dinámica de atra-pamiento/liberación de carga en la interfaz óxido semiconductor a través de la introducción de un efecto de segundo orden aplicando campos magnéti-cos. Los dos tipos principales de defectos se estudian utilizando esta novedosa aproximación experimental: trampas "lentas" (o profundas), y "rápidas" (o superficiales). El efecto combinado de magneto-conductividad podría ayudar a comprender mejor los efectos de atrapamiento que llevan a la degradación del rendimiento del transistor, y sus consecuencias en la confiabilidad a nivel circuital.

(6)

Acknowledgements

Me gustaría agradecer al Consejo Nacional de Ciencia y Tecnología (CONA-CyT) por haberme otorgado la beca durante mis estudios de doctorado.

Quisiera expresar mi gratitud principalmente al Dr. Edmundo A. Gutiérrez D. por su guía y apoyo a través del programa doctoral. Esta gratitud la extiendo también al Dr. Francisco Gámiz y sus colaboradores, especialmente al Dr. Carlos Márquez, por haberme dado la oportunidad de trabajar bajo su supervisión en el Laboratorio de Nanoelectrónica en CITIC-UGR (Granada, España), muchos de los resultados reportados en este trabajo vienen del tiempo que trabaje ahí.

Me gustaría además agradecer a GlobalFoundries por los fondos que financiaron este y otros proyectos.

Este trabajo refleja también muchas discusiones con gente del área y mis ami-gos, expreso mi gratitud al Dr. Joel Molina, Dr. Reydezel Torres, Dr. Adrián Tec, Dr. Héctor Uribe, Jairo Méndez y René Valderrama, y al resto de amigos de INAOE.

A Lizbeth Robles por su apoyo y paciencia.

A mis padres y hermanos por creer en mi.

(7)

(8)

4 Charge-pumping measurements under magnetic fields 35 4.1 Experimental setup and methodology . . . 35 4.2 Results and discussion . . . 36 4.2.1 Analysis for B ₆= 0 . . . 37 5 RTN and noise measurements under magnetic fields 43 5.1 Experimental setup and methodology . . . 44 5.2 Results and discussion . . . 44 5.2.1 Analysis for B 6= 0T . . . 50

6 Conclusions 57

(10)

List of Figures

1.1 General structure of the bulk MOS transistor. . . 2 1.2 TEM of a high- dielectric plus a metal gate. The complex

dielectric stack includes a SiO2 transition layer. Reproduced

from [1]. . . 3 1.3 Semiconductor band diagram illustrating the location and

en-ergy position of interface traps. . . 4

2.1 The degradation and recovery phases in time. . . 10 2.2 The Reaction-Diﬀusion model. Si-H bonds are broken at theSi

-SiO2 followed by a Hydrogen diﬀusion into the oxide, leaving

electrically active interface traps. . . 11 2.3 a) The missing atoms generate unpaired valence electrons in

the surface and generate interface traps. b) After oxidation, the majority of states are filled with oxygen atoms. c) After annealing, interface defects is reduced by the Hydrogen bonding with the remaining states. . . 13 2.4 Energy band diagram of a pMOS transistor in weak inversion.

The Fermi energy level defines the filling and the net charge. . 15

3.1 The experimental setup performs the measurement via Semi-conductor Device Analyzer connected to either a test fixture to characterize the INAOE transistors, or to a probe station to characterize the 250nm transistors. . . 18 3.2 Examples of the I-V traces for two separate devices: INAOE

and 250nm transistors. . . 19 3.3 Threshold voltage definition via the second derivative method.

Extracted from [2]. . . 20 3.4 The charge pumping technique is performed through the above

experimental setup. Usually, drain and source are tied together when reverse biased. . . 22 3.5 The charge pumping technique yields the five-region curve. a)

The biasing conditions that lead to the characteristicIcpcurrent

in b). . . 23 xi

(11)

List of Figures xii

3.6 An example of a signal aﬀected by the stochastic trapping/de-trapping into oxide traps. The ID current fluctuates between

two levels when a single oxide trap is activated. . . 25 3.7 Simplified energy band diagram for a transistor having a single

trap in the gate oxide. . . 27 3.8 Schematics of the noise measurement. A single specialized

in-strument performs the tasks. . . 30 3.9 Noise spectrum density vs frequency for a transistor biased at

VG = 500mV. Inset shows diﬀerent noise sources encountered

in MOS transistors. . . 30 3.10 Summarized experimental protocol to characterize interface an

oxide traps under the influence of magnetic fields. . . 31 3.11 The magneto-modulated performance parameters: a) ID, b)

VT HandST H, c)gm, and d) mobility for a20µm/20µmINAOE

transistor. . . 33 3.12 The proportional diﬀerence between the measurements at B =

0T and B 6= 0T. For three separate devices, the magnetic field

exerts a stronger eﬀect when driven in the subthreshold regime. 34

4.1 The concentration of traps over the whole range of Vbase. The

maximum current can be seen as two overlapping concentration of traps, each located in energy at diﬀerent positions. . . 37 4.2 When the rise/fall times of the gate pulse is higher,

recombi-nation current reduces due to carriers needing more time to be energized into the trap states. . . 38 4.3 a) The magneto-modulated trap concentration reveals that the

maximum concentration of traps in the plateau is increased by the B field. b) Region marked as "2" is aﬀected more than

region marked as "1" by the magnetic field. . . 39 4.4 In INAOE transistors, the trap concentration responds diﬀ

er-ently to the application of the magnetic field. The "N" shaped characteristic is consistent with the extracted parameters in sec-tion 3.4. . . 40

5.1 a) Representative noise characteristic of a transistor, following a 1/f trend. b) the experimental and model normalized drain

current power spectral density at f = 10Hz . . . 45

5.2 The SID/ID2 VG plot extracts the bias range where the

de-vice is aﬀected by trapping phenomena from the bell shaped characteristic . . . 47 5.3 RTN Time traces for distinct gate voltages. The times spent in

(12)

List of Figures xiii

5.4 Time domain data represented in the TLP space at diﬀerentVG.

Two well-defined states appear in the diagonal in each graph, suggesting trapping occurs into a single oxide trap. The color scale indicates the weighted number of events. Results for a transistor with tox = 14nm. . . 49

5.5 a) ⌧c and ⌧e with the gate voltage in transistors with tox =

14nm. (b) the logarithm of the ratio defines the location and

energy position of the trap. . . 50 5.6 TheSID/ID2 VG plot under diﬀerent magnitudes the magnetic

field. The noise power increment at B = 200mT occurs with VG ⇡700mV. . . 51

5.7 a) A 1/f2 _{behavior is observed instead of the} ₁_/f _{depicted at}

B = 0T. b) The CNF and Hooge mobility models agree,

al-though a slightly diﬀerent than the case when B = 0T.

No-tice the pronounced increment and subsequent reduction of the spectral density at around ID ⇡ 10 6A, which corresponds to

VG ⇡0.7V.. . . 52

5.8 The RTSs in the TLP space for a)B = +200mT, b) B = 200mT, c) B = 110mT and d) B = 110mT, showing a

weak eﬀect of the B field. In the four cases, two states are

well-defined. The color scale indicates the weighted number of events. . . 53 5.9 Normalized spectral density of the noise with the gate voltage in

the absence of the magnetic field (black) and under the influence of four perpendicular to channel magnetic fields. Frequency = 20Hz. Measurements for the transistor withtox = 7nm. . . 54

5.10 The TLP representation of a RTN signal at a)B = 200mT ,

b)B = 200mT, c)B = 110mT and d)B = 110mT. One

transition between two states is evident in b) and c). In a) and d), a second transition is induced, indicating a second trap joins in the trapping phenomena. The color scale indicates the weighted number of events. Inset of plots a) and c) shows the two-level drain current in time domain when a single trap is present, and the inset of plots b) and d) indicate the new trap emergence as a three-level drain current. . . 56

6.1 a) The energy levels in a quantum well at B=0T. b) The energy levels are shifted at B=200 mT. . . 58

(13)

(14)

Chapter 1 Introduction

1.1 Background

Figure 1.1 illustrates the general structure of the MOS transistor. Typically, the four contacts (gate, drain, source and bulk) are electrically stimulated in order to control the charge concentration in the channel through the MOS capacitance, blocking or conceding the charge carriers to flow typically from source to drain. This is the fundamental phenomenon behind the operation of the transistor as a switch in digital applications. To maximize performance, that is, to increase the switching speed and reduce the consumed energy dur-ing operation, studies have focused on improvdur-ing the control over the carrier transport in the channel region. The eﬀorts aimed at shrinking the MOS tran-sistor dimensions to the nanometer range, primarily the gate oxide thickness in conjunction with the channel length. The development of technological tech-niques reached an impressive level at manufacturing a few SiO2 atomic layers

as gate dielectric material [3, 4]. However, tunneling eﬀects leading to gate leakage current impede further reducing beyond ⇠1 nm thick SiO2 as, below

this range, electric degradation could potentially make the device useless as a logic element [5, 6]. Second-order eﬀects associated to tunneling phenomena degrade the device overall performance over time and, for this reason, the rate

(15)

Chapter 1 Introduction 2

Bulk

S

Drain

Gate

Oxide

Source

Figure 1.1: General structure of the bulk MOS transistor.

of escalation was attenuated. Conversely, these issues increased the motivation for studying alternative materials or novel device structures. The introduction of high  materials, as well as using metal gates as opposed to poly-silicon gates (used in SiO2 technology), solved some of the problems by making

pos-sible to keep the same gate capacitance with lower leakage currents [7, 8]. On the other hand, high  materials in direct bonding with silicon yields a high density of interface traps, and they were integrated in the fabrication process of the MOS transistor using a diﬀerent approach. The need of an underlying

SiO2 layer to keep stability over the carrier transport in the channel [8]

re-sulted in a complex dielectric stack (Figure 1.2), revealing previous and novel reliability phenomena, the most important being defect generation in the ox-ide, which can lead to undesired gate leakage current and trapping-induced instabilities. In this context, potential dielectric breakdown was one particular concern [5, 8]. In addition, transistors could also experience progressive para-metric degradation, led by the gradual trapping of charge in the oxide [3, 9]. Threshold voltage (VT H) shift is usually the onset of this parametric

degrada-tion of the MOS transistor triggering instabilities in the transconductance, the maximum cut-off frequency, the subthreshold swing, and consequently aff ect-ing the maximum drivect-ing capability of the channel current. Furthermore, some of the trapping phenomena exhibit recovery effects, in which the generated ox-ide traps during operation get partially passivated -or electrically deactivated-when electrical stress is reduced, a phenomena termed Bias Temperature Insta-bility (BTI), a voltage and temperature dependent effect that hitherto remains

(16)

Figure 1.2: TEM of a high- dielectric plus a metal gate. The complex

dielectric stack includes aSiO2 transition layer. Reproduced from [1].

under debate. Hot carrier injection (HCI) is another major reliability concern in which highly energetic carriers in the channel generate defects in the oxide that could potentially lead to dielectric breakdown [10]. The highly energetic carriers are originated by impact ionization from the elevated electric fields as consequence of device dimensions reduction and implementation of high- materials.

The common factor in these degradation mechanisms are defects in the structure of the dielectric and the interface with the silicon substrate. Con-sequently, defect control and further characterization became relevant topics of research. When studied at atomic level, such defects refer to a vacancy, a self-interstitial, an antisite, an impurity, or any combination of those sin-gular defects (clusters, interfaces, grain boundaries, surfaces, etc.), generated in the fabrication process, both intentionally and unintentionally, as well as during device regular operation. The latter arises from the bond breaking in the semiconductor-oxide interface by a combination of electric field and tem-perature variation (temtem-perature fluctuates during high-performance IC opera-tion), resulting in oxide or interface traps. In terms of energy, they are located throughout the Si bandgap, as in Figure 1.3. That physical location and energy position very close to the inverted channel leads to continuous trapping/de-trapping of carriers, especially into those located in the semiconductor-oxide interface (interface traps). The interaction with the surface channel triggers

(17)

D

_it

E

_c

E

_v

E

_i

Occupied

Oxi

de

Semiconductor

Empty

E

_f

Figure 1.3: Semiconductor band diagram illustrating the location and

energy position of interface traps.

carrier injection into the oxide and contributes to gate leakage current, low fre-quency noise, reduced mobility and drain current driving capability, although the whole physical picture is not entirely understood [3, 11]. Despite the amount of data, there is still room for discussion. The critical energy that needs to be applied so that the traps can be activated, the origin of these traps (pre-existant before stress but not active or induced by electrical stress), how to determine whether trapping eﬀects will lead to recovery (BTI) or not (HCI), and if recovery exists, which fraction of recovery comes from interface or oxide traps, are some of the aspects that remain unknown.

Much of the information regarding traps come from common characteri-zation techniques determining the interface traps, such as the Direct-current current-voltage method (DCIV), charge pumping, and capacitance-voltage plots. For oxide traps, there are some other like Low-Frequency-Noise (LFN), Deep-Level Transient Spectroscopy (DLTS) and Random Telegraph Noise (RTN) associated phenomena. However, these purely electrical characterization tech-niques proved hard to provide elemental and structural information on the charge trapping phenomenology and, by themselves, were insuﬃcient to iden-tify the defects responsible for electrical activity. Therefore, much of the mi-croscopic information about these mechanisms now come from electrical tech-niques combining optical and/or thermal experimental approaches [12–14].

(18)

The use of magnetic fields is one particular tool that has gain visibility in recent years, used primarily in spintronics studies [15, 16]. The applica-tion of magnetic fields coupled with tradiapplica-tional electrical techniques can be used to investigate electronic properties of the trapping phenomenology. In-deed, there have been some studies that combine both the eﬀect of trapping phenomenology with magnetic fields with the purpose of spin control in elec-tronic devices [17, 18]. In them, the magnetic fields are extensively applied at high magnitudes (>1T) in a low temperature environment (_⇠4K and

be-low). Here, however, we took an unexplored path to investigate trapping phe-nomenology by typical characterization techniques in conjunction with "low" magnetic fields (< 1T), at room temperature. Some works [19, 20] have

ex-hibited uncomprehended responses of the MOS transistor under these unique measuring conditions, especially in the channel and gate oxide current. We have introduced the experimental findings on the eﬀect of the magnetic fields on the trapping phenomenology for several MOS technologies, under diﬀerent magnetic field magnitudes.

1.2 Outline

This thesis guides the reader through the elemental physics of trapping phe-nomenology leading to the most important degradation mechanisms and how to gain insight into the phenomenon by performing some characterization tech-niques under the influence of magnetic fields:

Chapter 2describes the most important degradation mechanisms found in literature, where the trapping phenomenology has proved to be a crucial eﬀect implicated in all reliability issues (Hot carrier injection, Bias Tempera-ture Instability and Oxide breakdown). Consequently, this chapter addresses a general overview on the charge trapping dynamics. Chapter 3 introduces the experimental approach that serves to characterize traps in MOS transistors. They are studied to evaluate the quality of the semiconductor-oxide interface by forcing trapping/de-trapping eﬀects using the charge-pumping technique

(19)

(to study fast or shallow traps) and the RTN approach (to study slow or deep traps). Additionally, the complementary information we can obtain from applying magnetic fields is introduced. Chapter 4focuses on the experimen-tal findings using the charge-pumping method under magnetic fields in MOS transistors fabricated in diﬀerent technology nodes. Chapter 5 describes the experimental results by triggering RTN eﬀects, under the influence of magnetic fields as well. The results are accompanied by noise measurements revealing information on oxide traps. The discussion revolves around the deviations found when contrasting the results in the absence and presence of magnetic fields. Finally, this thesis ends with Chapter 6 presenting the summarized ideas and challenges yet to overcome, as well as future directions.

(20)

Chapter 2 Theoretical framework

To understand the physical processes implicated in the reliability evaluation of MOS transistors, the three well-accepted degradation mechanisms will be briefly discussed in this chapter. Additionally, it contains a review on some of the topics that remain unanswered. All the mechanisms described below are found in transistors with SiO2 as dielectric material, but the description can

be extended to transistors with alternative materials, i. e. with high-. The most important characteristic considered as the cause for device degradation is the presence of traps inducing charge modulation in the channel that leads to carrier injection into the gate dielectric. For this reason, a general overview of the phenomenological description of the traps implicated in the trapping dynamics is presented as well.

2.1 Hot carrier degradation

Hot carriers are highly energetic charge particles flowing in the channel of a MOS transistor accelerated by high lateral electric fields, aﬀecting both n-type and p-type transistors. When the channel is inverted and a drain-source volt-age is applied (VD 6= 0), charge carriers travel from the source towards the

(21)

Chapter 2 Theoretical framework 8

drain, gaining energy from the applied electric field, primarily by those carri-ers in the region where the lateral electric field is the highest (this would be the drain end in case this electrode was biased). The distribution of the kinetic en-ergy of carriers in this area mimics a population at a temperature higher than the mean temperature of the silicon lattice, and those charge carriers are said to become "hot". Accelerated by the electric field, they can generate interface or oxide traps, followed by carrier injection into the gate dielectric that results in high gate leakage currents (in case a suﬃciently large population reaches the gate), as well as high substrate currents (acting as an additional driving force for carriers in the surface). Both undesired currents are typically measured to evaluate the consequences of hot carriers. The presence of traps in the gate oxide and at the Si SiO2 interface yields local surface potential variations

leading to parametric degradation of the MOS transistor, the most important being threshold voltage shifts. These phenomena significantly reduce the op-erating lifetime of the transistors, especially in modern devices with deeply scaled dimensions [6, 21]. There are four markedly injection mechanisms re-lated to hot carriers: channel hot electron (CHE), drain avalanche hot carrier (DAHC), secondary generated hot electron (SGHE) and substrate hot electron (SHE).

Channel hot electron injection: In here, electrons gain suﬃcient energy to surmount theSi SiO2 barrier at the drain end in the channel, when the gate

voltage is approximately equal to the drain voltage (VG = VD). Under this

condition, the gate current IG can be measured to calculate the CHE eﬀect.

At VG < VD, the electric field is not capable of attracting carriers to the

gate electrode, but with higher VD the lateral electric field leads to avalanche

multiplication by impact ionization.

Drain avalanche hot carrier injection: The DAHC injection is notable with high VD and mid VG. Avalanche multiplication by impact ionization is the

cause of this injection mechanism where carriers gain energy from the lateral electric field. The avalanche multiplication phenomena leading to electron-hole

(22)

pairs generation consequently contributes to the substrate current IB as well,

complicating the measurement of DAHC injection.

Secondary generated hot electron: Aside from the electron-hole pairs gen-erated by the high electric field in the drain region, photons are additionally generated, inducing a secondary generation process for electron-hole pairs, leading again to avalanche multiplication phenomena. Photo-induced gener-ated carriers contribute to SGHE injection.

Substrate hot electron: Substrate carrier injection comes from substrate bias VB. Carriers in the bulk driven to the Si SiO2 interface gain kinetic

energy in the surface, contributing to the generation-injection cycle described in the above mechanisms. In SHE, as the stress conditions are well-defined in the interface due to the energetic carriers being uniformly distributed along the channel (in contrast, the maximum of the injection occurs at the drain end in the above mechanisms), it is majorly forced to occur for reliability tests [21]. The oxide field, the carrier energy, and the current intensity can be adjusted independently to investigate the trapping dynamics in MOS transistors.

In spite of the well-known qualitative description of hot carrier injection, some aspects remain unknown. Literature proves hard to describe the exact contribution from each injection mechanism to the totalIG and IB.

Addition-ally, the internal temperature variation as a result of the impact ionization, a variable often assumed to be constant, may lead to self-heating and phonon-assisted trapping eﬀects [21]. This is particularly important as in real circuits transistors are subjected to gate and drain bias variating in time, whereIGand

IB will be the result of the combined eﬀect of all the above injection

mecha-nisms. If found, both currents could be treated as indicators for the energy and thermal distribution of carriers in the channel due to hot carrier stress. To complicate things even more, it is not clear how the gate oxide trapping eﬀects are most aﬀected by each type of carrier, as both electrons and holes are present in hot carrier degradation as minority and majority carriers.

(23)

Vt (t=0)

Vt

(V

)

time

stress stress removed

most recovered

Figure 2.1: The degradation and recovery phases in time.

2.2 Bias temperature instability

Bias Temperature Instability (BTI) could reduce significantly the operating lifetime of the device, specially in deeply scaled down transistor dimensions with advanced materials, becoming a forefront reliability concern. By defini-tion, BTI is a reliability issue aﬀecting the electrical characteristics of the MOS transistor by high voltages at elevated temperatures (often encountered during high performance IC), as consequence of trap generation at theSi SiO2

in-terface and the dielectric. The accelerated bond-breaking at the inin-terface over time induces charge trapping eﬀects that shift the threshold voltage, reduce the channel mobility due to scattering, and induce drain current degradation over time. The characteristics under study include recovery eﬀects upon removal of stress (Figure 2.1), microscopics of degradation over time, the activation energies of trapping dynamics, frequency and material dependence.

The recovery eﬀects are the most important topic, still under debate, lead-ing to higher operatlead-ing lifetimes for transistors at AC stress, but complicatlead-ing the characterization techniques to investigate it [11, 22]. For the latter, ac-celerated characterization tests using higher bias and temperatures than the usual operating conditions are performed, where the characteristic BTI time-dependence is extracted, and the results are projected for estimating device lifetimes. Although some questions underlying this eﬀect have since then be

(24)

Gate Dielectric Silicon

Figure 2.2: The Reaction-Diﬀusion model. Si-H bonds are broken at the

Si-SiO2 followed by a Hydrogen diﬀusion into the oxide, leaving electrically

active interface traps.

answered, others still remain open. Despite being around for decades [23], there is no consensus on the exact physical mechanism behind the performance insta-bilities (several models have been proposed), but there is general agreement on charge building up in the interface or in the oxide layer as the cause of the para-metric degradation of the MOS transistor, and the Reaction-Diffusion (R-D) model has been well-accepted to explain this trap generation under BTI stress [11, 22]. The model illustrated in Figure 2.2 is a two-step process: at first, a field-dependent electrochemical Si-H bond breaking takes place, followed by interface trap generation as consequence of releasing hydrogen during this re-action phase. Subsequently, in the diffusion phase, such hydrogen is drawn away from the interface into the gate oxide at a certain rate. Similarly, the inverse process is possible, where diffusion of hydrogen from the oxide back to the interface yields passivation of Si- dangling bonds.

While there is little controversy on the acceptance of the R-D describing the BTI phenomenon, both the trap generation phase and the recovery mech-anism are not entirely clear yet. The discussion is centered around the experi-mental results strongly depending on the characterization methods, measuring conditions and the MOS transistor features such as geometry, size and materi-als. Moreover, the degradation effect has shown different behavior for different processing modifications such as dopants, thermal annealing treatments or nitridation techniques. At microscopic level, the gaps in our understanding

(25)

address the exact role of oxide charges in the dielectric, the contribution of each type of traps (electron and hole traps) and their origin (induced by stress or pre-existant).

2.3 Gate-Oxide breakdown

The optimum operation of the MOS transistor relies on the excellent insula-tor properties of the gate oxide (poor electrical conductivity and large energy bandgap). There is a maximum electric field that the gate dielectric sustains before the insulator properties are irreversibly lost, allowing electrical current to flow through the oxide. This occurs by the formation of a conductive path in the dielectric material(s) and the phenomenon is known as the dielectric break-down, the ultimate outcome of degradation. Generally, the insulator wears out after some time under electrical stress until it finally breakdowns entirely. The mechanism is ascribed as a two-step process: at first, a progressive damage builds up in the oxide and finally, an abrupt generation of a breakdown path takes place. A wide variety of models have been proposed describing the degra-dation process, such as the anode-hole injection, the electron trap generation, or the percolation theory, to name a few.

Anode-hole injection: This model suggests electrons tunneling through the gate oxide can transfer the excess energy to an electron in the valence band of the gate electrode, leaving a hot hole when promoted to the conduction band. Hence, this hole can tunnel back to the oxide, generating oxide traps. When a critical quantity is reached, breakdown occurs.

Electron trap generation: In this model, breakdown occurs by the forma-tion of a conducting path of oxide traps. To trigger it, a critical electron trap density must be generated by electrical stress. This quantity is independent of the oxide thickness in this model.

Percolation model: During electrical stress, oxide traps are generated at a certain rate and distributed at random positions in the dielectric. When two

(26)

a) b) c)

Figure 2.3: a) The missing atoms generate unpaired valence electrons in

the surface and generate interface traps. b) After oxidation, the majority of states are filled with oxygen atoms. c) After annealing, interface defects is

reduced by the Hydrogen bonding with the remaining states.

or more traps are located closely together, a conducting path is formed in which charge can flow from one trap to the other. Just in the same way, when collections of conducting paths hit a critical defect density with cumulative stress, these "clusters" will be arranged in such a way that charge may flow through the oxide towards the gate electrode followed by an instantaneous large gate current increase (for hard breakdown), a small gate current increase with a sudden gate current noise (for soft breakdown) or a progressive gate current increase (for progressive breakdown).

From the microscopic point of view, it is well known that dielectric break-down is directly related to the formation of a chain of traps, interface states, defects, hole traps, and slow states linked to the origin of the mechanism. However, the random nature of the phenomena (varying from sample to sam-ple and dependent from the stressing conditions) has brought some topics that remain under investigation, such as the link between the hole carriers, the oxide thickness, the critical electron trap concentration and the breakdown events, including reversible breakdowns in Metal-Insulator-Metal structures (MIM) for memristive devices.

(27)

2.4 Charge trapping dynamics

The discrepancy found in our understanding of the degradation mechanisms encourages researches to focus on the charge trapping/de-trapping eﬀects, a fundamental phenomenon in all reliability issues. To understand the trapping phenomenology, we need to investigate the nature ofSi SiO2interface. In the

crystalline structure, the silicon atom requires bonding with other neighboring silicon atoms to fully saturate the valance shell. However, at the surface (in theSi SiO2 interface), the silicon crystal does not perfectly bond with other

atoms, and traps are generated (Figure 2.3). For MOS transistors withSiO2

as dielectric material, the density of these interface traps is approximately 1010_cm 2_eV 1 _{after annealing techniques using hydrogen or nitrogen atoms}

[24, 25], giving first classSi SiO2 interfaces, albeit it is important to keep in

mind that the Si-H and Si-N2bonds generated after passivation are responsible

for some degradation mechanisms. The resulting dangling bonds are termed

Pb centers for Si3 ⌘Si•in (111) oriented substrates, while in (100) orientations

they are termed Pb0 for Si3 ⌘Si• and Pb1 for Si2O⌘Si•. All of these dangling

bonds reflect back in the forbidden silicon bandgap as trap levels, or shallow levels, being capable of both donating and accepting electrons from the sil-icon band edges [26], meaning they are of amphoteric nature. Their energy distribution is illustrated in figure (Figure 2.4). The charge state of the traps depend on whether they are occupied or empty and the type of the trap:

Donor-like energy level: Located above the valence band edge in the lower half bandgap, the trap levels are neutrally charged when occupied by electrons and positively charged when emptied.

Acceptor-like energy level: Located below the conduction band edge in the upper half bandgap, the trap levels are negatively charged when occupied by electrons and electrically neutral when emptied.

Another important defect is the E’ center. Although the exact nature and physical location is still under debate [26, 27], they are known to be oxide

(28)

SiO2 Silicon

Figure 2.4: Energy band diagram of a pMOS transistor in weak inversion.

The Fermi energy level defines the filling and the net charge.

traps in the SiO2, but electrically interacting with theSi SiO2 interface as

well. The E’ centers reflect as trap levels close to the middle of the silicon band gap, referred to as deep levels.

The charge state in all traps is given by the location of the Fermi level in the silicon. Correspondingly, the Fermi level moves with the application of voltages to the gate, source, drain and substrate electrodes as this process induces band bending in the surface in order to create the inversion channel and move carriers from point to point. This modulation eﬀect in conjunction with the electrically active energy levels present in the MOS transistor are the origin of trapping/de-trapping eﬀects that cause instabilities in the electrical characteristics of electronic devices. The reader must have in mind that the physical location as well the energy position of traps vary from transistor to transistor, and consequently each individual transistor exhibits a unique re-sponse to an specific trap. However, statistical values are reported throughout the literature.

The charge trapping dynamics are well-represented by phonon transitions following the Shockley-Read-Hall recombination model [28, 29]. The trap-assisted process requires energy from phonons (the silicon lattice vibrations)

(29)

and releases energy in the same form. The process can be summarized in four possible mechanisms:

Electron capture: From the conduction band, an electron is captured by an empty trap.

Hole capture: A trapped electron moves to the valance band neutralizing a hole (a hole from the valance band is captured by a trap).

Hole emission: From the valance band, an electron is trapped, leaving a hole behind (a hole is emitted from the trap to the valance band)

Electron emission: A trapped electron moves to the conduction band.

Several characteristics can be determined from the SRH theory taking into account the nature of the trap (acceptor or donor like traps) and the electron or hole concentrations, as well as the trap concentration, in the band edges, assuming stationary conditions. However, in transient conditions often encoun-tered in the regular operation of the MOS transistor, the rate of trapping and de-trapping eﬀects complicates the study by eliminating some simplifications in SRH theory, such as the capture and release rate being equal. The method-ology described in chapter 3 includes some of the characterization techniques performed to investigate trapping phenomenology, both for shallow and deep levels in MOS transistors.

(30)

Chapter 3 Methodology

This chapter introduces the experimental methodology used in order to inves-tigate the charge trapping dynamics implicated in reliability issues of MOS transistors. The characterization techniques address the two basic classes of defects that aﬀect the electrical activity in the channel, the interface and ox-ide traps. The charge-pumping technique selected for the study of interface traps has proven to be a versatile tool for extracting accurate characteristics of such traps, while the RTN approach accompanied by noise measurements has accounted for investigating the phenomenology of trapping due to oxide traps. In extensive studies, the user does not often need a deep understand-ing of the fundamental principles involved in the characterization techniques, the measurement equipment does all the job. Instead, the basic measurement principles need to be fully comprehended to analyze the experimental results in detail in this thesis. Such electrical characterization techniques were performed whilst applying external magnetic fields at diﬀerent magnitudes.

3.1 MOSFET devices and parameter extraction

The selected MOS transistors as test vehicles to investigate the trapping eﬀects under magnetic fields are:

(31)

Chapter 3 Methodology 18

DUT Semiconductor Device Analyzer DUT

Figure 3.1: The experimental setup performs the measurement via

Semi-conductor Device Analyzer connected to either a test fixture to characterize the INAOE transistors, or to a probe station to characterize the 250nm

transistors.

INAOE nMOSFET: The samples featuring poly-silicon as gate material have thermally grown SiO2 as dielectric material (tox = 60nm).

250nm nMOSFET: Samples fabricated at IBM facilities feature a tox =

14nm and below.

First, the electrical performance of the MOS transistor is conventionally evalu-ated from current vs voltage (I V) characteristics. From these measurements,

some of the electrical parameters of the device such as the threshold voltage (VT H), subthreshold swing (ST H), maximum transconductance (gmmax), or

mobility, can be extracted. Figure 3.1 illustrates the basic experimental set-up to carry out the electrical measurements. The INAOE transistors, encapsu-lated in package, were electrically characterized using an Agilent B1500a semi-conductor analyzer (SDA). The 250 nm MOS transistors, diced from the wafer, were characterized in a Janis probe station by the same SDA. The equipment biases the transistor electrodes and extracts the current or voltage charac-teristics through Source-Measurement-Units (SMU). Figure 3.2 illustrates the

I V characteristics of the above transistors fabricated in diﬀerent technology

(32)

0 1 2 3

0 10 20 30

Drain Voltage (V)

ID ( µA) Vg=1.4 V Vg=1.8 V Vg=2.2 V Vg=2.6 V

Vg=3 V Tox=60nm

W=L=20µm

0 2 4 6

0 100 200 300 400 Vg(V) ID ( µA)

Vd = 0.4 V Vd = 0.8 V Vd=1.2 V

Tox=14nm W=L=700nm

Figure 3.2: Examples of the I-V traces for two separate devices: INAOE

and 250nm transistors.

3.1.1 Threshold Voltage extraction

The threshold voltage is defined as the gate bias necessary to fulfill S = 2 B,

where S and B are the surface potential and the potential diﬀerence between

the bulk Fermi-level and the intrinsic Fermi-level, respectively. This definition comes from a one-dimensional analysis of the MOS capacitor [30]. From the phenomenological point of view, it is the gate bias condition where the minority carrier density is equated to the bulk majority carrier density, driving the transistor from depletion into inversion. There are a number of experimental techniques to extract V th[2], however only one method with proven accuracy

(33)

0v104 2×10−4 4×10−4 6×10−4 8×10−4 1×10−3

0 0.5 1 1.5 2

d gm /d VG S (S /V)

Gate Voltage (V) VT=0.98 V

Figure 3.3: Threshold voltage definition via the second derivative method.

Extracted from [2].

In the ideal case, whereVG < VT H yields ID = 0and VG > VT H givesId6= 0, a

step function comes fromdID/dVG in a ID VG plot, finding VT H as the onset

of the positive value. For the second derivative,d2_I

D/d2VGgrows to infinity at

VT H. The non-ideal case (Id 6= 0 for VG < VT H) shows the second derivative

having a limited maximum value at VT H instead of tending towards infinity,

depicted in Figure 3.3.

3.1.2 Maximum transconductance and subthreshold swing

The channel transconductance shows the rate of change of the drain current with the gate bias for a givenVD, directly calculated by the following equation

using the measured ID VG characteristics at low VD:

gm =

✓ @ID

@VG

◆

VD6=0

(3.1)

The subthreshold swingST H allows to estimate how "fast" the ION/IOF F

transition takes place by the gate voltage, represented as the shift inVGneeded

(34)

from:

ST H =ln10

✓

kT q

◆ ✓

Cox +CD

Cox

◆

(3.2)

whereT is the temperature,k the Boltzmann constant,qthe elemental charge, Cox the oxide capacitance, and CD the capacitance in depletion. In

experi-mental measurements, a logID linear dependence with VG is observed in the

subthreshold region for VD > kT /q, the calculus of the inverse of this slope

yields ST H.

3.1.3 Mobility extraction

A universal behavior of mobility of carriers in the channel is observed when uniquely analyzing the impact of the transverse electric field, applied to the gate electrode, on the carrier velocity [31]. This eﬀective mobilityµef f can be

calculated as:

µef f =

gdL

W Qn (3.3)

whereLis the gate length, W the width,Qnthe mobile channel charge density

(C/cm2_{), and} _g

d the drain conductance, defined as:

gd=

✓ @ID

@VD

◆

VG6=0

(3.4)

The Qn extraction is carried out by the following expression:

Qn=Cox(VG VT H) (3.5)

Albeit having some deficiencies, experimental results have shown good agree-ments with this approach [2, 31–33]. From ID VG measurements, µef f is

calculated with VD typically in the range of50-100mV, or below, to ensure a

channel charge uniformity from source to drain [2, 33]. Physically, µef f means

the proportional constant between the carrier velocity and the total effective electric field affecting an average carrier, this effective field takes into account

(35)

B

S D

G

S Oxide

A

Figure 3.4: The charge pumping technique is performed through the above

experimental setup. Usually, drain and source are tied together when reverse biased.

the full eﬀect of the depletion layer, but only a portion of the inversion layer [33].

3.2 The charge pumping technique

The technique introduced in [34], widely used for precise estimations of the in-terface trap concentration (Nit), allows in-depth analysis of the

semiconductor-oxide interface of the MOS transistor, often used for reliability evaluations of such devices. The charge-pumping method is considered a versatile tool to in-vestigate trapping phenomenology given the development of several variations of the basic technique in order to extract detailed information on the energy and physical distribution of interface traps [2, 35]. This experimental tool was selected to study fast traps due to the well-accepted phenomenological expla-nation of the method, the high sensitivity to the trap density, and the basic equipment required for the measurements. Figure 3.4 illustrates the basic

(36)

ex-Chapter 3 Methodology 23

4

5

1

2

3

4

5

1

2

3

Vg VTH

V_fb Vbase ∆V Vbase

a)

b)

Icp

Figure 3.5: The charge pumping technique yields the five-region curve. a)

The biasing conditions that lead to the characteristicIcp current in b).

perimental set up for a nMOS transistor. Source and drain to substrate diodes are slightly reverse bias. The gate is then pulsed-bias, driving the surface from accumulation into inversion, while monitoring the substrate current. During the inversion phase, minority carriers (electrons in a nMOS transistor) injected from the source and drain regions occupy the channel area and some of them become trapped in interface states. When the surface is driven towards accu-mulation, the minority carriers leave the channel, flowing back to source and drain, except for those trapped carriers if the gate is rapidly pulsed, and the majority carriers from the substrate driven to the surface recombine with the trapped minority carriers. The identical process takes place in the accumu-lation back to the inversion phase, with opposite type of carriers, leading to a net charge pumped at each cycle. If the cycle is repeated at a certain fre-quency, this charge leads to a constant measurable current proportional to the concentration of interface traps Nit.

The approach introduced by Elliot in [36] was selected among the diﬀerent methods performed for charge-pumping measurements [35], given its capability to determine the energy distribution of interface states. This method sweeps the base level of the gate voltage pulse Vbase to drive the MOS transistor from

accumulation into inversion, assuming an amplitude of the pulse VA larger

than VT H Vf b, whereVf b is the flatband voltage. The resulting measurement

(37)

Region 1: When Vbase&Vtop < Vf b, the surface is in accumulation. No

recom-bination current is measured with interface traps filled with majority carriers.

Region 2: With Vbase < Vf b and Vf b < Vtop < VT H, the surface enters into

depletion from inversion. Some minority carriers gain suﬃcient energy to flow into the surface, recombining with the trapped majority carriers, measuring anIcp increment. The origin of this current still raises controversy [37].

Region 3: AtVbase < Vf b and Vtop> VT H, the surface is continuously

switch-ing between accumulation and strong inversion. The majority of trapped car-riers recombine with surface carcar-riers, leading to the highest magnitude of Icp.

The largest amount of interface traps is calculated in this region.

Region 4: WhenVf b < Vbase< VT H, the channel is driven from inversion only

into weak accumulation. Icp is reduced by the decreasing amount of majority carriers flowing into the surface in order to recombine with trapped minority carriers.

Region 5: DuringVbase > VT H, the surface is permanently inverted with traps

filled with minority carriers. Zero Icp is measured again, unless other leakage

currents contribute as well [35, 38].

3.3 Random Telegraph Signals and noise

mea-surements

3.3.1 Random Telegraph Signals

Random Telegraph Signal (RTS) consists of the drain current ID randomly

switching between discrete levels by the stochastic trapping/de-trapping of carriers from the channel into traps located at a close tunneling distance from the inversion layer, a phenomenon first reported in [39]. The phenomena gained a great deal of interest due to modern devices reducing the operational cur-rent to levels comparable to the fluctuations induced by RTS, which resulted

(38)

Time (s/div) ID

(0.1nA/div)

Vg = 400 mV Vd = 50 mV

Figure 3.6: An example of a signal aﬀected by the stochastic trapping/de-trapping into oxide traps. TheIDcurrent fluctuates between two levels when

a single oxide trap is activated.

in reliability issues that limit the performance of such devices, especially in submicron memories, CMOS image processors, and deeply scaled technologies (nanowires, carbon Nanotubes, etc.[40, 41]). However, when studied in detail, RTS provides valuable information regarding the transport properties of the MOS transistor, particularly on the semiconductor-oxide interface. The exper-imental characterization is carried out by monitoring the drain current ID in

a long enough time window to observe as many trapping/de-trapping events as possible, since the analysis of RTS is often carried out through statistical approaches given the random nature of the phenomena [29, 42]. The equip-ment scans for capture/release events linked to a particular trap energy range by the proper selection of the sampling rate, i. e., slow states (oxide traps) reflect back to the drain current as fluctuations in the millisecond range, but fast states (interface traps) require sampling rates below this range. In the simple case often encountered in modern devices, the drain current fluctuates between two possible values by the presence of a single oxide trap [39]. Multi-level transitions reported as well, appear as consequence of fast traps aﬀecting

ID, due to a higher density of interface traps (Dit) close to the band edges,

but proven diﬃcult to measure. The current signal is characterized by esti-mating the diﬀerence between the high and low current levels ID, the times

spent between capture events, as well as the time between de-trapping events. With the appropriate characterization tools, important parameters, such as the nature of the trap (donor or acceptor like state), the energy level of the trap ET, the barrier for carrier capture, or the depth and the lateral position

(39)

approaches describe the carrier capture and emission by standard Shockley-Read-Hall (SRH) theory in many cases to extract such parameters [43, 44]. In this scenario, assuming a n-channel transistor, the average capture time for a carrier in the inversion layer is given by:

⌧c =

1

nvth (3.6)

where n is the electron volume concentration (proportional with ID), vth the

thermal velocity for electrons, and the capture cross-section; while the emis-sion time is described as:

⌧e =

1

gnvth ⇤

exp

✓

EF ET

kBT

◆

(3.7)

whereEF is the surface Fermi level, kB the Boltzmann’s constant,T the

tem-perature, g the trap degeneracy factor. The latter is usually unknown and

assumed equal to 1 [29, 45]. The energy level of the trap can be determined by the ratio:

⌧c

⌧e

=g⇤exp

✓

ET EF

kBT

◆

(3.8)

The unknown parameter ET can be extracted from the analysis of the

simplified band diagram illustrated in Figure 3.7. From this schematic:

ET EF =



(Ecox ET) (q s ox q s) +

xT

tox

(_|Vf b|+VG q s)

(3.9) where Ecox is the minimum of the dielectric conduction band, s the

semi-conductor work function, ox the electronic aﬃnity of the oxide, tox the

ox-ide thickness, and xT the physical position of the trap calculated from the

semiconductor-oxide interface. The following expression is obtained from equa-tion 3.8 and 3.9:

ln⌧c

⌧e

= 1

kBT



(Ecox ET) (q s ox q s) +

xT

tox

(_|Vf b|+VG q s)

(40)

Figure 3.7: Simplified energy band diagram for a transistor having a single trap in the gate oxide.

The derivative of equation 3.10 with respect toVGyields the trap position:

xT =

tox d s

dVG 1 !

⇤

✓

kBT

q

dln(⌧c/⌧e)

dVG

+ d s

dVG

◆

(3.11)

With typical locations of oxide traps aﬀecting the drain current around 1-2nm away from the interface [45], ET can be determined from equation 3.9. It

be-comes evident from these equations that the process is thermally activated, and the room temperature condition is suﬃcient to energize the trapping/de-trapping process. From the foregoing, complementary measurements varying temperature while scanning RTSs provide additional information on the trap-ping phenomenology, but the temperature eﬀect is out of the scope of this thesis.

(41)

3.3.2 Noise measurements

RTSs have an impact on the noise signature of MOS transistors, as such, it has been suggested that the typical Low-Frequency-Noise behavior found in MOS transistors is composed of multiple RTSs with diﬀerent time constants [42, 46]. Consequently, in addition to time domain analysis of trapping phe-nomenology linked to RTSs, measurements in the frequency domain, required to investigate the noise characteristics, complement this study. The measure-ments are accompanied by the extraction of the noise power in the frequency domain, an essential characteristic defined as the noise power spectral density (PSD). Aside from the RTSs, some other fundamental sources of noise con-tribute to the characteristic behavior: thermal noise, shot noise, flicker noise, and Generation-Recombination (G-R) noise [2]. In brief, thermal noise is at-tributed to the random motion of charge carriers leading to small fluctuations in the current. Shot noise relates to the discrete nature of charge transport, considering the current is not a continuum but rather a sequence of carrier "packets" traveling towards an electrode. Both sources of noise exist in practi-cally all electronic systems but they are negligible in magnitude when measured against the following.

Flicker noise, or Low Frequency Noise (LFN), arises from fluctuations in the charge transport caused by stochastic trapping/de-trapping of carriers in the channel into traps, which results in mobility and carrier density variations that lead to drain current fluctuations in a MOS transistor. There are es-sentially two competing models based on the individual contribution of each parameter (carrier or mobility fluctuations) on the noise signal. Those are the McWhorter number fluctuation theory and the Hooge mobility fluctuation approach [46]. Both are supported by experimental evidence despite the inter-twined eﬀect between one and the other on the drain current characteristics. Flicker noise, identified sometimes as1/f noise, prevails at low frequencies in

the noise spectrum with a characteristic1/f response.

G-R noise is caused by the generation and recombination of electron-hole pairs, which results in the random variation of carrier density in the inversion

(42)

layer. The noise spectrum proportional to the square of the current corresponds to a Lorentzian-like spectrum with the maximum at low frequencies, followed by a 1/f2 _roll-o_ﬀ_{. The noise signature of RTSs resembles that of the}

G-R noise, with a diﬀerent physical origin attributed to carrier trapping/de-trapping in a single oxide trap. When many trapping/de-trapping events occur having diﬀerent time characteristics, the summation of their individual RTSs yields a 1/f characteristic signature.

Noise measurements demand specialized equipment in a controlled en-vironment to extract accurate results, for this reason this characterization method is neither extensively examined nor applied as often as other tech-niques. In recent years, however, noise gained visibility as a tool to get insight into the degradation mechanisms by studying trapping phenomenology. As mentioned earlier, noise signals in MOS transistors are characterized by the extraction of the current PSD in the frequency domain, but in diﬀerent VG

steps, to scan for traps in diﬀerent energy ranges in the bandgap. First of all, an I-V amplifier magnifies the small magnitude current fluctuations. Then, the power of the augmented signal is calculated and most suitably expressed as the noise PSD using the Fast-Fourier-Transform algorithm. The tasks are performed through a low-noise programmable bias amplifier (BPA) controlled by a computer with a dedicated software. Figure 3.8 shows the experimental setup to perform the aforementioned tasks, whereas Figure 3.9 illustrates an example of the measurement.

(43)

Figure 3.8: Schematics of the noise measurement. A single specialized

instrument performs the tasks.

Figure 3.9: Noise spectrum density vs frequency for a transistor biased

at VG = 500mV. Inset shows diﬀerent noise sources encountered in MOS

(44)

I-V characteristics

Charge-pumping

Noise measurements: Spectral Scanning

Random Telegraph Noise

-300 mT < B < +300 mT

Figure 3.10: Summarized experimental protocol to characterize interface

an oxide traps under the influence of magnetic fields.

3.4 Experimental protocol

The systematic characterization protocol is summarized in Figure 3.10. At first, measurements are performed at room temperature in the absence of the magnetic fields. The same characterization method is then repeated but under the influence of external magnetic fields at diﬀerent magnitudes B, ranging

from -300 mT to +300mT. The electrical parameters are subsequently exam-ined for every magnitude of B. For in-package devices, the magnetic field

is externally applied using a GMW 5403AC electromagnet, where the Device-Under-Test (DUT) is placed between two poles in such a way that the magnetic field hits the sample perpendicularly. The magnitude and sign ofB is given by

the direction and the intensity of the current flowing in the poles. For devices diced from the wafer, the DUT is placed in the center of neodymium permanent magnetic rings. In this case, the dimensions of the ring defines the magnitude of B, while the orientation determines the sign of B. Prior to analyze the

charge trapping dynamics, the electrical characteristics and some performance parameters should be extracted in the selected devices using the conventional techniques described in section 3.1 to identify the classical Lorentz’ force, which deflects carriers in the channel by the application of magnetic fields.

(45)

The next step in the characterization protocol is to analyze the dynamic trapping eﬀects into interface states by performing the charge-pumping tech-nique described in section 3.2. By the variation of the frequency, the ampli-tude, and the rise/fall times of the gate pulse, additional information can be extracted from the Icp.

Slow traps are then examined through the characterization protocol devel-oped by Marquez et al. [47], via noise measurements and RTSs. As described in section 3.3, noise measurements use an experimental setup which biases the DUT, and measures the current and the fluctuations by a low noise current/-voltage amplifier connected to a high-resolution Analog-Digital converter, then performs the Fourier analysis with a spectrum analyzer and, after all, records and displays the data. RTSs are then measured: following the description in section 2.4 and 3.3, only specific devices are suitable to be affected by RTSs, considering that the time constants and the current amplitude dependent on the trap energy level and the Fermi energy in the surface, which are properties that vary between samples and depend on the bias conditions. The use of the Spectral Scanning by Gate Bias( SSGB) approach [47], which analyzes the noise characteristic response of the drain current (detailed in chapter 5), pre-vents elongated and repetitive measurements in the selection of devices affected by RTSs. The method additionally determines the bias conditions where the device is most likely affected by individual traps. Upon selection of the device and determination of the optimum bias range, sampling measurements of the drain current are recorded at a 2mssampling rate for 200s.

As an example to demonstrate the magneto-modulation eﬀect, the I-V characteristics and some of the performance parameters are contrasted in the absence and presence ofB, depicted in Figure 3.11. Recent works [19, 20] have

examined this magneto-modulation eﬀect, in which carrier re-allocation in the inversion channel due to carrier deflection results in localized modulations of threshold voltage, transconductance, and some other electrical parameters. Furthermore, carriers are forced to flow in a non-homogeneous channel with anisotropic conductance, due to variability in the fabrication process, which contribute to this localized parametric variations. These conclusions are the

(46)

-300 -200 -100 0 100 200 300

2.06×10-6 2.08×10-6 2.10×10-6 2.12×10-6 2.14×10-6 B (mT) Gmax (s)

Gmax vs B

5.50×105 _5.74_×₁₀5 _5.98_×₁₀5 _6.22_×₁₀5

-5 0 5 10

E_eff (V/cm)

Δ

Mobility (cm

2/Vs)

∆ Mobility at different B

300 mT 100mT

-100mT -300mT

-300 -200 -100 0 100 200 300 1.52 1.53 1.54 1.55 1.56 130.00 131.00 132.00 133.00 134.00 B (mT) Vth (V) S (mV/Dec) Sub. Slope Vth

Vth & S

0 1 2 3 4 5

-8.0×10-8 3.0×10-8 1.4×10-7 2.5×10-7 3.6×10-7 4.7×10-7 5.8×10-7

Vg (V) ∆ Id (A) 300mT 50mT -50mT -300mT

∆Id vs Vg

∆Id = (Id_B_≠₀ - Id_B=0)

Vd = 2.4 V

a) b)

c) d)

Figure 3.11: The magneto-modulated performance parameters: a) ID,

b) VT H andST H, c)gm, and d) mobility for a20µm/20µmINAOE

tran-sistor.

basis of this work, as the parametric variation is closely related to trapping phenomenology. An example of this correlated effect is demonstrated in Figure 3.12. I-V measurements in various transistors fabricated under different tech-nology generations have confirmed that a transistor experiences the strongest magneto-modulation effect when driven in the subthreshold-weak inversion regime, which has proven conveniently to be the region with the most evident impact of trapping effects in the electrical characteristics.

(47)

0 1 2 3 4 5

0.0 10.0 20.0 30.0

Vg (V)

∆

ID

(%)

Octagonal nFET

∆Id/Id(%) vs Vg

B = -300 mT 250 nm nFET INAOE nFET

Vth

Figure 3.12: The proportional diﬀerence between the measurements at

B = 0T and B ₆= 0T. For three separate devices, the magnetic field exerts

(48)

Chapter 4 Charge-pumping measurements

under magnetic fields

An investigation into the dynamic trapping of interface states was conducted in nMOS transistors with the charge-pumping technique performed at room tem-perature under the influence of perpendicular-to-the-surface magnetic fields. Devices fabricated under two diﬀerent technologies were characterized using the experimental method described in section 3.2. The concentration of in-terface traps was calculated from the charge-pumping current measured at diﬀerent magnitudes of the B field. The analysis presented in this chapter

re-vealed the pumped current was magneto-modulated as a result of the magnetic field probably altering the trapping dynamics. Furthermore, the experimental findings suggests that both electrons and holes are aﬀected diﬀerently by the magnetic field.

4.1 Experimental setup and methodology

The INAOE and the 250 nm transistors were selected as test vehicles. The former features a gate oxide thickness of 60nm, with a (W/L) aspect ratio of (20µm/20µm). The 250nm transistors, diced from the wafer and fabricated

(49)

Chapter 4 Charge-pumping measurements under magnetic fields 36

at IBM facilities, feature an oxide thickness of 14nm, with gate length and width of 700nm. All devices featureSiO2 as dielectric material. Following the

methodology described in section 3.2, prior to characterize the interface states, the pulse-base-level method requires the extraction of theVT H,Vf band VA>

VT H Vf b. The reverse voltage is applied by a B1500A SDA through

Source-Measurement-Units. The pulse signal is then applied to INAOE transistors via the HP33120A waveform generator, and to the 250 nm transistors through a Semiconductor Pulse Generator Unit (SPGU). TheNit is calculated from the

maximum charge pumped currentIcp in theIcp Vbase plot as:

Icp =qAGf Nit (4.1)

The Icp was measured at two frequencies (100KHz and 1MHz), and the

rise/fall times of the gate pulse was varied to extract further information. The experimental characterization protocol was repeated at room temperature but with static perpendicular-to-the-surface magnetic fields B ranging from -300

mT to +300 mT.

4.2 Results and discussion

The results of the experimental measurements at B = 0 are depicted in fig-ures 4.1 and 4.2. The maximumNit agrees with transistors having thermally

oxidized silicon as gate dielectric material (⇠ 1010_{, [24, 25]). The reduced}

Nit for f = 1M Hz in all devices has indeed been widely reported [35, 48–50]

and attributed to the time spent in inversion/accumulation being suﬃciently short that only interface traps can contribute to the CP current, as opposed to shorter frequencies (f = 100KHz), where traps located at a certain distance

away from the interface may contribute to the measured data.

Figure 4.1 additionally shows two possible maximum values of Nit, over

a specific Vbase range. The explanation to this phenomenon is understood