Electrical modeling and optimization of multilayer via transitions for fully-integrated systems

1

Electrical Modeling and Optimization

of Multilayer Via Transitions for

Fully-Integrated Systems

by

Gaudencio Hernández Sosa, MSc

A thesis submitted in partial fulfillment of the

requirements for the degree of

DOCTOR OF PHILOSOPHY

Department of Electronics

National Institute for Astrophysics,

Optics and Electronics (INAOE)

November 2011

Tonantzintla, Puebla

Supervised by:

Prof. Reydezel Torres Torres, PhD

INAOE

©INAOE 2011

All rights reserved

The author hereby grants to INAOE permission to

reproduce and to distribute paper or electronic copies

ii

Abstract

Due to the advances in electronics technology, today’s modern life is inevitably

dependent on the complex convergence of diverse technologies into products designed

to provide solutions in many applications (e.g., computing, communication, biomedical, etc.). In this way, the concept of fully-integrated “convergent electronic systems” has

emerged. As promissory approach for implementing reliable fully-integrated systems,

System-On-Package (SOP) technology proposes the integration of active and passive

components into a single package. Nonetheless, SOP presents important challenges

over traditional packaging due to the presence of multiple ICs, embedded passives and

other components connected within the package. On the other hand, high-density

substrates with narrow traces widths and thousands of vias in order to achieve vertical

integration of different ICs working at higher speed is a key enabler technology for SOP.

Unfortunately, electrical discontinuities introduced by via transitions are the main limiting

factors for the ultimate performance of SOP interconnects. As a result, the development

of interconnects capable of guiding broadband digital signals without degrading the

signal integrity plays a key role in the SOP implementation.

Thus, due to the importance of vias for fully-integrated systems based on SOP, fast

and accurate techniques to model vias in multilayered high-density packages are

developed in this thesis. Furthermore, techniques to mitigate the signal integrity

problems related to vias are proposed. Among the contributions that the reader will find

in this document are novel full-wave/circuit modeling methodologies for vias in

high-density packages, return loss and crosstalk mitigation techniques which allow extending

the useful bandwidth of chip-to-chip links. Rigorous theoretical analyses were carried

out accompanied by exhaustive simulations in the time and frequency domains to

develop and demonstrate the models and methodologies proposed in this thesis.

Moreover, several prototypes were designed and fabricated as part of this project to

serve as test vehicles that allow the verification of the mitigation techniques in an

iv

Dedicated to

My wife Bris and daughter Diana whose lives have

changed my entire world… my parents and brothers for

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Acknowledgments

First and foremost, I would like to express my sincerely gratitude to my advisor, Dr.

Reydezel Torres, for his guidance and patience during the course of this work. I thank

him for recognizing my potential to achieve research success in the exciting field of

electromagnetics, and especially in the signal integrity area which is a new emerging

field in Mexico. His kind guidance, patience and motivation have contributed to develop

my research skills.

I would like to thank and acknowledge my Intel mentors Dr. Gerardo Romo and Dr.

Adan Sánchez during my internships at Intel Guadalajara. Those internship positions

held over the course of my graduate studies provided me with the unique opportunity to

acquire hands-on experience and the industry point of view on signal integrity research

problems. In particular I am fortunate to have had the patience and understanding of my

manager at Intel Dr. Horacio Visairo for the valuable support to finish this doctoral

thesis.

Finally, I would like to thank INAOE and CONACyT for the human, technical and

financial support to develop and finish this thesis.

Gaudencio Hernández-Sosa

viii

Table of Contents

LIST OF TABLES x

LIST OF FIGURES xi

1.

Fully-Integrated

Electronic

Systems:

Requirements

and

Challenges

1.2 Approaches for Fully-Integrated Systems ……….. 3

1.2.1 System-On-Chip (SOC) ...……….………... 3

1.2.2 System-In-Package (SIP) ………..……….………. 4

1.2.3 System-On-Package (SOP) ……… 6

1.3 Why SOP instead of SOC? ...………. 7

1.3.1 SOP Technical Advantages ……...……….…… 8

1.4 Requirements for SOP ……….. 10

1.5 Electrical Challenges in SOP realization ……….. 12

1.6 Objective and Thesis Organization ………..……….. 14

2.

Full-Wave and Circuit Modeling of Multilayer Via Transitions in

High-Density Packages

2.2 Segmented Modeling of Multilayer Via Transitions ..……….. 19

2.3 The Interior Problem ……… 24

2.3.1 Full-Wave Approach ...………..……….. 26

2.3.1.1 Single Via with Arbitrary Power/Ground Via Distribution ………. 30

2.3.1.2 Multiple Vias with Arbitrary Power/Ground Via Distribution ……. 34

2.3.1.3 Effect of the Finite Thickness of the Metal Layer …………... 40

2.3.2 Circuit Modeling Approach ………. 45

2.3.2.1 Single Via with Arbitrary Power/Ground Via Distribution ………... 46

ix

2.4 The Exterior Problem for Single and Multiple Traces ………. 57

2.5 Segmented Full-Wave/Circuit Model for Multilayer Via Transitions ….………... 58

2.6 Comparison between Full-Wave, Segmented Full-Wave and Segmented Circuit Modeling Approaches for Multilayer Via Transitions ………..….. 59

2.7 Conclusions ……….……….……… 62

3.

Analysis of Return Loss and Crosstalk in Multilayer Package

Interconnects

3.2 Return Loss and Crosstalk Analysis for Multiple Vias with Arbitrary Power/Ground Via Distribution ……….….………….…… 65

3.2.1 Conditions for Mitigating Return Loss and Crosstalk Effects ………….... 66

3.2.2 Methodology for Mitigating the Return Loss and Crosstalk ………... 71

3.2.3 Example and Discussion ………..……… 77

3.3 Return Loss Mitigation for Single Multilayer Via Transitions ……….. 84

3.3.1 Conditions for Mitigating the Return Loss ……..……….. 88

3.4 Conclusions ……….………. 92

4.

Minimizing the Return Loss in a Practical Chip-to-Chip Link

4.2 Description of Prototypes ……… 95

4.3 Designing of Chip-to-Chip Links for Minimum Return Loss ...……….. 98

4.4 S-parameters and TDR Measurements ………. 100

4.5 Conclusions ……….……….. 105

5.

Conclusions and Opportunities for Future Research

5.2 Opportunities for Future Research .………..……… 109

Appendix: List of Publications ………. 111

x LIST OF TABLES

1. Comparative features between SOP and SOC ………..……….. 9

LIST OF FIGURES

1.1 Trend of electronic products toward the fully-integrated convergent systems ….… 2 1.2 SOC approach for fully-integrated systems …………...……….... 4

1.3 SIP approach integrating memory, memory controller, and a microprocessor into a single package/module using wirebonds ………...……… 5 1.4 Generic SOP approach ………..………….. 6

1.5 Fundamental basis of SOP with two parts: the digital CMOS IC regime, and system regime ……….……….. 10

2.1 Multilayer via transition interconnecting a surface trace and an inner trace in a high-density package/board ……….. 19

2.2 Multilayer via transitions interconnecting M coupled surface traces and M coupled inner traces in a high-density package/board ……….… 20

2.3 Decomposition of a multilayer via transition into exterior and interior problems using the equivalence principle (power/ground vias are not shown) ……….……. 22

2.4 a) Multiple vias inside a parallel-plate cavity and the corresponding dimensions and

b) model for N vias in Fig. 2.4a when the equivalent principle is applied ……….. 25

2.5 Signal via with Q power/ground vias disposed in an arbitrary spatial distribution

showing the corresponding dimensions: a) perspective view, and b) side view ... 31

2.6 a) 3D model of a single via with four P/G, and b) model implemented and simulated in HFSS ………....……….. 33

2.7 Real and imaginary parts of 1/Y11 for a single via with four P/G vias. Full-wave

versus Foldy-Lax (n=0) confrontation ………..……… 34

2.8 Real and imaginary parts of 1/Y12 for a single via with four P/G vias. Full-wave

versus Foldy-Lax (n=0) confrontation ………..……… 34

2.9 N signal vias with Q power/ground vias disposed in an arbitrary distribution showing the corresponding dimensions ……….. 35

xi

2.10 3D model of two signal vias with three P/G and the port corresponding assignation ………..……….. 38 2.11 Re(1/Y11) and Im(1/Y11) for two signal vias with three P/G vias ……….. 38 2.12 Re(1/Y12) and Im(1/Y12) for two signal vias with three P/G vias …………..…….... 39 2.13 Re(1/Y13) and Im(1/Y13) for two signal vias with three P/G vias ………..…... 39 2.14 Re(1/Y14) and Im(1/Y14) for two signal vias with three P/G vias ……….. 39

2.15 Hybrid model for including the pad and the antipad holes effects due to the finite thickness of the metal planes ……… 40

2.16 Magnitude of the S-parameters for a single via with four P/G vias considering effects due to the metal thickness ……….... 43

2.17 Phase of the S-parameters for a single via with four P/G vias considering effects due to the metal thickness ………. 43

2.18 TDR for single via with four P/G vias considering effects due to the metal thickness ………. 43

2.19 Magnitude of the S-parameters for two vias with three P/G vias considering the effects due to the finite metal thickness ………... 44

2.20 Phase of the S-parameters for two vias with three P/G vias considering effects due to the finite metal thickness ……… 44

2.21 TDR (at port 1) for two vias with three P/G vias considering effects due to the metal thickness ………... 44

2.22 TDR (at port 3 and 4) for two vias with three P/G vias considering effects due to the metal thickness ……….… 45

2.23 Equivalent circuit model for one signal via including ground power/ground vias arbitrarily disposed inside a parallel-plate cavity ……… 47

2.24 Inductive effects due to a signal via and Q power/ground vias ……… 48

2.25 a) Circuit model for one signal via sharing Q power/ground vias, and b)

combination of Q power/ground vias and one signal via into an equivalent

inductance ………... 49

2.26 Equivalent circuit model for multiple signal vias with an arbitrary distribution of ground power/ground vias inside a parallel-plate cavity ………... 51

xii 2.28 a) Circuit model for two signal vias sharing Q power/ground vias, and b)

combination of Q power/ground vias and two signal vias into equivalent

self-inductances and and mutual inductance ………... 53

2.29 a) Six signal vias with two power/ground vias, and b) the corresponding port assignation at the antipad holes ……… 56

2.30 Circuit model for six signal vias with two power/ground vias (equivalent mutual inductances are shown only for via 1 with other vias) ………... 56

2.31 Comparison between S-parameters predicted by HFSS and those predicted by the circuit model of Fig. 2.30 ……… 57

2.32 Comparison between S-parameters predicted by HFSS and those predicted by the circuit model of Fig. 2.30 ……… 57

2.33 a) Segmented full-wave model, and b) segmented circuit model for representing multilayer via transitions ………. 58

2.34 a) Segmented full-wave model for two coupled multilayer via transitions, and b) the corresponding segmented circuit model ……….. 60

2.35 Comparison of return loss (S11) in magnitude and phase predicted by the full model, the segmented full-wave model (hybrid model), and the segmented circuit model ………. 60

2.36 Comparison of insertion loss (S21) in magnitude and phase predicted by the full model, the segmented full-wave model (hybrid model) and the segmented circuit model ………. 61

2.37 Comparison of near-end crosstalk (S31) in magnitude and phase predicted by full model, the segmented full-wave model (hybrid model) and the segmented circuit model ………. 61

2.38 Comparison of far-end crosstalk (S41) in magnitude and phase predicted by full model, the segmented full-wave model (hybrid model) and the segmented circuit model ………. 61

3.1 Circuit model for an array of multiple signal vias and power/ground vias inside a parallel-plate cavity ………. 65

xiii

3.2 Circuit model for calculating the input impedance | at port 2p –1 showing

the corresponding simplification at the right side ………... 66

3.3 Structures used to investigate the impact of the number of power/ground vias, and the corresponding spatial distribution on : a) two P/G vias, b) three P/G vias, and c) four P/G vias ……… 73

3.4 versus and R for the test structures shown in: a) Fig. 3.3a, and b) in Fig. 3.3b, 3.3c ……….. 74

3.5 Structures used to investigate the impact of the number of power/ground vias and the corresponding spatial distribution in the value of : a) one P/G via, and b) two P/G vias ………. 75

3.6 versus for the test structures in Fig. 3.5a and 3.5b ………... 76

3.7 Flow chart for simultaneously minimizing the return-loss and crosstalk in multiple vias (antipad radius b and the number of the power/ground vias W are the varying parameters) ………..… 78

3.8 Six signal vias disposed in a 2×3 array with a) two GND vias, and b) seven GND vias ……… 79

3.9 and corresponding to the signal vias depicted in Fig. 3.8a ……… 80

3.10 Equivalent impedance for signal vias depicted in Fig. 3.8a ……….…... 80

3.11 and corresponding to signal vias depicted in Fig. 3.8b ………... 81

3.12 Equivalent impedance for signal vias depicted in Fig. 3.8b ………...…. 81

3.13 Magnitude of the return loss corresponding to the signal vias at the edge corners (vias 1, 2, 5 and 6) ……….. 82

3.14 Magnitude of the return loss corresponding to the signal vias at the center of the array (vias 3 and 4) ……….… 82

3.15 Magnitude of NEXT between vias 3 and 1 ……….. 83

3.16 TDR waveforms at signal via 1 for the arrays with two and with seven GND vias when no impedance matching is achieved ( ), and for impedance matching ( ) ………...……….…….… 83

3.17 Exterior problem and the corresponding circuit model ……….…. 85

xiv 3.19 Four-layer via transition and the corresponding dimensions and circuit model … 88

3.20 Comparison of the return-loss (S11) predicted by the circuit model and full-wave simulations for the via transition depicted in Fig. 3.19 ………..…… 88

3.21 Simplified circuit model partitioned into several T-networks for a multilayer via transition embedded between two traces ……… 89

3.22 Circuit model to calculate the partial input impedance at the k-th T-network …… 89

4.1 Cross section of a symmetrical chip-to-chip link including multilayer via transitions ……….… 96

4.2 A four-layer via transition and the corresponding dimensions and circuit model .. 97 4.3 A six-layer via transition and the corresponding dimensions and circuit model … 97

4.4 Chip-to-chip links including four-layer via transitions with probing pads for measurement purposes ………..… 97

4.5 Chip-to-chip links including six-layer via transitions with probing pads for measurement purposes ………. 98

4.6 and , versus de corresponding to the four-layer via transition ……...…. 99

4.7 , , and , , and versus de corresponding to the six-layer via

transition ………..………… 99

4.8 Equivalent impedance Ze versus de corresponding to four-layer and six-layer via

transitions ………...…… 100

4.9 Photograph of the fabricated chip-to-chip links using four-layer via transitions and the probes used to collect the measurements ……….………. 101

4.10 Photograph of the fabricated chip-to-chip links using six-layer via transitions and the probes used to collect the measurements ………..………… 101 4.11 De-embedded return-loss for the fabricated chip-to-chip links ……….. 102

4.12 Measured TDR profile for the three chip-to-chip links using four-layer via transitions ……….. 103

4.13 Operation regions (dominantly capacitive, inductive and matched) for chip-to-chip links using four-layer via transitions ………...………… 103

4.14 Measured TDR profile for the two chip-to-chip links using six-layer via transition ……….. 104

xv

4.15 Eye diagram at 20 Gbps corresponding to chip-to-chip links using a) non-matched six-layer via transitions and b) matched six-layer via transitions …………..…… 105

1

CHAPTER I

Fully-Integrated Electronic Systems:

Requirements and Challenges

1.1 Introduction

During the last four decades, electronics technology based on semiconductor

devices has revolutionized every aspect of human life. Thus, electronic products

have emerged in several fields such as automotive, computing,

telecommunications, aerospace, military, and medical care. In this regard, the

shrinking of transistor size has yield the integration of hundreds of millions of

transistors on a single chip, allowing a considerably high computing capacity. In

this way, a wide variety of electronic systems with powerful computing capabilities

has been developed.

Thus, due to the advances in electronics technology, today’s modern life is

inevitably dependent on the complex convergence of technologies into products

designed to provide solutions in many applications. In fact, there is an emerging trend within the electronics industry which is referred to as “convergent electronic systems” [1]. This trend is characterized by the convergence of computer,

communications, consumer, and biomedical functions (among others) into one

product. As shown in Fig. 1.1, the development of these systems is leading to

miniaturized and portable multi-function systems. Several examples of electronic

systems in the past and in the near future are depicted in Fig. 1.1. In fact,

fully-integrated systems are expected to be about a cubic centimeter in size with not

only computing and communication capabilities, but also with devices to sense and

digitize signals, to monitor, to control, and to communicate anyone anywhere.

Thus, when developing these systems, several technical aspects have been

2

Fig. 1.1 Trend of electronic products toward the fully-integrated convergent

systems [2].

On the other hand, the projected market for fully-integrated systems will

demand increased performance, smaller size, lower power and lower cost than that of today’s systems. Unfortunately, these demands cannot be fulfilled with

conventional packaging and interconnect technologies because of the

corresponding limitations in interconnect density, thermal dissipation, power

integrity, and signal integrity [3]. In consequence, advanced packaging

technologies are starting to be developed to allow three-dimensional (3D) integration of digital, analog, and mixed-signal chip technologies to build reliable systems [4].

In this chapter, an overview about fully-integrated electronic systems is

presented including the aspects related to the corresponding implementation.

Thus, by recognizing the requirements of these systems, the related challenges

are exposed. Visualizing these challenges allows identifying the opportunities for

research and development of packaging technologies, in particular of

system-on-package (SOP). As it will be shown later, vias are key structures in the

development of a reliable wiring technology for SOP and therefore; accurate

modeling of these structures at microwave frequencies is a vital part of the design

cycle. Furthermore, mitigation of the undesirable effects due to vias such as

3

1.2 Approaches for Fully-Integrated Systems

Before reviewing the system integration approaches for fully-integrated convergent

systems, it is important to mention that the ultimate goal of an entire electronic

system is to capture input signals, carrying out a processing, and providing output

signals. In general, the input and output signals are provided/received by the user

in response of a need. So, the necessary basic building blocks of an electronic

system are: power sources, integrated circuits (ICs), passive components,

interconnections, packages/substrates, heat removal structures, sensors, and

actuators. On the other hand, traditionally, the electronics industry has been guided

by the following system aspects: high-reliability, high-performance, low power

consumption, small size, and fast time to market. Thus, it is not a surprise that

fully-integrated convergent systems are driven by the same aspects. In this way,

the full integration of all building blocks of an electronic system is the goal of the

integration approaches. For this reason, in the following sections, the most

important concepts associated with system integration paradigms are presented

and discussed.

1.2.1 System-On-Chip (SOC)

SOC is a system integration approach that integrates a large number of transistors

as well as various mixed-signal active and passive components into a single planar

chip in order to build fully-integrated systems. Furthermore, SOC can be defined as the realization of an entire system’s functionality in a single, large IC with various

semiconductor technologies. Thus, SOC ICs must integrate digital, RF, analog,

and other functions in order to perform all the operations demanded to the

electronic system. Fig. 1.2 highlights the SOC integration approach. As expected,

SOC is guided by the technology roadmap for semiconductors, which is in turn based on Moore’s Law. If fully-integrated systems based on the SOC approach can

be cost-effectively designed and fabricated while offering high performance, high

4

Fig. 1.2 SOC approach for fully-integrated systems [2].

Unfortunately, at this time, there are many technical, financial, and strategy

challenges that obstruct the realization of the SOCs for all applications. One of the

most important problems to be faced by technologists developing SOC is the long

design time due to the complexity of integrating diverse semiconductor

technologies (such as bipolar, CMOS, Silicon-Germanium (SiGe), and

optoelectronics) for simultaneously performing several system functionalities (e.g.

digital, analog, mixed-signal processing, RF, optoelectronics, etc.) Another problem

is the high cost of integrating different semiconductor technologies into a single

chip with multiple voltage levels and dozens of mask steps. Thus, as can be

concluded, SOC presents major challenges for the realization of cost effectively

fully-integrated systems. Fortunately, it is not the only available alternative.

1.2.2 System-In-Package (SIP)

Due to the problems related to SOC, alternative system integration approaches

have been proposed. SIP is among these approaches, and can be defined as 3D

or vertical stacking of ICs into a single package or module, which contrasts the

planar nature of SOC. In fact, vertical stacking in SIP can be achieved using

5 (TSV), flip-chip, etc. [1]. Thus, SIP overcomes some of the above SOC limitations,

such as cost, design complexity and time to market.

SIP is often alternatively called 3D ICs or 3D stacked die/package. This

approach allows designers to stack multiple ICs at a low cost and into a SSF

package. In this case, the vertical die-to-die via pitch in a 3D stacked package is

very small; so, designers can arrange digital functional modules across multiple

dies. Moreover, stacked digital ICs have shorter wires than conventional

packaging, which can be translated into less wire delay and less power

consumption. As can be noticed, there are major benefits offered by the SIP

approach: simpler design and operation verification, a process with minimal mask

steps, minimal time-to-market, and minimal intellectual property (IP) issues. Thus,

SiP provides major opportunities in both miniaturization and integration for

advanced and portable electronic products.

Fig. 1.3 SIP approach integrating memory, memory controller, and a

microprocessor into a single package/module using wirebonds [2].

There are, however, some problems associated with the SIP approach, which

are in a certain way similar to SOC. An SIP, defined above as vertical stacking of

ICs, includes only the IC integration and hence addresses only about 10 to 20

percent of the system. Additionally, the integration of discrete passive elements

such as resistors, inductors and capacitors is not covered in current SIP

6

SIP approaches only integrate ICs, this may be considered as a “pseudo full-integration approach” because the ultimate goal of a fully-integrated system is not

achieved. In fact, some of the roadblocks for full system integration remain

unsolved such as in SOC. Even though limited benefits are offered by SIP,

currently, about fifty IC and packaging companies are designing and fabricating

products based on SIP modules. For example, using SIP, a 3G cell phone with

multiple semiconductor technology ICs, discrete passive components, and RF

radios can be developed in a few months. Integration of this functionality into an

SOC would be cost prohibitive, technically impossible, or beyond a viable market

window.

1.2.3 System-On-Package (SOP)

SOP is a system integration approach that seeks to integrate multiple system functions into one compact, low-cost, and high-performance packaged system [1] –

[4]. To implement SOP, a high-density substrate with embedded passives, active

devices, and integrated optics are required. A generic SOP is illustrated in Fig. 1.4, showing the similarity with SOC in the fact that it is a “single component” system.

Fig. 1.4 Generic SOP approach [1].

However, in contrast to SOC, SOP is a system-level package containing multiple

large ICs that integrate all the system functions. Furthermore, SOP can be seen as

7 single package, while maintaining a low-cost profile and SFF supporting mixed IC

technologies. SOP accomplishes this goal by achieving ultra-high wiring density,

using multiple layers, and applying a variety of embedded ultrathin-film component

integrations [5]. For this reason, a very important point to be mentioned here is the

fact that microvias are a key feature enabling SOP realization. The Association

Connecting Electronic Industries defines any via that is equal or less than 150 µm (6 mils) in diameter as a “microvia”. In this regard, considerable advances in

fabrication at large scale of buried and blind microvias within high-density

packages and boards have been reported to date.

Notice that the SOP paradigm proposes a unified chip-package view of the

design process. Thus, SOP is more than SIP, which contains only digital wiring to

interconnect ICs and requires two levels of packaging, including a motherboard.

Finally, it is important to clarify that when all the system components (e.g., passive

components, interconnections, and thermal structures), power sources, and

system boards are integrated into a single complete system, there is no difference

between SIP and SOP.

1.3 Why SOP instead of SOC?

As previously discussed, the SOC paradigm seeks to integrate numerous system

functions on one planar substrate, called the chip. This chip requires external

connections for power supplies and input/output signals. If this can be totally

implemented on chip, SOC offers the most compact, light-weight system that can

be massively produced. However, the electronics industry is figuring out that the

SOC paradigm has fundamental engineering and financial limits [6]. The technical

SOC problems include:

1) Difficulty of capturing the requirements and composing the

specifications of a mixed digital-analog-RF microwave system in a unified

and machine-processable form. In other words, there is a lack of experience

about integrating disparate semiconductor technologies (CMOS, SiGe,

8

deteriorate the overall performance; therefore, the SOC benefits can be

marginal.

2) Lack of design test tools for mixed-semiconductor technologies, for

trade-off evaluation, synthesis, and verification. Additionally, currently there

are limited model libraries that capture material-processing, circuit design,

and architectural information for modeling and design.

3) Lack of design tools for partitioning, floor planning, device placement,

routing, and other physical design tasks. This problem limits the integration

of heterogeneous technologies and components on the same IC.

4) Mechanical, thermal, and manufacturing-related problems. For

example, a high cost for large ICs is expected due to the high cost of wafer

fabrication and the low yield for technologies with minimum feature size of

less than 0.1-micron.

Due to these problems, fully-integrated systems based on the SOC approach

require long design and test cycles due to the large complexity of the system. In

fact, due to the long design cycle, an SOC system may face obsolescence due to a

rapid increase in product requirements in the market, and thus, it represents a

high-risk investment for the foundry and the product developer. However, SOP can

address the drawbacks of both SOC and SIP approaches, as well as those of

traditional packaging. In this way, SOP overcomes both the computing and

integration limitations of SOC, SIP, multichip modules (MCMs), and traditional

system packaging. Moreover, 3D SOP addresses the wire delay problem by

enabling the replacement of long, slow global interconnects with short, fast vertical

routes based on microvias.

1.3.1 SOP Technical Advantages

Recent advances in manufacturing technology will lead to low cost and

high-density packages and boards. Thus, SOP can provide strategic and tactical

advantages when using high-density packaging for high-performance digital

systems but also for fully-integrated systems. The advantages that SOP offers

9

 Higher Memory bandwidth.

 Transfer of interconnection functionality to a high-density substrate.  Improved system integration (noise isolation and feasibility of integrating

passive components).

SOP has rapidly penetrated most major market segments: consumer

electronics, mobile, automotive, computing, networking, communications, medical

electronics, etc. The SOP benefits are for different market segments but they share

some common elements. Time to market, size, power requirements and cost have

resulted in the strongest initial penetration in mobile communications. A summary

about the pros and cons related to SOP and SOC are listed in Table I.

Technical Features

SOP SOC

PROS Different front-end technologies; GaAs, InP, Si, SiGe, etc.

Better yield at maturity (this depends upon complexity)

Different device generations Greater miniaturization

Re-use of common devices Improved performance

Reduced size vs. conventional

packaging

Lower cost in volume

Active & passive devices can be embedded

CAD systems automate interconnect design

Individual components can be upgraded Higher interconnect density

Better yield for smaller chip sets Higher reliability (not true for very large die)

Individual chips can be redesigned cheaper

Simple logistics

Noise & crosstalk can be better isolated Faster time to market

CONS

More complex assembly Difficult to change

More complex procurement & logistics Single source Power density for stacked die may be

too high

Product capabilities limited by chip technology selected

Design tools may not be adequate Yield limited in very complex, large

chips

10

The SOP paradigm creates synergy between CMOS and system integration

and this synergy overcomes both the fundamental and integration limitations of

SOC and SIP, which are limited by CMOS. In this regard, while Si technology is

great and matured for transistor density improvements from year to year, it is not

the optimal platform to integrate system components such as power sources,

thermal structures, packages, boards, and passives. These are highlighted in Fig.

1.5.

Fig. 1.5 Fundamental basis of SOP with two parts: the digital CMOS IC regime,

and system regime [2].

1.4 Requirements for SOP

The general requirements for SOP are many and the relative importance varies

with the application. However, these general requirements can be summarized in

the following areas [5]:

Electrical interconnects. SOP devices require high-density substrates with

narrow trace widths and thousands of microvias in order to achieve vertical

integration of different ICs and passive components. Thus, SOP provides a unique

opportunity for translating the global IC wiring to the package for enhanced signal

integrity performance. In this regard, recent developments in advanced build-up

11 dielectrics, conductor geometries with submicron precision, and low-cost

processes for multilayer stacked via interconnects [8]. Moreover, because SOP

devices require more ICs and other components embedded into the package, the

signal routing complexity is continuously increasing and therefore vertical

interconnects (e.g., vias and microvias) have become one of the most important

structure for reliable SOP implementations. Vias are extensively used for signal

interconnections when a signal flows between layers, or when a plane is connected

to another plane providing a low impedance current path. In this way, vias

decrease the routing complexity, provide a low impedance power/ground network

and allow 3D system integration. Nevertheless, two signaling features are very important for vertical interconnects based on vias and microvias: a) high-speed, for supporting high-data rates and high-frequency analog signals, and b) high-density, to allow 3D integration of the entire systems into a compact space. However, even though vias play a key role in the implementation of high-density chip-to-chip links,

these structures also introduce impedance mismatch, crosstalk and

electromagnetic interference (EMI), causing severe signal and power integrity

problems. Consequently, fast and accurate techniques to model hundreds of

thousands of vias in multilayered high-density packages are required for a

successful SOP implementation.

Chip-to-package interface: Current approaches for lead-free soldering

techniques present major challenges in both dispensing the underfill and ensuring

fatigue resistance as solder bumps shrink in height. Thus, recent SOP research

advances concerning the chip-to-package interface include the extension of solder

bumps to stretched-solder columns and improvements in underfill technology [9].

High-quality embedded passives: Designers have begun to use multilayer

ceramic and multilayer organic structures with liquid crystal polymer (LCP)

technology to embed passives elements in an efficient way in the package,

including high-Q inductors, capacitors, matching networks, low-pass and

12

Analog/RF components: The recent development of thin-film RF materials and

processes allows designers bringing the SOP concept into the RF area to meet the

rigorous needs of wireless communication. Thus, researchers are addressing

critical problems such as board-compatible embedded antennas and switches,

low-loss and low-cost boards, low-crosstalk embedded transmission lines, and

single-mode packages, as well as design rules for vertically integrated transceivers over a

wide frequency range [11].

Optical interconnects: A high-speed optical clock and data transport simplifies

the digital architecture by requiring fewer parallel transmission lines. Moreover,

optical links present low crosstalk and they are not susceptible to electromagnetic

interference (EMI) noise. Thus, researchers have developed a low-temperature

polymer process to fabricate and integrate optoelectronic components such as

micro lens arrays, lasers, waveguides, splitters, couplers, gratings, and photo

detectors on printed wiring boards for mixed-signal SOP applications [12].

Additionally to these requirements, small form factor (SFF) packages with high

functional density, high-frequency operation, and low cost must be designed. Also,

a package for SOP must include a good thermal dissipation for high reliability of

interconnects (e.g., avoiding cracks due to thermal and mechanical stress). Although SOP takes advantage of SOC and SIP approaches under the “More than Moore” approach [6], there are many challenges that impede the ultimate

realization of optimal SOP at the moment. In the next section, vias as key enabler

of high-density interconnects is discussed.

1.5 Electrical Challenges in SOP Realization

SOP presents new design complexities and challenges over traditional packaging

due to the presence of multiple ICs, embedded passives, and other components

connected into the package. In consequence, SOP is expected to present

interactions between different components of the system originating the need of

13 example, thermal dissipation imposes the most serious bottleneck for SOP

realization due to temperature gradients in multilayer substrates with different coefficient of thermal expansion (CTE) [15] – [16]. Because high-density packages

can use different dielectric materials with different CTE, mechanical stress on

copper-based interconnects may cause catastrophic electrical failure. Moreover,

due to the high-density integration in SOP devices, the interaction between the

thermal, mechanical, and electrical properties of the materials would significantly

impact the electrical properties of interconnects. Consequently, SOP would require

multi-physics analysis, design, and optimization in order to realize reliable

fully-integrated systems.

In this work, the electrical challenges related to SOP implementations are

considered. Among these challenges, there is a lack of package/chip co-design

methodologies and signal integrity/power integrity co-analysis at high-frequencies.

Besides, a good package design with accurate characterization and modeling must

be part of chip-package co-design methodology. Hence, excellent performance of

packages and interconnects is a crucial factor to achieve high-speed and wider

bandwidths. This is due to the fact that poor electrical performance of packages

and interconnects may degrade the entire system performance, especially when

digital signals processed by ICs present fast edge rates. Since faster edge rates of

digital signals imply higher frequency harmonics, the accurate characterization and

modeling of packages and interconnects at microwave frequencies is a critical

design step in the SOP design flow.

Since SOP devices require high-density substrates with thousands of vias,

multilayer via transitions need to be accurately modeled and optimized at

microwave frequencies. If multilayers via transitions are not well designed

(electrically optimized), when digital signals propagate throughout them crossing

power/ground planes with different voltages, the return current paths could behave

as electrical discontinuities causing severe signal degradation. In fact, the return

current for multilayer via transitions behaves very different from return path for

14

that the displacement current at the vias is a distributed property of the parallel

power/ground planes and this fact makes very hard to model the return path in

multilayer via transitions. Different modeling strategies can be found in the

literature to address the problem of modeling vias in multilayer packages. Most of

them are based on numerical methods, whose computational requirements rapidly

grow as the size and complexity of the interconnect structure increase. In contrast,

to overcome computational limitations, circuit models for vias have been proposed

with the purpose to perform large system-level signal integrity simulations.

As can be noticed, efficient modeling of vias in high-density packages becomes

essential in the SOP design process to obtain the best tradeoff between cost and

performance. This is a challenging task because of the large number of vias that

must be considered to model a realistic SOP package. As it will be explained, vias

and microvias can excite parallel-plate modes in the power/ground planes of a

multilayered package. These parasitic modes are the dominant source of parasitic

radiation, crosstalk, and impedance mismatch, causing signal integrity problems.

Since crosstalk and impedance mismatch due to vias are exacerbated as the

frequency operation of chip-to-chip links increases, fast and accurate modeling

techniques are needed for successfully designing SOP packages. Although SOP

can address the SOC and SIP limitations, much work is required to be done,

mainly in the signal and power integrity area.

1.6 Objective and Thesis Organization

As discussed throughout this chapter, vias and microvias play a key role in the

implementation of reliable 3D high-density interconnects for SOP devices.

Nevertheless, due to the signal and power integrity problems caused by them,

electrical modeling and optimization is mandatory in order to achieve low-power,

high-bandwidth links for SOP based fully-integrated systems. From an exhaustive

review in the literature, it was found that contributions for the electrical modeling

and optimization of multilayer via transitions in high-density packages and boards

15 currently used as the main tool for analyzing vias, the number of these structures

required for real SOP implementations (tens of thousands or even more) makes

unpractical using the full-wave approach. Furthermore, since fast to time to market

are required for SOP devices, the accurate characterization and modeling of vias in

high-density packages must be faster than full-wave approaches.

For this reason, the objective of this thesis is to develop a systematic electrical

modeling for multilayer via transitions at microwave frequencies as well as the

optimization of these structures from a point of view of signal integrity. In this way,

the contributions of this work will allow exploring the design space in a systematic

and fast manner, especially when the SOP system is highly constrained (in terms

of power, area and cost) and when a fast time to market is needed.

The full-wave modeling of vias based on the Foldy-Lax theory and the

equivalent principle is reviewed in Chapter 2 in order to develop a simplified

framework to calculate the Y-parameters of vias in a parallel cavity (taking into

account the distributed property of the return path). Additionally, a circuit model is

proposed and a general methodology to calculate the corresponding electrical

parameters is developed in order to analyze the reflection loss and crosstalk in

multilayer via transitions structures.

Based on the results presented in Chapter 2, in Chapter 3 reflection loss and

crosstalk analyses are performed in order to develop the corresponding mitigation

techniques. The benefits of the proposed solutions are demonstrated in Chapter 4

by using as test vehicles several chip-to-chip prototypes. As demonstrated by

S-parameter measurements corresponding to optimized and non-optimized

chip-to-chip links, the proposed mitigation techniques provide a great insight regarding

how to minimize the reflection and crosstalk in practical chip-to-chip buses and

how this minimization is translated into a great improvement of the signal-to-noise

(SNR) ratio of signals propagating in multilayer packages. Finally, Chapter 6

summarizes the contributions of this thesis. Also research directions are discussed

17

CHAPTER II

Full-Wave and Circuit Modeling of Multilayer

Via Transitions in High-Density Packages

2.1 Introduction

Vias play a key role in the reliable implementation of high-density interconnects for

3D system integration. Because vias are extensively used in high-speed links to

interconnect signal traces and power/ground planes at different layers, these

structures have become one of the most important features for the implementation

of high-speed and high-density interconnects for SOP devices. Furthermore, vias

reduce the signal routing complexity, provide a low impedance power/ground

network and allow 3D system integration. Consequently, the characterization,

modeling, and optimization of high-density, high-speed, and low-power

interconnects based on via structures represent a fundamental part of a packaging

design cycle. On the other hand, with the ever-rising clock rate in digital systems,

the spectral content of digital signals is becoming wider and wider and

interconnects must be designed to operate at higher frequencies than before.

Unfortunately, vias cause impedance mismatch, crosstalk, mode conversion, and

other signal integrity issues in a signal link path [17]. Vias passing through a

parallel power/ground plate pair could be affected by emissions originated at the

power distribution network, resulting in degraded signal quality. Similarly,

high-speed transient currents flowing along vias could also excite the multiple

parallel-plate environments existing in packages and PCBs, causing serious voltage

fluctuations in the power distribution network and introducing electromagnetic

interference (EMI) problems. Therefore, the electromagnetic modeling of vias in

parallel plates plays a critical role when analyzing signal integrity, power integrity,

and EMI for multilayer packages and boards in early design stages.

Basically, the modeling of vias may be accomplished through: a) carrying out

18

behavior of vias by means of equivalent circuit models. As it is well-known,

full-wave analysis of complex structures is often computationally prohibitive. Moreover,

full-wave simulations require considerable time and effort on the part of the

designer; this becomes a drawback when short time-to-market is needed.

Fortunately, equivalent circuit models can be developed using full-wave

simulations. Circuit models for vias are preferred for signal integrity analysis

because these can be easily integrated in SPICE-like environments with the

purpose of performing system-level signal integrity simulations. Furthermore,

physics-based circuit models relate geometry parameters with electrical properties.

This fact allows the fast analysis and design of optimized vias because circuit

models can be scaled according to physical geometry and material properties.

Thus, due to the massive number of vias in high density packages and boards,

physics-based circuit models for vias are preferred over full-wave-only approaches.

Notice, however, that although circuit models provide fast analysis and design,

full-wave analysis is often required in order to capture the details that are ignored by

the circuit modeling approach. This means that both types of analysis are

complimentary and can be of great help when properly applied.

In order to provide a clear and solid understanding of the electrical properties of

vias in compact space environments such as SOP, the full-wave as well as the

equivalent circuit modeling of vias in multilayered structures is presented in this

chapter. For this purpose, a review of the state-of-the-art regarding full-wave

numerical methods and equivalent circuit models for analyzing vias is carried out.

Additionally, in this chapter, a physics-based equivalent circuit model for coupled

vias in a parallel-plate environment is developed as well as the corresponding

closed-form equations for calculating the model parameters. Thus, there are two

main contributions presented in this chapter: 1) a new and systematic approach for

full-wave modeling of multilayer via transitions based on a simplification of the

Foldy-Lax Theory, and 2) the development of a physics-based circuit model which

allows representing multilayer via transitions in compact spaces when the distance

19

2.2 Segmented Modeling of Multilayer Via Transitions

Vias are mainly used to interconnect traces and devices located at different layers

within a package; therefore, these structures present a multilayer nature. Fig. 2.1

shows a multilayer via transition interconnecting two single traces, one located at

the surface of the package/board and another located at an inner layer level.

Similarly, Fig. 2.2 shows multilayer via transitions interconnecting M traces located

at the surface of the package/board and M inner traces. In both figures, the metal

layers are labeled as , where p = 1, 2,…, P, which is used to number the layer

level from the top of the structure. In this case, the metal planes can be either used

as power (PWR) or ground (GND) planes for the power delivery network (PDN).

Fig. 2.1 Multilayer via transition interconnecting a surface trace and an inner trace

in a high-density package/board.

Nowadays, a common practice for modeling multilayer via transitions similar to

Fig. 2.1 and 2.2 is using full-wave methods. Unfortunately, this approach becomes

unsuitable for analyses including many multilayer via transitions because of the

required computational resources and simulation time, which may be prohibitive at

early design stages. Furthermore, simultaneously minimizing undesired effects

such as return loss and crosstalk due to via transitions is very hard to achieve

20

dimensions of these structures with the corresponding electrical properties.

Nevertheless, in spite of these inconveniences, using full-wave solvers as the main

tool for analyzing effects due to multilayer via transitions in modern packaging is

still a common practice both in the academy and industry. In order to overcome the

drawbacks associated to model multilayer via transitions using full-wave

approaches, a segmented modeling methodology has been developed here. In this

section, this methodology is explained in detail.

Fig. 2.2 Multilayer via transitions interconnecting M coupled surface traces and M

coupled inner traces in a high-density package/board.

When a signal is transmitted from port 1 to port 2 through the multilayer via

transition depicted in Fig. 2.1, the signal firstly propagates in a quasi-transversal

electromagnetic (TEM) wave mode supported by the surface trace that presents a

characteristic impedance Zc. Moreover, if the metal layer M1 is included in the

layout of the package/board, the surface trace can be designed for operating in

coplanar waveguide-like (CPW) mode configuration. Then, this quasi-TEM wave

excites a vertical current in the signal via 1 and the quasi-TEM wave is converted

into a coaxial TEM wave at the antipad hole due to the finite thickness of the metal

layer M2. In most practical designs, the coaxial TEM mode assumption at the

antipad holes is valid even at very high frequencies. This assumption is based on

the fact that the cutoff wavelength of the higher-order modes for coaxial

21





n a b

c

  2

 (2.1)

where n is an integer number indicating the higher coaxial mode index, b is the

antipad radius and a is either the pad radius or the via radius when no pad is used.

For many practical PCBs, the term (b–a)is typically less than 0.5 mm. This implies

that the cutoff wavelength of the first high-order coaxial mode is about 1 mm, i.e.,

the corresponding cutoff frequency is about 300 GHz (beyond the frequency range

of interest in this project). Due to the fact that the dimensions in high-density

packages and boards are smaller than PCB dimensions, the cutoff frequency in

this case is even higher than 300 GHz. Therefore, all the higher order coaxial

modes at the antipad holes are neglected from the analysis presented in this work.

Other approaches have reported that the TEM approximation for a coaxial-type

structure provides accurate results, presenting additional justification of this assumption [19] – [20]. Continuing with the explanation about propagation through

the multilayer structure, once the signal reaches the via, part of the coaxial energy

traveling in TEM mode is converted into evanescent/propagating cylindrical waves

at the parallel-plate cavity formed by the metal layers M2 and M3. Since the edges

of the substrate between the metal layers is mostly terminated as open circuits,

propagating cylindrical waves reflect back and forth from these edges, leading to

the formation of standing waves at certain frequencies. At/near the resonance

frequencies of the planes, these waves cause significant coupling, resulting in EMI

within the cavity as well as in radiation from the edges of the substrate. The return

path for the current due to these cylindrical waves is provided by the ground/power

(PWR/GND) vias. Afterwards, the cylindrical waves in the cavity is converted again

into a coaxial TEM mode at the antipad hole in the metal layer M3 and similar

conversions occur at the different layers until the signal reaches the inner trace

located at the metal layer MP-1. Similarly to the quasi-TEM wave supported by the

surface trace, the inner trace supports a TEM wave if this trace is designed for

22

On the other hand, when many signals are transmitted throughout the

multilayer via transitions depicted in Fig. 2.2, the signals propagate as quasi-TEM

waves supported by the surface traces. Similarly to the single trace case, each

trace in Fig. 2.2 presents a characteristic impedance Zc. However, it is important to

point out that the characteristic impedance associated to a single trace having

neighbor traces is different from the characteristic impedance of a single isolated

trace. Thus, in this case the quasi-TEM waves are converted into coaxial TEM

waves at the antipad holes and then these are converted into cylindrical waves.

Again, these conversions occur until the signal reaches the inner traces. As can be

noticed, the propagation of signals throughout multilayer via transitions is a

consecutive conversion of coaxial TEM waves into cylindrical waves. Fortunately,

the presence of coaxial TEM waves at the antipad holes allows using the

equivalence principle in order to simplify the analysis of multilayer structures. The

equivalence principle has been widely used to model multilayer via transitions in

packages and boards [21] – [35]. Basically, this principle allows assuming that a

coaxial TEM wave at the antipad holes can be replaced with an equivalent

magnetic frill current that excites the cylindrical waves at the parallel-plane cavity.

Additionally, the metal layers (including the antipad hole) are replaced with a

perfect electric conductor (PEC) boundary. Thus, according to the equivalence

principle, the signal propagation through the multilayer via transitions depicted in

Fig. 2.1 and 2.2 can be decomposed into interior and exterior problems as shown

in Fig. 2.3.

Fig. 2.3 Decomposition of a multilayer via transition into exterior and interior

23 The two problems can be separately solved and combined in order to obtain the

response of the multilayer via transitions. Thus, multilayer via transitions can be

segmented into many smaller blocks, which is computationally more efficient than

solving the whole multilayer via transitions at once. It is important point out that

when the equivalence principle is applied, the metal planes are replaced by PEC

boundaries; therefore, the effects due to the finite thickness of the metal planes

must be separately included in the cascaded model in order to capture the

corresponding effects to preserve accuracy.

The exterior problem consists of traces that are bent into vias, whereas the

interior problem consists of magnetic sources between metal planes and vias

modeled as conducting cylindrical scattering surfaces. Extensive research effort

has been devoted to study the via-plate interactions in the literature. Thus, for vias

crossing a single plate (similar to the exterior problem), either full-wave methods or

quasi-static approaches are effective due to the localized field distribution near the vias [36] – [43]. Nevertheless, for vias crossing a parallel-plate cavity (i.e., for the

interior problem) formed by power/ground planes, the quasi-static approximation

and simple lumped circuit modeling are not suitable anymore since the

electromagnetic fields are not localized near vias. On the other hand, although

higher-order cylindrical waves are localized in the proximity of the vias as energy

stored in the electric and magnetic fields, there may be cylindrical modes

propagating over the entire parallel-plate cavity. Furthermore, since the separation

between vias is comparable to the wavelength corresponding to the highest

frequency of interest in high-speed digital circuits, lumped circuits fail to capture the

propagation nature of cylindrical waves into the cavity. This makes more difficult to

model vias crossing a plate pair than vias crossing a single plate. Nevertheless,

due to the small dimensions in high-density packages in SOP, the separation

between vias can be treated as electrically short even at frequencies of tens of

gigahertz and therefore can be modeled using circuit models without a significant

loss of accuracy. Hence, equivalent circuit models can be more efficient than

24

mentioned before, circuit models for vias are preferred for signal integrity analysis

because these can be easily implemented in SPICE-like circuit simulators.

A review of the state-of-the-art in full-wave numerical methods as well as

equivalent circuit models for modeling interior and exterior problems related to vias

are presented in order to provide a clear and solid understanding of the

corresponding electrical properties. This understanding will be fundamental in

Chapter III where techniques to minimize the reflection losses and crosstalk in

high-speed chip-to-chip links are developed. Also, the explanations presented in

this chapter will show the feasibility and accuracy of using circuit models instead of

full-wave 3D simulations to simulate vertical interconnect containing via structures.

2.3 The Interior Problem

Generally speaking, the interior problem consists of many vias inside a

parallel-plate pair formed by two metal planes as depicted in Fig. 2.4. This figure shows the

via radius a, the radius of the antipad on the power/ground planes b, the radius of

the pads c, and the relative dielectric constant and thickness of the layer between

the two P/G planes and h, respectively. The distance between vias p and q is

spq, whereas the metal layers present a thickness tc.

At the antipad hole of each via, there is a coaxial TEM mode that excites the via

and transversal magnetic (TM) cylindrical waves inside the cavity. However, the

coaxial TEM modes can be replaced by magnetic frill currents and (where i

= 1,2,…, N) located at the bottom and top of the antipads holes, which excite each

via in the cavity. In addition, the metal planes are replaced by PEC boundaries as

shown Fig. 2.4b. Notice that in the resulting model, the effect of the finite thickness

of the metal planes is not considered at this point, but it can be taken into account

after solving the model shown in Fig. 2.4b. Analytical methods for modeling vias

inside a parallel-plate cavity were firstly reported in [21] – [22]. In both cases, the

segmentation of the entire multilayer via transition was carried out based on the

equivalence principle. Thus, magnetic frill currents were assumed in the antipad

25 Unfortunately, methods in [21] – [22] were developed to model only two vias.

Moreover, those methods are restricted to an infinitely large plate pair, and

possible reflection of the propagating cylindrical waves due to the edges was not

considered in model (due to the analytical nature of the formulation).

a)

b)

Fig. 2.4 a) Multiple vias inside a parallel-plate cavity and the corresponding

dimensions and b) model for N vias in Fig. 2.4a when the equivalent principle is

applied.

Recently, however, an algorithm referred to as the Foldy–Lax multiple

scattering approach has been proposed to extend the analytical method to multiple vias in a parallel-plate cavity [23] – [29]. In fact, methods based on the Foldy–Lax

multiple scattering equations in vector spherical/cylindrical wave functions have been developed [33] – [44]. The Foldy–Lax method was originally used for multiple

26

each other’s far-field region [45]. On the other hand, a unified method has been

reported in [34], which takes into account the coupling of multiple vias with and

without pads in a much simpler and more comprehensive manner. As shown later

here, the preferred tool for analyzing vias in a parallel-plate cavity is the Foldy-Lax

approach which is faster than full-wave modeling using three-dimensional meshing

and solving the Maxwell equations for each node of the model mesh. Thus, the

multiple scattering methods can be regarded as efficient semi-analytical methods.

Although semi-analytical methods based on Foldy-Lax theory are more efficient

in time and computational resources than commercial full-wave solvers (such as

HFSS, CST, Sonnet, etc.), the required time to evaluate the semi-analytical

expressions for thousands of vias may become a drawback if high-order effects are

included in the model. Fortunately, analytical equations can be derived from the

Foldy-Lax approach bearing in mind that via structures in high-density packages

for SOP present smaller dimensions than those found on PCBs.

2.3.1 Full-Wave Approach

The vias in Fig. 2.4b can be associated to a multiport microwave network whose

admittance matrix can be obtained from the current distributions in the ports and

the voltage at the antipad holes. The detailed process to calculate the current

distribution inside vias and therefore the corresponding admittance parameters is

described in [25] – [26]. To simplify the analysis, every via in Fig. 2.4b can be

considered as a two-port network, where the upper ports ui can be grouped into a

single upper port u and the bottom ports bi into a single bottom port b. Thus, the

admittance matrix corresponding to the via array is given by:

   

  



 _{bu bb}

ub uu

Y Y

Y Y

Y (2.2)

where u and b stand for upper and bottom ports, and Y presents a size of 2N × 2N

matrix. Then, the Foldy–Lax multiple scattering method is applied to compute the