Modelling of the carrier transport properties in nanostructured devices with applications in advanced logic technologies

1

Modelling of the Carrier Transport

Properties in Nanostructured Devices

with Applications in Advanced Logic

Technologies

By

M. Sc. Héctor Manuel Uribe Vargas

A thesis submitted in partial fulfillment of the requirements for

the degree of

Ph.D. in Electronic Sciences

at

National Institute of Astrophysics, Optics and

Electronics

June 2018

Tonantzintla, Puebla

Advisor:

Dr. Joel Molina Reyes

INAOE

©INAOE 2018

All rights reserved Author hereby grants to INAOE permission

to reproduce and to distribute copies of this work partially or

ii

Acknowledgments

This thesis would not have been possible without the support of many people who have been with me throughout this journey.

I would like to thank my wife, Marione Mañon, who has been with me in this long journey, always supporting me, and always being there for me. Thank you for everything. I could not have asked for a better life partner. I love you.

To my family, for giving me the tools necessary to achieve this goal in my life.

I also express my sincere gratefulness to INAOE for being the place I called home all these years.

My sincere gratitude to my advisor, Joel Molina, for the continuous support and advises in this research work.

To my thesis committee: Dr. Edmundo Gutierrez, Dr. Alfonso Torres, Dr. Francisco Javier Wade, Dr. Roberto Murphy and Dr. Alberto Herrera; your comments and insights have made this work better.

I would like to thank the laboratory staff: Oscar Pestaña, Victor Aca, Armando Hernandez and Ignacio Juarez, without your help, this work could have not been done.

Also to my friends: Oscar Huerta, Manolo Pérez, Alejandro Martínez, Héctor Bandala, Ricardo Jiménez, and everyone, who have made this journey mucho more enjoyable .

iii

Abstract

Ultra-thin high-k oxides are widely used in todays advanced Complementary Metal-Oxide-Semiconductor technology to continue scalability and to increase performance due to a large dielectric constant (k>8) and low leakage current. Understanding conduction mechanisms (CMs) through these oxides is important to accurately make predictions ensuring the long-term operation of these devices. Nevertheless, this task presents several challenges due to several physical and electronic considerations like: 1) precise atomic control of the high-k material in the ultra-thin regime (thickness, stoichiometry, dielectric constant, etc), 2) excessively large gate leakage current levels, 3) appearance of several conduction mechanisms which degrade the performance and reliability of the devices, 4) interfacial defects at the high-k/silicon interface and 5) low thermodynamic stability of the high-k materials.

With the purpose to make accurate predictions of lifetime and/or reliability characteristics, this work reviews the conduction mechanisms of fabricated Metal-Insulator-Semiconductor (MIS) devices using ultra-thin Al2O3, HfO2, and TiO2, (less than 10 nm in

thickness for each dielectric) deposited by Atomic Layer Deposition (ALD). This deposition technique presents several advantages like: 1) high reproducibility and conformality, 2) outstanding control (to atomic level) on the thickness and stoichiometry, 3) good interface properties with the semiconductor substrate, and 4) low deposition temperature (T ≤ 250°C) for these metal oxides which enables enhanced performance and therefore, more accurate reliability predictions.

After fabrication, MIS devices were electrically characterized using standard Ig-Vg, C-V, and Ig-Vg-temperature measurement to determine the precise carrier conduction mechanism for each dielectric under different conditions of passivation (SiOx) and

post-metallization annealing. Physical and electronic parameters such as barrier height 𝚽B, energy trap level 𝚽Tand effective mass m* were extracted and further validated using semi-empirical models in MATLAB and SILVACO and compared with those found in literature, having excellent agreement. From this study a simple but practical correlation between materials’ properties with device performance could be obtained and compared among these high-k oxides.

On the other hand, resonant tunneling (RT) devices based on one or more insulator layers are attractive devices for nano electronics due to their nonlinear properties, which can be used in high speed applications. Nevertheless, there are still challenges that need to be solved in order for this technology to be a mainstream solution in these applications, like 1) achieving sufficient non-linearity, 2) high asymmetry and 3) low dynamic resistance to achieve high efficiency.

In this work, by taking advantage of the band offsets present in stacked high-k dielectrics metal-insulator-insulator-insulator-semiconductor (MIIIS) structures were fabricated in order to achieve quantization in an intermediate ultra-thin layer and therefore, RT and negative differential resistance (NDR). After fabrication, experimental proof of RT at room temperature was obtained via (NDR) for devices having Al2O3/HfO2/Al2O3

(2nm/1nm/2nm), and even when no NDR is present for devices having Al2O3/TiO2/Al2O3

iv

Resumen

Los dieléctricos ultra-delgados de alta constante son muy usados en la en la tecnología actual basada en el transistor de efecto de campo con el fin de continuar el escalamiento y mejorar el desempeño debido a que presentan una alta constante dieléctrica (k>8) y una baja corriente de fuga. Entender los mecanismos de conducción a través de estos óxidos es importante ya que podremos realizar predicciones precisas en cuanto al comportamiento a largo plazo de estos dispositivos. Sin embargo, esta tarea presenta varios retos debido a algunas consideraciones físicas y electrónicas como lo son 1) el control atómico preciso de estos óxidos en el régimen ultra-delgado (espesor, estequiometria, constante dieléctrica, etc.) 2) excesivas corrientes de fuga, 3) la aparición de diferentes mecanismos de conducción que degradan el dispositivo, 4) defectos en la interfaz entre el dieléctrico y el silicio y 5) baja estabilidad térmica.

Con el propósito de hacer predicciones precisas acerca del rendimiento y la confiabilidad de estos óxidos, en este trabajo hemos revisado y analizado los mecanismos de conducción de estructuras Metal-Aislante-Semiconductor (MIS) utilizando Al2O3, HfO2 y

TiO2 como oxido de compuerta en el régimen ultra-delgado (>10 nm de espesor)

depositados por Atomic Layer Deposition (ALD). Esta técnica de depósito presenta ventajas como lo son 1) alta reproducibilidad y depósito conformal, 2) excelente control en espesor y estequiometria, 3) excelentes propiedades en la interfaz oxido/semiconductor, y 4) baja temperatura de depósito (T ≤ 250°C), lo que permite un excelente desempeño y predicciones más precisas de confiabilidad.

Los dispositivos fabricados fueron caracterizados utilizando técnicas de medición estándar Ig-Vg, C-V e Ig-Vg-T para determinar los mecanismos de conducción asociados a cada uno de ellos bajo diferentes variaciones de proceso (pasivados y tratamiento térmico). De estas mediciones, parámetros físicos y electrónicos como lo son la altura de barrera𝚽B, el nivel energético de trampas 𝚽Ty la masa efectiva m* fueron obtenidos y validados usando simulaciones en MATLAB y SILVACO, para después comparar los valores obtenidos con literatura, donde hubo una gran concordancia. De este estudio, una relación entre propiedades de materiales y desempeño de dispositivos puede analizarse.

Por otro lado, los dispositivos que presentan tuneleo resonante (RT) utilizando una o más capas de aislante, son muy atractivos para la industria nano electrónica debido a sus propiedades altamente no-lineales. Sin embargo, para ser usados de forma convencional, existen algunos retos como lo son 1) lograr una alta no-linealidad, 2) una alta asimetría y 3) una baja resistencia dinámica.

En este trabajo, a partir de las caracterizaciones de óxidos de alta constante dieléctrica y aprovechando las características de cada uno de ellos con su interfaz con silicio, se propuso una estructura compuesta de 3 óxidos delgados, con el fin de lograr cuantización de estado energéticos en una capa intermedia y de ese modo, obtener RT a través de una resistencia diferencial negativa (NDR). A partir de mediciones Ig-Vg se pudo comprobar este fenómeno (NDR) en estructuras con Al2O3/HfO2/Al2O3 (2nm/1nm/2nm) y aun

cuando no fue posible encontrarlo para estructuras con Al2O3/TiO2/Al2O3 (2nm/1nm/2nm), las

características de rectificación de estos dispositivos son superiores a lo actualmente reportado.

v

List of acronyms

µ Mobility

A* Richardson constant AFM Atomic force microscopy Al Aluminum

ALD Atomic -layer deposition BT Ballistic transport CB Conduction band CM Conduction mechanism

CMOS Complementary Metal-Oxide-Semiconductor C-V Capacitance-Voltage

CVD Chemical vapor deposition Dit Density of interface states E Electric field

EDS Energy Dispersive X-Ray Spectroscopy EOT Equivalent oxide thickness

E-TAT Elastic trap-assisted tunneling Ɛ0 Vacuum permittivity

Ɛr Optical dielectric constant

FD-SOI Fully depleted Silicon on insulator FFT Fast Fourier transform

FN Fowler-Nordheim

FTIR Fourier-transform infrared spectroscopy GIDL Gate induced leakage current

h Planck's constant Ig-Vg Current-Voltage IL Interfacial layer

ITRS International Roadmap for Semicodnuctors J-E Current density-Electric field

k Dielectric constant KB Boltzman constant m* Effective mass

m0 Free electron mass

MBE Molecular beam epitaxy

MIIIS Metal-Insulator-Insulator-Insulator-Semiconductor MIIM Metal-Insulator-Insulator-Metal

MIM Metal-Insulator-Metal

MIS Metal-Insulator-Semiconductor

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n refractive index

Nc Density of sates in the conduction band NDR Negative differential resistance

ɸB Barrier height

PD-SOI Partially-depleted Silicon on insulator PF Poole-Frenkel

PL Photoluminiscence ɸT Energy trao level

PVD Physical Vapor Deposition QSCV Quasi-static Capacitance-Volatge QW Quantum well

RCA Radio Coorporation of America RT Resonant tunneling

RTD Resonant tunnelind diode SB-MOSFET Schottky barrier-MOSFET SCLC Space charge limited conduction SEM Scanning electron microscope Si Silicon

T Temperature

T(E) Transmission probability

TEM Transmission electron microscopy

tox Oxide thickness

VB Valence band

VDD Supply voltage

Vfb Flat band voltage

XPS X-ray photoelectron spectroscopy XRD X-ray diffraction

vii

INDEX

Acknowledgments ... ii

Abstract ... iii

Resumen ... iv

List of acronyms ... v

1 Introduction to advanced logic technology ... 1

1.1 Evolution of CMOS technology ... 1

1.2 Importance of high-k dielectrics and metal gates ... 4

1.3 Atomic-layer deposition of ultra-thin high-k oxides ... 6

1.4 Emergent applications of ultra-thin stacked oxides ... 9

1.5 State of the art ... 9

1.6 Motivation of this study ... 10

1.7 Objectives and organization of this study ... 11

References ... 12

2 Conduction mechanisms and ballistic transport in confined structures ... 15

2.1 Introduction ... 15

2.2 Gate-leakage current in deeply-scaled down MOSFET devices ... 15

2.3 Conduction mechanisms in Metal-Insulator-Semiconductor (MIS) devices ... 16

2.3.1 Schottky emission ... 16

2.3.2 Fowler-Nordheim tunneling ... 17

2.3.3 Direct tunneling ... 18

2.3.4 Poole-Frenkel emission ... 20

2.3.5 Hopping conduction ... 20

2.3.6 Ohmic conduction ... 21

2.3.7 Space-charge limited conduction ... 22

2.3.8 Elastic trap assisted tunneling (E-TAT) ... 23

2.3.9 Inelastic trap assisted tunneling ... 24

2.4 Ballistic transport ... 25

2.5 Resonant tunneling (RT) as a form of ballistic transport ... 27

2.5.1 Parameters defining ballistic transport ... 29

viii

2.6 Resonant tunneling (RT) devices ... 31

2.6.1 RT diodes ... 32

2.6.2 RT in double-barrier MIIM devices ... 32

References ... 34

3 Characterization of materials and devices ... 37

3.1 Introduction ... 37

3.2 Physical characterization of materials ... 37

3.2.1 Transmission electron microscopy ... 37

3.2.2 Scanning electron microscopy ... 39

3.2.3 Energy Dispersive X-Ray Spectroscopy ... 40

3.2.4 X-ray photoelectron spectroscopy ... 42

3.2.5 X-ray diffraction ... 43

3.2.6 Atomic force microscopy ... 44

3.2.7 Fourier-transform infrared spectroscopy ... 45

3.2.8 Photoluminescence ... 47

3.2.9 Profilometry ... 48

3.3 Electrical Characterization ... 48

3.3.1 Ig-Vg measurements ... 49

3.3.2 Ig-Vg-T measurements ... 50

3.3.3 C-V measurements ... 50

References ... 53

4 Fabrication of MIS/MIIIS devices ... 54

4.1 Introduction ... 54

4.2 Silicon cleaning and passivation ... 54

4.3 Atomic-layer deposition (ALD) of high-k oxides... 55

4.4 ALD of TiO2 using super cycles ... 56

4.5 Electron beam evaporation ... 57

4.6 Photolithography ... 58

4.7 Thermal treatment ... 59

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5 Charge transport properties in MIS and MIIIS devices ... 62

5.1 Introduction ... 62

5.2 Metal-Insulator-Semiconductor (MIS) devices... 62

5.2.1 Al2O3 MIS devices ... 63

5.2.1.1 Physical characterization ... 63

5.2.1.2 Current-Voltage (Ig-Vg) characteristics... 66

5.2.1.3 Current-Voltage-Temperature (Ig-Vg-T) characteristics ... 68

5.2.1.4 Capacitance-Voltage (C-V) characteristics ... 69

5.2.1.5 Parameter extraction and modelling ... 72

5.2.2 HfO2 MIS devices ... 75

5.2.2.1 Physical characterization ... 75

5.2.2.2 Electrical characterization ... 77

5.2.2.3 Parameter extraction and modelling ... 81

5.2.3 TiO2 MIS devices ... 82

5.2.3.1 Physical characterization ... 83

5.2.3.2 Electrical characterization ... 85

5.2.3.3 Parameter extraction and modelling ... 86

5.3 Metal-Insulator-Insulator-Insulator-Semiconductor (MIIIS) devices ... 91

5.3.1 Al2O3/HfO2/Al2O3 MIIIS devices ... 91

5.3.1.1 Physical characterization ... 92

5.3.1.2 Modeling of MIIS devices and electrical characteristics ... 93

5.3.2 Al2O3/TiO2/Al2O3 MIIIS devices ... 97

5.3.2.1 Physical characterization ... 97

5.3.2.2 Electrical characteristics ... 98

References ... 103

6 Tailoring the performance of MIS and MIIIS devices ... 106

6.1 Correlation between material’s properties and electronic performance in high-k MIS devices ... 106

6.2 Analysis of the Resonant tunneling properties in fabricated MIIIS devices ... 112

x

7.2 Conclusions ... 114

7.3 Recommendations for future work ... 115

Appendix A ... 116

List of figures ... 119

List of tables ... 128

1

1 Introduction to advanced logic technology

1.1 Evolution of CMOS technology

In 1947, the first bipolar transistor [1.1] was invented by W. Schockley, J. Bardeen and W.H. Brattain at Bell laboratories. After that invention, the semiconductor era erupted and in 1959, J. Kilby from Texas instruments proposed the first integrated circuit [1.2] (IC). 1960 marked the fabrication of the first Metal-Oxide-Semiconductor Field-Effect-Transistor [1.3] (MOSFET) by D. Kahng and M.M Attala, and since then, the MOSFET became the most important device in the semiconductor industry due to easy integration and scalability. In 1965, G. Moore proposed that the number of transistors that could be integrated in a square inch would be doubled every 18 months and this projection known as Moore’s Law has been valid to this day, nevertheless, this has come with challenges, which have been sorted by changing materials or the overall structure of the MOSFET, as seen in fig.1.1

Fig. 1.1 Evolution of MOSFET. a) Planar technology MOSFET. b) High-k/metal gate (HK/MG) MOSFET, c) Partially depleted Silicon on insulator (PD-SOI), d) Fully-depleted Silicon on insulator (FD-SOI), e) Schottky barrier MOSFET,

f) FinFET, g) 14 nm commercial FinFET, h) Ideal MOS transistor from ITRS [1.4].

The materials used in the fabrication of these devices (Silicon and Silicon oxide (SiO2))

have been a key factor that has allowed scalability of MOSFET technology over four decades, since SiO2 is an excellent insulator, with great thermal stability and presents a

high-quality interface with Si. Nevertheless, as devices reach nanometer scales, oxide thickness became so thin (tox<3.5nm) that a high gate leakage current (fig. 1.2) resulted in a continuous

waste of energy in the form of overheating and leakage currents that otherwise, could be used to perform logic operations.

2

Fig. 1.2 Gate current density as a function of gate voltage for MOS capacitors with different gate dielectric thickness

[1.5].

This reduction in the oxide thickness introduced new challenges for MOSFET fabrication, and in 2007, a new gate oxide material (HfO2) in the 45 nm fabrication node replaced this technology based on Poly-Si/SiO2, a metal gate also replaced the Poly-Si of the gate in order to obtain the best control in the channel region. This change in materials reduced the gate leakage current by maintaining equivalent oxide thickness (EOT) with respect to SiO2 of

about 1.2 nm and below. The increased gate-to-substrate capacitance resulted in better control of the inversion channel in the MOSFET. Since then, and in order to enhance the performance and reliability of devices, other planar devices have been used, like the Partially-depleted Silicon on insulator (PD-SOI), Fully-depleted Silicon on insulator (FD-SOI) and the Schottky barrier MOSFET. By year 2011, when planar technology was near its scaling limits, Intel presented their first 3D integrated circuit; which was a huge step towards new MOSFET technologies by migrating from a planar technology to high aspect ratio devices (3D devices) giving birth to the FinFET, a device that has enabled the continuous scaling trend and has kept Moore’s law valid. Nevertheless, one parameter of MOSFET devices that has remained almost the same is the supply voltage (VDD) (fig.1.3) meaning that

the continuous waste of energy in terms of leakage current and overheating of devices is still a big challenge in today’s microelectronics industry.

3

Fig 1.3 Predicted trends of gate oxide EOT and supply voltage, VDD, scaling for the technology node in the coming decade. Oxide electric fields are calculated based on the physical thickness of gate oxide and VDD as predicted by

ITRS [1.6]

The fabrication of the FinFET has allowed the scalability trends to continue, but as the fundamentals physical limits are reached, new technologies will be needed in order to continue this aggressive scaling, as seen in fig. 1.4. Technologies such as quantum well III-V devices, graphene nanowires could be the solution to this challenge.

4

1.2 Importance of high-k dielectrics and metal gates

SiO2 with a dielectric constant (k) of 3.9 has been used as the primary gate dielectric for

over 40 years due to 1) high-quality interface between SiO2/Si, 2) chemical and thermal

stability at high temperatures, 3) good quality of insulation, 4) the property of hard mask in different diffusion and doping processes, and 5) high breakdown fields (~13 MV/cm). Nevertheless, reducing the thickness of the SiO2 below 3.5 nm resulted in a high gate

leakage current, which is a big reliability issue for the transistor as the schematic in fig 1.5 shows, so the need for new materials that have an adequate equivalent oxide thickness (EOT) with respect to Si reducing the gate leakage current while incrementing the capacitance are needed.

Fig 1.5 a) Schematic of the gate leakage current for a Poly-Si/SiO2 based MOSFET devices compared to b) the gate leakage current for an EOT in high-k material. Capacitance is also increased

In order to continue the aggressive scaling of the MOS transistor, new materials are required with higher dielectric constants (k>10) and an adequate EOT in order to reduce the gate leakage current as seen in fig. 1.6. Several metallic oxides present EOT of ~1 nm while increasing the physical thickness, thus reducing the gate leakage current, making them excellent candidates for the replacement of SiO2 as gate dielectric.

5

Fig 1.6 Leakage current density vs. EOT for various high-κ oxides [1.8]

Nevertheless, even though there are many high-k materials available the selection is not that simple, as there are issues that need to be solved, like; 1) high-k, 2) bandgap width and offset, 3) thermodynamic stability on silicon, 4) film morphology and 5) process compatibility [1.8-1.14]. Ideally, the dielectric constant of the selected materials should be in the range of 20-40, nevertheless, there is trade-off between k and band-gap (fig.1.7), which could enhance the gate-to-substrate capacitance, but increased the gate leakage current, an undesired effect in advanced MOSFET’s.

Fig. 1.7 Dielectric constant vs. band gap for candidate gate oxides [1.8]

Also, the dielectric material must have a bandgap larger than 5 eV, with a band offset with silicon larger than 1 eV in order to avoid a high leakage current (fig. 1.8). Another

6

important parameter is the thermodynamic stability on silicon, as the interface between these would have a major impact in the overall electric characteristics of devices. High-k materials should also be able to withstand rapid thermal annealing (1000°C) without crystallizing. Finally, the deposition of these high-k oxides must be compatible with the overall Complementary Metal-Oxide-Semiconductor (CMOS) processing, and these dielectrics must have high reproducibility, and an excellent control on the thickness and stoichiometry.

Fig 1.8 Predicted barrier heights for a range of high-k oxides [8]

For the case of the metal gate, the materials must be highly conductive and have very high melting points in order to withstand the thermal budget used in CMOS processing. Also, the work function value of these materials will greatly influence the threshold voltage of fabricated devices. CMOS technology usually requires different metal gates for n-MOS and p-MOS devices. In addition, these metal gates should be thermally stable with the high-k dielectric [1.15-1.18].

1.3 Atomic-layer deposition of ultra-thin high-k oxides

As mentioned in the previous section, the deposition technique is of greatly importance in order to obtain the desired electrical characteristics of the fabricated devices. The main thin-film deposition methods are physical vapor deposition (PVD), chemical vapor deposition (CVD) and atomic-layer deposition (ALD). PVD physically deposits the material into the substrate, so there is not any form of chemical reaction and because of this, it could be deposited at higher ratios, but the control on thickness and uniformity is very poor. CVD utilizes chemical reactions to create solid materials. These materials are directly formed from chemical reactions in gas or liquid compositions. During this form of deposition, gases and liquids are a byproduct. This is what primarily sets CVD apart from PVD. Chemical vapor deposition is ideal when seeking good coverage over the substrate and has a good uniformity. For the case of atomic-layer deposition (ALD), it has been demonstrated that it presents high conformality, shows a high aspect ratio deposition, excellent control of thickness and stoichiometry, and an outstanding control in the coating of devices [1.19-1.21] as seen in fig. 1.9.

7

Fig. 1.9 Comparison between coating of different deposition methods

These deposition techniques present advantages and disadvantages according to the application needed, as seen in table 1.1.

Process Material

Substrate temperature

(oC)

Deposition

rate (Å s−1) Directionality Uniformity

Film density Grain size (nm) Impurity level Cost E-beam evaporation

Both metal and

dielectric 50–100 10–100 Yes Poor Poor 10–100 Low High

Sputtering Both metal and dielectric –200

Metal –200 Dielectrics 1–

10

Some degree Very good Good –20 Low High

PECVD Mainly

dielectrics 200–300 10–100 Some degree Good Good 10–100 Very low Very high

LPCVD Mainly

dielectrics 600–1200

Metal –100 Dielectrics 1–

10

Isotropic Very good Excellent 1–10 Very low Very high

ALD

(thermal)

Mainly

dielectrics 50–300 0.1–1

Isotropic step

conformal Superior Superior 1–10 Very low Very high

ALD

(plasma)

Mainly

dielectrics 20–200 0.1–1 Isotropic Superior Superior 1–10 Very low Very high

Table 1.1 Comparison between different deposition techniques. In red the PVD deposition techniques (less reliable method for deposition of ultra-thin film), in yellow the CVD deposition techniques (reliable method for deposition of ultra –thin films), and in green, the ALD deposition techniques (best and most reliable method for deposition of

ultra-thin films) [1.20]

Due to the superior characteristics ALD is the go-to deposition technique for ultra-thin high-k oxides. A schematic of the deposition process is shown in fig 1.10. First the precursor A enters the chamber, reacting with the surface, afterwards, a purge is needed to eliminate the byproducts, then precursor B enters the chamber, reacting with the surface, then a purge is needed to eliminate the byproducts, and the cycle is repeated until the desired thickness is obtained.

8

Fig. 1.10 Schematic of ALD process. (a) Substrate surface has natural functionalization or is treated to functionalize

the surface. (b) Precursor A is pulsed and reacts with surface (c) Excess precursor and reaction by-products are purged with inert carrier gas. (d) Precursor B is pulsed and reacts with surface. (e) Excess precursor and reaction

by-products are purged with inert carrier gas. (f) Steps 2–5 are repeated until the desired material thickness is achieved [1.19]

Finally, fig. 1.11 shows some TEM images from various devices in different fabrication processes using ALD to deposit the high-k material. As seen, the superior quality in the ALD deposition has allowed the scalability trends to continue.

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Fig. 1.11 Different multiple gate design structures where ALD gate oxides have been used. (a) A TEM cross-section of Intel’s FinFET transistor at the 22 nm node with the gate-oxide and gate wrapped around the fin. (b) Omega gate structure wrapping around a Ge channel (c) A pi-gate surrounding a poly-Si nanowire in a thin film transistor (d) A carbon nanotube FET with a gate all around structure, e) 10 nm FinFET presented by Intel at IEDM 2017 [1.19, 1.22]

1.4 Emergent applications of ultra-thin stacked oxides

By taking advantage of the ALD deposition technique, high-k oxides stacks are emerging for new applications, like passivation and enhancement of the performance of solar cells to achieve higher efficiencies and as coating materials [1.23-1.25]. They are also used in memory devices to increase the retention times of non-volatile memories, and in new emergent memories as seen in [1.26-1.28]. Another emergent application of these stacked oxides is MIIM resonant tunneling diode [1.29-1.32], where, by taking advantage of an enclosed triangular barrier, quantization of energy levels can occur resulting in resonant tunneling. Still, one of the most important applications of the stacked high k dielectrics is the high-mobility MOS transistors due to a high-quality interface with III-V and II-VI materials [1.33-1.34].

1.5 State of the art

The 10 nm FinFET is the most advanced logic technology device nowadays (fig.1.12), but the continuous waste of energy due to excessive gate leakage current and overheating of devices are still issues, which ultimately, results in low performance and low reliability. On the other hand, quantum well technologies based on heterostructures (fig. 1.12) (III-V and II-VI materials) deposited by molecular beam epitaxy (MBE), take advantage of a form of ballistic transport known as resonant tunneling (RT). This kind of coherent transport reduces

10

scattering and enhances the reliability of devices. However, due to the nature of the materials used in these devices, these kind of transport is only attainable for extremely complex devices and at low temperature (T<77°K). In summary, advanced logic technology presents an inherent problem of overheating due to gate leakage current, thus affecting reliability; meanwhile, heterostructures have this problem solved, but only for very complex structures at low temperature. In this work, we propose a structure that could take advantage of each characteristics, scaling and ballistic transport for its use in advanced logic technology, as explained in the next section.

Fig. 1.12 a)TEM image of 10 nm node FinFET presented by intel at IEDM 2017 [22], b) Quantum Well in heterostructures [1.35]

1.6 Motivation of this study

As the dimensions of advanced electron devices reach nanometer scales, unavoidable effects reduce the reliability and performance of these devices commonly found in CMOS technology. For the particular case of MOSFET, an increase in the gate leakage current would translate in a continuous waste of energy and the low, unstable and noisy control of the inversion channel.

For the case of CMOS technology, aggressive scaling has resulted in the use of ultra-thin (tox<10nm) high-k oxides as gate dielectrics in the most advanced logic technologies, and a

compromise between performance and reliability is to be made.

This is why is important to accurately define and understand the conduction mechanism in this high-k based devices MIS devices, in order to accurately predict their behavior and have better reliability and performance models that account for various process variations, like temperature annealing or passivation.

Also, as the dimensions continue to scale down, devices could reach the ballistic transport regime in the gate leakage current. In this matter, and taking advantage of the stacking of these high-k oxides, and their band-offset with silicon, a structure having a quantum well could result in resonant tunneling, where electrons are trapped inside and are transported without scattering when energy levels are aligned. This type of transport could be exploited in order to ensure better reliability of devices due to no scattering and no creation of traps in the bandgap of the oxides, thus ensuring its long-term operation.

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1.7 Objectives and organization of this study

The objectives of this study are:

 To fabricate and characterize MIS devices using the ALD high-k process and variations.

 To understand conduction mechanism in high-k oxides like Al2O3, HfO2 and TiO2,

for various fabrications variations in order to accurately extract the physical parameters associated to each material and device.

 To model and make a correlation between materials properties and Current-Voltage (Ig-Vg) characteristics.

 From the previous study, select the best materials in order to design and fabricate devices having stacked oxides forming quantum wells in order to promote RT at room temperature.

This thesis consists of 7 chapters which are described below. Following this chapter, Chapter 2 describes the conduction mechanism usually found in Metal-Insulator-Semiconductor (MIS) devices, which is of great importance when making accurate predictions for performance and reliability. Also, ballistic transport is discussed as the means to obtain better reliability during larger periods of time.

Chapter 3 introduces and discusses the main characterization methods used. Materials’ characterization is very important to understand the film thickness, stoichiometry and roughness, as the interfaces between deposited materials and silicon substrate. Also, electrical characterization methods are mentioned, taking special consideration in those that provide information about the materials properties of the fabricated devices.

Chapter 4 discusses in great detail the fabrication process of MIS and MIIIS devices. Variations in the process are also taken into account in order to understand the effect they have in the final fabricated devices. Deposition rate of metal gate, passivation of silicon substrate, ALD variations and temperature annealing are all taken into account.

In chapter 5, measurements of the fabricated devices are presented, along with the extraction of the physical parameters obtained for each fabricated device. Modelling of current conduction mechanisms is also obtained and a correlation with process variations is made. RT in MIIIS devices is presented as a form to enhance the reliability of CMOS based structures.

Chapter 6 presents a correlation between materials properties and performance of devices. Also a comparison, between the devices fabricated with the different oxides, is introduced as a way of tailoring the RT effect, and help in designing and predicting an optimized negative resistance effect.

Finally, chapter 7 summarizes and concludes the contributions of this study and suggests recommendations for future work.

12

References

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Non-Bulk CMOS,” vol. 0, no. C, pp. 0–3, 2002.

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[1.21] L. Niinistö, J. Päiväsaari, J. Niinistö, M. Putkonen, and M. Nieminen, “Advanced electronic and optoelectronic materials by atomic layer deposition: An overview with special emphasis on recent progress in processing of high-k dielectrics and other oxide materials,” Phys. Status Solidi Appl. Res., vol. 201, no. 7, pp. 1443–1452, 2004.

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3204–3211, 2014.

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2 Conduction mechanisms and ballistic transport in

confined structures

2.1 Introduction

This chapter is devoted to the understanding of conduction mechanisms in Metal-Insulator-Semiconductor (MIS) devices to accurately predict the gate leakage current through ultra-thin gate oxides in state-of-the-art Complementary Metal-Oxide-Semiconductor (CMOS) technology. This is because when an electric field (E) with a moderate intensity (E > 1 MV/cm) is sustained across a thin dielectric film, relatively large gate tunneling currents could degrade the behavior of the device (usually a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) or Metal-Insulator-Semiconductor (MIS)), thus compromising the performance of these devices and shortening their lifetime.

Also, ballistic transport is studied as a form to enhance the reliability of these devices. Ballistic transport is defined as the transport of electrons in a medium having negligible

resistivity caused by scattering. One way to obtain ballistic transport is trough resonant tunneling (RT), which result in a negative differential resistance (NDR) effect in the current-voltage (I-V) characteristics of devices.

2.2 Gate-leakage current in deeply-scaled down MOSFET devices

As the devices reach nanometer dimensions, one of the main issues that arise is the increase of the gate leakage current, which is a direct result of the decrease in the gate oxide thickness due to the scalability of devices as stated by Dennard et al. [2.1]. The decrease in the gate oxide thickness has reached the regime of quantum mechanical tunneling, which directly affects the performance of the devices. One of the consequences of a high leakage current is the gate induced leakage current (GIDL); this phenomenon affects the off-state of a nanometer transistor, as seen in fig. 2.1. [2.2], reducing its performance and increasing the energy consumed by these devices. Another effect of the reduced dimensions in the oxide thickness is a high gate leakage current, which has derived in the necessity of new materials for the gate oxide. High-k oxides are the materials of choice, nevertheless, due to its intrinsic characteristics; new models for current conduction are needed, as explained in the following section.

16

Fig. 2.1 GIDL effect in a MOSFET having ultra-thin oxide thickness (<3 nm) [2.2], b) limit of scaling for different gate

oxides [2.3].

2.3 Conduction mechanisms in Metal-Insulator-Semiconductor (MIS)

devices

Understanding the conduction mechanisms in dielectric films is important in the accurate predictions of performance and reliability of MOSFET devices. There exist two types of conduction mechanisms in dielectric films, the electrode-limited conduction and the bulk limited conduction mechanism [2.4-2.8]. For the case of the electrode-limited conduction, physical properties of the barrier height at the electrode-dielectric interface and the effective mass of conduction carriers in dielectric films can be extracted. The bulk-limited conduction mechanisms depend on the electrical properties of the dielectric itself. From these mechanisms, important physical parameters like energy trap level, trap spacing, trap density, etc., could be obtained. It is important to accurately distinguish one conduction mechanism from another, since there could be a contribution of two or more at the same time, and since several conduction mechanisms depend on temperature in different ways, measuring the temperature dependent conduction currents is of essence to identify them correctly.

2.3.1 Schottky emission

Schottky emission is a conduction mechanism that occurs if the electrons can gain enough energy provided by thermal activation, as shown in the schematics in fig 2.2. The electrons in the semiconductor may overcome the energy barrier (𝑞𝛷_𝐵) to get into the dielectric. The energy barrier height at the semiconductor-dielectric interface may be lowered by the image force, which is called the Schottky effect. This conduction mechanism is one of the most often-observed in dielectric films, especially at relatively high temperatures. The expression for Schottky emission is [2.9-2.11]:

17

𝐽 = 𝐴

∗

𝑇

2

exp [

−𝑞(𝛷𝐵−√𝑞𝐸/4𝜋𝜀𝑟𝜀0)

𝐾𝐵𝑇

] , 𝐴

∗

₌

4𝜋𝑞𝐾𝐵2𝑚∗

ℎ3

=

120𝑚∗

𝑚0

(1)

Where J is the current density, A* is the effective Richardson constant, m0 is the free

electron mass, m* is the effective electron mass in the dielectric, T is the absolute temperature in Kelvin, q is electronic charge, 𝑞𝛷_𝐵 (ΦB) is the Schottky barrier height, E is the

electric field across the dielectric, KB is the Boltzmann’s constant, h is the Planck’s constant,

𝜀

0 is the permittivity in vacuum, and 𝜀𝑟

is the optical dielectric constant. The optical dielectric

constant should be close to the square of the refractive index (n).

Fig. 2.2 Schematic energy band diagram of Schottky emission

2.3.2 Fowler-Nordheim tunneling

In quantum mechanics, the electron wave function may penetrate through a potential barrier when the barrier is thin enough (<4 nm), hence the probability of electrons existing at the other side of the potential barrier is not zero due to the tunneling effect. Fowler-Nordheim (FN) tunneling occurs when the applied electric field across the dielectric is large enough so the electron wave function may penetrate through a triangular potential barrier into the conduction band of the dielectric as seen in the schematic in fig. 2.3. The expression for the FN tunneling current is [2.12-2.14]

𝐽 =

𝑞3𝐸2

8𝜋ℎ𝑞𝛷𝐵

exp[−

8𝜋√2𝑚∗ _(𝑞𝛷 𝐵)3/2

3𝑞ℎ𝐸

]

(2)

where 𝑞𝛷𝐵 (ΦB) is the effective barrier height between semiconductor and dielectric and

18

Fig. 2.3 Schematic energy band diagram of Fowler-Nordheim tunneling

2.3.3 Direct tunneling

When the gate oxide thickness is 4 nm or less, electrons from the conduction band in the semiconductor are able to tunnel across the oxide directly by quantum-mechanical tunneling, (without changing energy) into the conduction band of the metal gate (substrate injection). Here, the intensity of tunneling current through the gate oxide will strongly depend on the oxide thickness (tox), effective mass for tunneling carriers (m*), and barrier height (𝛷𝐵), as stated in the expression [2.15-2.17]:

𝐽 = exp [−

8𝜋√2𝑞

3ℎ

(𝑚

∗

_𝛷

𝐵

)

1

2

𝜀 𝑘𝑡

_{𝑜𝑥,𝑒𝑞}

]

₍₃₎

where 𝛷𝐵 is the barrier height, 𝑡𝑜𝑥,𝑒𝑞 is the equivalent oxide thickness and 𝜀 is the permittivity of the high-k oxide. All the other parameters are defined as before. Quite importantly, we notice the lack of any temperature dependence in this equation. In fig. 2.4, a schematic of the energy band diagram for this mechanism is shown.

19

Fig. 2.4 Schematic energy band diagram of direct tunneling

The scaling limits of alternative gate dielectrics based on their direct tunneling characteristics and gate leakage requirements for future CMOS technology are shown in fig 2.5. The tunneling leakage current for a given Equivalent Oxide Thickness (EOT) (𝑡𝑜𝑥,𝑒𝑞) is dependent not only on the k-value of a gate dielectric but also tunneling barrier height (𝛷𝐵) and tunneling effective mass (m*). They introduced a figure of merit to compare the relative advantages of gate dielectric candidates. The figure of merit is given by 𝑓 = (𝑚∗_𝛷

𝐵)1/2𝐤. Fig. 2.5 indicates the scaling limit for several gate dielectrics when VG is specified to be 1.0 V and

the maximum tolerable gate current density JG is 1 A/cm2. A dielectric with a larger figure of

merit possesses a lower scaling limit EOT.

20

2.3.4 Poole-Frenkel emission

Poole-Frenkel (PF) emission involves a mechanism similar to Schottky emission, due to electrons being excited from traps within the band-gap to the conduction band of the dielectric. This conduction mechanism considers an electron in a trapping center, the Coulomb potential energy of the electron can be reduced by an applied electric field across the dielectric film. The reduction in potential energy may increase the probability of an electron being thermally excited out of the trap into the conduction band of the dielectric. The schematic energy band diagram of PF emission is shown in Fig. 2.6. The general expression for PF emission is [2.18-2.20]

𝐽 = 𝑞𝜇𝑁

𝐶

𝐸 exp[−

𝑞(𝛷𝑇−√𝑞𝐸/(𝜋𝜀𝑖𝜀𝑜)

𝐾_𝐵𝑇

]

(4)

where, 𝜇 is the electronic drift mobility, 𝑁𝐶 is the density of states in the conduction band of the dielectric 𝑞𝛷𝑇 (ΦT) is the energy trap level found in the energy gap of the oxide (taken

from the minimum of its conduction band), 𝜀𝑖 is the optical dielectric constant and 𝜀𝑜 is the vacuum permittivity and the other variables are defined as before. For this conduction model, we notice a strong dependence with temperature.

Fig. 2.6 Schematic of the energy band diagram of Poole-Frenkel emission

2.3.5 Hopping conduction

Hopping conduction is due to the tunneling effect of trapped electrons “hopping” from one trap site to another in dielectric films. Fig. 2.7 shows the schematic energy band diagram of hopping conduction. The expression of hopping conduction is [2.21-2.23]

𝐽 = 𝑞𝑎𝑛𝑣 exp (

𝑞𝑎𝐸−𝐸𝑎

21

where a is the mean hopping distance (the mean spacing between trap sites), n is the electron concentration in the conduction band of the dielectric, v is the frequency of thermal vibration of electrons at trap sites, and Ea is the activation energy (energy level from the trap

states to the bottom of conduction band); the other terms are defined before.

Fig. 2.7 Schematic energy band diagram of hopping conduction

2.3.6 Ohmic conduction

This conduction mechanism considers the movement of both carriers, mobile electrons in the conduction band and mobile holes in the valence band during tunneling. In this conduction mechanism, a linear relationship exists between the current and the electric field as seen in fig. 2.8a. This follows the Ohm Law, which is often observed in many semiconductor devices. Although the energy gap of some dielectrics is relatively large, a small number of carriers that may be generated due to thermal excitation could be present [2.24-2.25]. The expression for Ohmic conduction (considering only electrons in the conduction band) is

𝐽 = 𝑛𝑞𝜇𝐸 exp [− 𝐸𝑔

2𝐾_𝐵𝑇] (6)

where 𝑛 is the number of electrons in the conduction band and the other variables are defined as before. Equation (6) needs to be modified if holes in the valence band are to be accounted (holes in the valence band (p) instead of n, and the mobility). The magnitude of the current is very small because is often found at relatively small electric fields. This current mechanism is observed if there is no significant contribution from other conduction mechanisms. A schematic of this conduction mechanism is presented in fig. 8b.

22

Fig. 2.8 a) Ohmic conduction in a device having Al/ZrO2/p-Si, the slope in this regime is almost 1, b) schematic

energy band diagram of Ohmic conduction

2.3.7 Space-charge limited conduction

Space-charge limited conduction is a conduction mechanism governed by 3 zones. A typical characteristic plotted in a log-log curve for space-charge-limited current is shown in fig. 2.9. The J-V characteristic in the log J-log V plane are bound by three limited curves, namely, ohm’s law (JOhm∝ V), traps-filled limit (TFL) current ( JTFL∝ V), and Child’s law (JChild ∝ V2_{). The equations that govern this conduction mechanism are [2.26-2.27]}

𝐽𝑂ℎ𝑚= 𝑞𝑛0𝜇 𝑉

𝑑 (7)

𝐽𝑇𝐹𝐿= 9 8𝜇𝜀𝜃

𝑉2

𝑑3 (8)

𝐽𝐶ℎ𝑖𝑙𝑑= 9 8𝜇𝜀

𝑉2

𝑑3 (9)

where 𝑛0 is the concentration of the free charge carriers in thermal equilibrium, 𝜃 is the ratio of the free carrier density to total carrier (free and trapped) density, V is the applied voltage, d is the thickness of the film and 𝜀 is the dielectric constant, all the other terms are defined above.

23

Fig. 2.9 Typical current density-voltage (J-V) characteristic of space-charge-limited conduction current, 𝑽𝒕𝒓 is the transition voltage and 𝑽𝑻𝑭𝑳 is the trap-filled limit voltage [2.5]

2.3.8 Elastic trap assisted tunneling (E-TAT)

The trap assisted tunneling is a conduction mechanism mostly related to the generation of traps in the bandgap of the dielectric due to the presence of high electric fields. It is often related to stress induced leakage current (SILC). The tunneling probability of carriers is, to first order, exponentially dependent on the energy barrier that they have to pass through. The presence of traps inside the gate oxide splits the energy barrier in two parts, thus allowing the consecutive tunnel through thinner energy barriers and increasing exponentially the probability of the total tunneling process. The gate current increase is especially remarkable in the direct tunneling (DT) regime, when the tunneling mechanism is strongly dependent on the oxide thickness and the oxide traps can divide in symmetric parts the energy barrier, thus producing the most favorable condition for the TAT process and largely increasing the tunneling current. Therefore the stress-induced distortion of the tunneling characteristic is more enhanced in the DT regime, hence at low gate voltages [2.28-2.30].

In heavily stressed devices, the number of oxide trap can be considerably high, and the TAT process can involve more than one trap. The generation of oxide defects close yields the interaction of the traps in the SILC mechanism. In particular, in relatively thick oxides, the presence of only one trap in the oxide can be insufficient to produce considerably large gate current increases, but the generation of paths due to the presence of several traps can produce very large SILC values and eventually breakdown. Two main types of this mechanism are identified; the elastic trap assisted tunneling (TAT) and the inelastic TAT.

For the case of the elastic TAT, when the electron is trapped, and then tunnel through the barrier, no kinetic energy is lost, thus the momentum of the particle is conserved, the schematic of this conduction mechanism is shown in fig 2.10. A model for the elastic TAT is proposed by Jiménez-Molinos et al [2.31] and is given by:

24

𝐽𝑇= 𝑞 ∫ 𝑑𝑧 𝑡𝑜𝑥

0 ∫

𝑁𝑇(𝑧,𝐸) 𝜏_𝑐(𝑧,𝐸)+𝜏_𝑒(𝑧,𝐸)𝑑𝐸

𝐸0 (10)

where q is the electron charge, NT is the concentration of traps with energy at position z,

and c and e are the time constants for capture and emission processes.

Fig. 2.10 Schematic model for elastic TAT process, no energy is lost in this kind of tunneling.

2.3.9 Inelastic trap assisted tunneling

For the case of the inelastic TAT, the electron gets trapped in a trapping center and then relaxes (losing energy) to another trap site as seen in the schematic in fig. 2.11. Contrary to elastic TAT, in this model, the energy loss is not a fixed parameter, and has to be taken into account in order to correctly predict this phenomenon. The equation for inelastic TAT is given by [2.32]

𝐽𝑇= 𝑞 ∫

𝑁𝑇(𝑧) 𝜏_𝑐(𝑧)+𝜏_𝑒(𝑧)𝑑𝑧 𝑡𝑜𝑥

0 (11)

Where



c and



e are the time constants for capture and emission processes and the other

25

Fig. 2.11 Schematic model for inelastic TAT process, the electron energy is not conserved

2.4 Ballistic transport

Transport in nanoelectronic systems could be classified by relating the size of the sample to length scales, which determine how the carriers propagate through the sample. For this, the mean free path is studied in order to understand the ballistic transport regime.

The mean free path () is a measure of the distance between subsequent scattering events. Such events occur due to the fact that the sample is not ideal but rather contains irregularities in the lattice. Scattering can be considered as elastic when the electron energy is conserved. In addition electron scattering can also be connected to an energy transfer which means that the scattering processes are considered to be inelastic; and the carrier either gains or losses energy depending on whether excites the lattice or is excited by it [2.33-2.35].

By comparing  with the dimension of a sample (L) different transport regimes can be classified. For the case where L>>, many scattering events occur while the electrons propagate through the structure, this is called diffusive transport and is illustrated in fig 2.12a. When L~ some electrons encounter scattering events, but some of them are transmitted without them, thus this type of transport is called quasi-ballistic (fig. 2.12b). Finally, when L< the electrons can transverse the system without any scattering; this regime is called ballistic, as seen in fig. 2.12c. Therefore, ballistic transport (BT) occurs when the transmission probability (T(E)) of an electron equals 1.

26

Fig. 2.12 a) Diffusive transport, b) Quasi-ballistic transport, c) Ballistic transport [2.33]

In ultra-scaled MOSFET devices, the channel of the transistor has reached the nanometer scale, thus enabling ballistic transport along the channel, this is an important development, since no scattering events would occur, and therefore, the performance of the devices would be enhanced. Fig 2.13 shows the distribution of scattering events for MOSFET transistor in the ballistic and diffusive regimes [2.36].

Fig. 2.13 Difference between ballistic and scattered transport in the channel of a MOSFET. As seen, in the BT regime, no scattering events occur along the channel [2.36].

27

The drain current vs drain voltage (Id-Vd) characteristics of such transistor are shown in fig. 2.14, as seen, an enhancement of the response in the Id current is very notorious. Also, for this model, the Id presents a saturation which is a direct result of the ballistic regime. This ballistic transport usually is studied along the channel (horizontal transport), in order to achieve high microprocessor processing speeds and to increase the overall performance of devices. Nevertheless, in the gate-to-substrate region (vertical transport) this type of BT regime could be reached, diminishing the scattering events and increasing the reliability of these devices, and this is the main study of this work.

Fig. 2.14 Comparison between experimental data for a 70 nm channel length MOSFET and the ideal ballistic MOSFET [2.33]

2.5 Resonant tunneling (RT) as a form of ballistic transport

To understand how resonant tunneling could be a form of ballistic transport (BT), the concept of tunneling becomes important. Tunneling is a quantum mechanical phenomenon when a particle is able to penetrate through a potential energy barrier that is higher in energy than the particle’s kinetic energy as seen in fig 2.15. Consider a ball trying to pass through a wall. If the ball has enough energy (E) to overcome the potential energy (V) at the top of the barrier then it can get through. This is the classical picture and is controlled by the simple Law of Conservation of Energy. However, if the ball does not have enough kinetic energy, to overcome the barrier it will not get through. In contrast, when quantum effects are taken into effect, the ball can "tunnel" through the barrier to the other valley, even if its kinetic energy is less than the potential energy of the barrier to the top of one of the hills (in addition, you need available carriers in one side and available states on “the other side”). The reason for the difference between classical and quantum motion comes from wave-particle nature of matter. One interpretation of this duality involves the Heisenberg uncertainty principle, which defines a limit on how precisely the position and the momentum of a particle can be known at the same time. Hence, the probability of a given particle's existence on the opposite side of an

28

intervening barrier is non-zero, and such particles could “tunnel” with a relative frequency proportional to this probability.

Fig. 2.15 Classical approach and quantum mechanical tunneling.

By taking advantage of this transport property, devices have been fabricated such as the tunnel diode, which is a thin insulator between two semiconductors. These structures form a significant basis for the construction of many nanoelectronic devices because the electron transport takes place without any loss of energy (without scattering). One important parameter which relates the ballistic transport regime in these devices is the transmission probability (T(E)), which indicates when the electron is able to “tunnel” without any scattering, thus giving an insight of this conduction regime as seen in fig. 2.16.

Fig. 2.16 Electron transmission probability and current against electron energy for 3 nm and 6 nm barriers [2.37]

A variant of the tunnel diode is the resonant tunneling diode (RTD) and it is one of the most important quantum effect devices nowadays. In this device, the band gap alignment consists of two doped layers (bottom and top contact layers), two barriers, and one quantum

29

well with at least one bound energy state. When an electric field is applied to electrons, they tunnel from the bottom contact through the barriers, then the bound states resonates with the Fermi energy level of the bottom layer. The term resonant means alignment and transmission due of energy levels between bottom and top contact layers, as seen in fig. 2.17 [2.37-2.39].

Fig. 2.17 Resonant tunneling in a double barrier quantum well structure

2.5.1 Parameters defining ballistic transport

In nanoscale devices where the length becomes comparable to or less than the  of carriers, we enter the quasi-ballistic or pure ballistic regime of transport. Landauer emphasized the role of contacts in determining the current through such a conductor. The maximum conductance, in this case, is limited by the contacts and is given by Gc = 2q2 /h per mode, where q is elementary charge and h is Planck’s constant. Thus, the resistance is finite even though there is no scattering in the conductor. This is known as the quantum conductance and is one of the main parameters in determining the ballistic transport in devices, as seen in fig. 2.18.

30

Fig. 2.18 The conductance through a quantum point contact is quantized and only increases in units of 2q2_{/h as the}

width of the contact is increased. This effect is more notorious at low temperatures [2.40]

Like the quantum of conductance, other parameters could help us identify ballistic transport, especially in RT devices. The transmission probability T(E) is very important, since it represents the probability of “finding” an electron on the other side of the potential barrier, and as we approach to 1, ballistic transport becomes the main regime. Other parameters like 1) Asymmetry, defined as the ratio of the current at positive bias to that at negative bias at certain voltage J+_/J-_{, 2) dynamic resistance, defined as dV⁄dI and 3) non-linearity, defined as}

the ratio of the static to dynamic resistance (V/I) ⁄ (dV/dI) could help us identify the ballistic transport regime in RT devices, as seen in fig 2.19.

Fig. 2.19 Rectifying characteristics of the MIIM devices showing the: a) J-V characteristics, b) asymmetry, c) non-linearity [2.41]

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2.5.2 Negative differential resistance

Negative differential resistance (NDR) is a phenomenon where an increase in the applied voltage decreases the current, thus giving the impression of a negative resistance and it is often associated to resonant tunneling. Usually consists of three steps which are explained below.

Step 1: At zero bias, no current is observed; nevertheless, there exists a quantization of energy levels in the quantum well (fig. 2.20a). .

Step 2: As the forward bias increases, an alignment between the discrete energy levels and the conduction band of the emitter results in a large increase in the current (fig 2.20b).

Step 3: As more forward bias is applied, a misalignment between the discrete energy levels occurs, thus dropping the tunnel current. This is known as NDR (fig. 2.20c).

Fig. 2.20 a) No forward bias, b) when the applied potential is enough, the energy levels align, causing an increase in the tunnel current. c) Misalignment of the energy levels, which causes a decrease in the current, d) current-voltage

characteristics of a RT devices having a NDR zone.

2.6 Resonant tunneling (RT) devices

Resonant tunneling devices take advantage of the discretization of energy levels confined in a quantum well, as defined before. Some of them present characteristics such as NDR zones, but for other devices, even when no NDR is present, RT is a strong possibility due to some specific I-V characteristics (like high asymmetry and non-linearity).

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2.6.1 RT diodes

Resonant tunneling diodes based on heterostructures (III-V and II-VI materials) are one of the most important devices in optoelectronics nowadays due to their high cut-off frequency and the ability to generate numerous quantum wells in order to enhance the performance of these devices (fig 2.21). Nevertheless, RT is often observed in highly complex structures and at extremely low temperatures (T<77°K). Additionally, as most of these materials are deposited by molecular beam epitaxy (MBE), they could not be integrated in a CMOS process.

Fig. 2.21 a) A cross section schematic of a fabricated device showing the layer structure; (b) SEM image (c) conduction band potential profile for a symmetric structure at zero bias, where QW (W1) is the same width as QW

(W2).; (d) the symmetric structure under bias.(e) an asymmetric structure at zero bias, the calculated electron probability density shows the n = 1 states are misaligned and localized to a specific QW (f) an asymmetric structure

under bias, the electron probability density shows alignment of the n = 1 QW states [2.42]

2.6.2 RT in double-barrier MIIM devices

Metal–insulator–metal (MIM) devices using double insulator layers are being used as resonant tunneling devices, due to their scalability and CMOS compatibility [2.41]. The objective is to have superior diode characteristics such as large responsivity, asymmetry and nonlinearity. Devices with two insulator layers, metal–insulator–insulator–metal (MIIM) could result in RT of electrons through a quantum well formed between the two insulators as seen in fig. 2.22. This occurs when the metal Fermi level on the higher barrier side is biased positive creating a right-triangular well at the interface of the two insulators. When an allowed energy level in the quantum well aligns with the metal Fermi level on the negative side, it causes an increase in the current. Nevertheless, these devices show no sign of NDR zones,