A high dynamic range-CMRR and tunable bandwidth front-end amplifier for biomedical applications

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Tunable Bandwidth Front-End

Amplifier for Biomedical Applications

By

Liliana Haiko Salas Barradas

A Dissertation submitted in partial fulfillment of the requirements for the degree of:

MASTER ON SCIENCE WITH MAJOR ON ELECTRONICS

at the

Instituto Nacional de Astrof´ısica, ´Optica y Electr´onica April 9

Tonantzintla, Puebla

Under the supervision of:

Dr. Alejandro D´ıaz S´anchez

Dr. Carlos Mu˜niz Montero

c

INAOE 2015

The author grants to INAOE the permission to reproduce and distribute parts or complete copies of this thesis

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.

“There is a driving force more powerful than steam, electricity and atomic energy, the will.”

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First of all, I would like to thank to Consejo Nacional de Ciencia y Tecnolog´ıa (CONA-CyT) and Programa para el Mejoramiento del Profesorado (PROMEP) by the support of this work throughout projects 181201 and PROMEP-UPPue-PTC-047

I acknowledge the support given by Instituto Nacional de Astrof´ısica ´Optica y Electr´onica and all my professors at INAOE during this academic training process.

My special gratitude to my advisors Dr. Alejandro D´ıaz S´anchez and Dr. Carlos Mu˜niz Montero, for their extraordinary support and guidance throughout the develop-ment of this work.

I am grateful to my parents for giving me all than they are and make me the per-son who I am, and to my grandparents for their unconditional love all the time.

I would like to thank all my family and all the persons who love me, specially my aunt and uncle Ofe and Arturo for giving me support in every stage of my life.

Thanks to my angel Harumi and my cousins Sugei, Michelle, Arturo Valeria and Pepito.

Furthermore, I express my gratitude to my Sensei Jaime Ortega for teaching me to give my best in everything I do in my life with his extraordinary example.

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iii

And thanks to you, my love H´ector Christian for loving me, believing in me and sup-porting me in every project of my life.

Finally but not less important, even though they can not read, thanks to my babies Madara and Canton to come into my life.

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RESUMEN

T´ITULO:

AmplificadorFront-End de Alto Rango Din´amico, Alto CMRR y Ancho de Banda Sin-tonizable para Aplicaciones Biom´edicas

AUTOR:1 _{Liliana Haiko Salas Barradas}

PALABRAS CLAVE: Amplificador Front-End, Se˜nales de Biopotenciales, Filtro Notch , Preamplificador.

DESCRIPCI ÓN: Los desaf´ıos en el diseño de sistemas de monitoreo no invasivos de biopotenciales, tales como: bajo consumo de potencia, bajo voltaje de alimentación, bajo costo y portabilidad, han impulsado a los ingenieros eléctricos a mejorar el de-sempeño de dichos sistemas, mas allá de especificaciones usuales para desarrollar apli-caciones para el cuidado de la salud.

En este trabajo se presenta una propuesta de preamplificador basado en la topolog´ıa folded cascodecombinado condc-feedback como técnica de compensación de offset y una técnicafeed-forward combinada con transistoresQuasi Floating Gates con reutilización de hardware, para mejoramiento de CMRR. Aunado a esto se presentan bloques de filtrado pasa banda y notch sintonizables para lograr sintonización en us frecuencias de corte de acuerdo a la aplicación médica requerida (EEG, ECG y EMG). Con el fin de utilizar este sistema como electrodo activo se busca obtener minimización de área en layout, bajo consumo de potencia y bajo costo en tecnolog´ıa de 0.5µm.

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v

SUMMARY

TITLE:

A High Dynamic Range-CMRR and Tunnable Bandwidth Front-End Amplifier for Biomedical Applications

AUTHOR:2 _{Liliana Haiko Salas Barradas}

KEY WORDS:Front-End Amplifier, Biopotential Signals, Notch Filter, Preamplifier.

DESCRIPTION:The challenges in non invasive monitoring systems design for biopo-tentials acquisition, such as: low power consumption, low supply voltages, low cost and portability, have encourage electrical engineers to enhance the performance of such sys-tems, beyond common specifications in order to develop medical care applications.

This work propose a pre-amplifier based on the combination of a folded cascode topol-ogy, an offset compensation technique based on dc-feedback and a CMRR enhancement technique based on feed-forward combined with Quasi Floating Gates transistors and hardware reuse. Additionally, two filter stages, tunable band pass and tunable notch configurations to achieve tunability in cutoff frequencies according with the required medical application (EEG,ECG and EMG).

In order to implement this system as an active electrode, the layout area minimiza-tion, low power consumption and low cost have been pursued in a CMOS technology of 0.05µm

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List of Figures

1.1 Amplifiers with offset: (a)differential input voltage equal to input

off-set voltage forces output to zero, (b) output offoff-set of an amplifier with

shorted inputs. . . 5

1.2 Offset Compensation scheme . . . 7

1.3 Block Diagram for an EEG acquisition system . . . 17

2.1 Thermal noise of a resistor . . . 24

2.2 Thermal noise of a MOS transistor . . . 24

2.3 Flicker noise of a CMOS Transistor . . . 26

2.4 Noise Power Spectrum of Standard CMOS Operational Amplifier . . . 27

2.5 Quasi Floating Gate MOS Equivalent Circuit . . . 32

2.6 Basic Structures of Floating QIRs (a) A Cross section view of a PMOS transistor and its associated PN junctions. (b) QIR Electrical model of Figure 2.6(a). (c)Electrical Model of a Low swing QIR. (d) Electrical Model of a moderate swing QIR. (e)Electrical Model of a Large-Swing QIR. . . 33

2.7 Circuit Implementation of Tunable R2 . . . 35

2.8 Circuit Implementation of Tunable Rg . . . 36

2.9 Folded Cascode Op Amp Topology . . . 37

2.10 Twin Tee Topology with amplifier . . . 41

2.11 Resistive Feedback Technique Topologies . . . 45

2.12 Topology presented in [36] for CMRR enhancement . . . 46

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3.1 Block diagram of a processing biomedical signal acquisition system. . . 51

3.2 Preamplifier block diagram of Figure 3.1 . . . 52

3.3 Folded Cascode Operational Amplifier. (a)Topology of the folded cas-code amplifier. (b)CMFB of the folded cascas-code amplifier. . . 53

3.4 Frequency response of the FCC Amplifier of Figure 3.3 . . . 56

3.5 DC response of the FCC Amplifier of Figure 3.3 . . . 57

3.6 CMRR of the FCC Amplifier of Figure 3.3 . . . 57

3.7 PSRR of the FCC Amplifier of Figure 3.3 . . . 58

3.8 Block diagram of the offset compensation technique. . . 61

3.9 Topology of the Offset Compensation Circuit. . . 61

3.10 Frequency Responses of the system of Figure 3.8 . . . 63

3.11 FCC Amplifier with Offset Compensation Scheme. . . 64

3.12 Frequency Response of the FCC amplifier with Offset Compensation. . 65

3.13 CMRR of the FCC amplifier with Offset Compensation . . . 66

3.14 Offset of the FCC amplifier with Offset Compensation . . . 66

3.15 Topology of the CMRR Enhancement Circuit. . . 67

3.16 FCC Amplifier with CMRR Enhancement Circuit . . . 68

3.17 Frequency Response of the FCC amplifier with CMRR Enhancement Circuit . . . 69

3.18 CMRR of the FCC amplifier with CMRR Enhancement Circuit . . . . 70

3.19 Offset of the FCC amplifier with CMRR Enhancement Circuit . . . 70

3.20 FCC Amplifier with Offset Compensation Scheme and CMRR Enhance-ment Circuit. . . 71

3.21 Frequency Response of the FCC amplifier with CMRR Enhancement Circuit and Offset Compensation Scheme . . . 72

3.22 CMRR of the FCC amplifier with CMRR Enhancement Circuit . . . . 73

3.23 Offset of the FCC amplifier with CMRR Enhancement Circuit and Offset Compensation Scheme . . . 73

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LIST OF FIGURES xiii

4.1 Topology of the High Voltage Tunable Resistor. . . 76

4.2 Resistance of the HVTR vs Control Voltage @VAB = 1V . . . 77

4.3 Frequency Response of the Resistance of the HVTR vs Control Voltage @VAB = 1V . . . 77

4.4 Topology of the Amplifier implemented in the Band Pass Filter. . . 78

4.5 Frequency Response of the Amplifier of the Band Pass Filter. . . 79

4.6 DC Response . . . 80

4.7 Analysis of Power Supply Rejection Ratio of the Amplifier of Band Pass Filter. . . 80

4.8 Analysis of the Common Mode Rejection Ratio of the Amplifier of Band Pass Filter. . . 81

4.9 Slew Rate of the Amplifier of Band Pass Filter. . . 82

4.10 Current of the BPF Amplifier . . . 82

4.11 One Stage Topology of the Band Pass Filter. . . 84

4.12 One Stage Topology of the Band Pass Filter with the HVTR model. . . 84

4.13 One Stage Topology of the Band Pass Filter with RC modelled effects in HVTR model, . . . 85

4.14 Topology of the Band Pass Filter. (a)Three-stages block diagram of the BPF. (b)One stage topology of the BPF. . . 86

4.15 Tunable Band Pass Filter Frequency Response . . . 87

4.16 Band Pass Filter Sweep of the Low Frecuency Cutoff. . . 88

4.17 Sweep of the High Frecuency Cutoff . . . 88

4.18 Second and third Harmonic Distortion Percentage of the Band Pass Filter. 89 4.19 Layout of the Tunnable Band Pass Filter . . . 90

4.20 Topology of the Amplifier for the Notch Filter . . . 91

4.21 Frequency response of the Amplifier of the Notch Filter. . . 92

4.22 CMRR of the Amplifier of the Notch Filter. . . 93

4.23 PSRR of the Amplifier of the Notch Filter. . . 93

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4.25 Swing and offset of the Amplifier of Figure 4.20 . . . 94

4.26 One Stage Notch Filter Topology. . . 96

4.27 Block diagram of the Tunable Band Pass Filter and Notch . . . 97

4.28 Frequency Response of the Tunable Notch Filter . . . 98

4.29 Central Frequency Sweep of the Tunnable Notch Filter . . . 98

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List of Tables

1.1 Band Frequencies of Biopotential Signals Classification. . . 2

1.2 Design Specifications of the Preamplifier for Preprocessing Biopotentials Systems . . . 3

1.3 Qualitative and Quantitative Comparison of the State of the Art for Offset Compensation and 1/f Noise Reduction Techniques . . . 9

1.4 State of the Art Quantitative Comparison for Biomedical Acquisition Systems . . . 11

1.5 State of the Art Quantitative Comparison for Biomedical Acquisition Systems . . . 11

1.6 Qualitative and comparative description of the Biomedical Acquisition Systems in the State of the Art . . . 12

1.7 Quantitative and comparative description of the Biomedical Acquisition Systems in the State of the Art . . . 14

1.8 State of the Art of Notch Filters . . . 15

1.9 State of the Art of Band Pass Filters . . . 16

1.10 Design Specifications for the preamplifier based on the state of the art. 18 3.1 Sizing of the Folded Cascode Amplifier of Figure 3.3(a). . . 54

3.2 Sizing of the CMFB circuit used in the FCC of Figure 3.3 (b). . . 54

3.3 FCC Design Parameters. . . 55

3.4 Technology characterization data. . . 55

3.5 Characterization of the FCC amplifier . . . 59

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3.6 Performance Characteristics of the Closed Loop FCC Amplifier. . . 60

3.7 Poles and zeros distribution of Figure3.8 system . . . 62

3.8 Sizing of the offset compensation circuit. . . 63

3.9 Sizing of the CMRR enhancement circuit. . . 67

4.1 Designed Values for the HVTR of Figure 4.1.. . . 75

4.2 Transistors Sizing of the Amplifier of Figure 4.4. . . 79

4.3 Performance Characteristics of the BPF Amplifier . . . 83

4.4 Resistor’s Value for the Band Pass Filter for the different biomedical band. 86 4.5 Control Voltages of HVTR to each Biomedical Band. . . 87

4.6 Performance parameters of the band pass filter obtained by simulation for different bandwidths. . . 89

4.7 Sizing for the Amplifier of Figure 4.20. . . 92

4.8 Performance Characteristics of the Notch Amplifiers . . . 95

4.9 Performance parameters of the notch filter obtained by simulation.. . . 97

4.10 Control Voltage of HVTR for each Biomedical Band with the central frequency of the notch at 60Hz. . . 99

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Chapter 1 Introduction

1.1 Analog preprocessing of biomedical signals

Because of the tough requirements to develop noninvasive monitoring and testing sys-tems for medical care, engineers have been deeply involved in the pursuit of innovative design and development of electronic devices. The importance of Portable Monitoring Systems (PMS) lies in the timely diagnosis of several diseases, avoiding a chronic or deadly condition for the patients with certain cardiac affections, or epilepsy attacks, dif-ference between a prompt medical attention of a deadly condition for the patient. Nev-ertheless, biopotentials monitoring systems require high density multi-electrode readout systems up to hundred of channels, increasing their power consumption and silicon area. Nowadays, these systems are implemented by Application Specific Integrated Circuit technology (ASIC) as well as multichannels suitable Integrated Circuits (IC’s). ASIC high level integration allows the creation of Personal Body Area Network (BAN) whose main task is recording biopotential signals in a non-invasive way via PMS. Example of such signals are Electroencephalogram (EEG) , Electrocardiogram (ECG) or Electro-miogram (EMG) .

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Table 1.1: Band Frequencies of Biopotential Signals Classification.

Band(Hz) Application Specifications [3]

0.05-100

* QRS spike 400µV-2.5mV peak.

ECG * Gain requirements 103.

* Requires Notch Filter.

* Requires High Imput Impedance>100MΩ

0.2-100

* EEG potential (20 to 200)µV peak.

* Gain requirements 104 to 105.

EEG * Low amplitude Signals.

* Low frequency.

* Requires low 1/f noise amplifier.

50-3K

* Biopotentials (20 to 200)µV peak.

EMG * It may require needle electrodes.

* Required Gain 103.

* Requires programmability in-band.

Table 1.1 shows the corresponding band frequencies and its related applications and specifications. According with this table, the systems must lie tunable in one of the three different frequency bands ranging from 0.05Hz to 3kHz. The amplitude levels of the skin biopotential are signals between 20µV and 100mV, which means the pream-plifier noise levels to be ten times below the minimum biopotential amplitude, in order to minimize disturbances in the preprocessed signal. Another important issue is the input impedance which must be higher of one hundred Mega ohms, disabling the cur-rent paths from the patient to the device in case accidental contact with the power line which is specially important for ECG systems [3]. The most common way to imple-ment monitoring systems is using wet-(gel based) electrodes which causes discomfort in the patient and requires qualified personnel to assist the monitoring process, making it unsuitable for ambulatory medical applications. Therefore, wet-based electrodes can be replaced by gel free electrodes implemented via active readout circuits. Gel-free electrodes implementation increases the tissue contact impedance as well as the

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inter-1.2. PREAMPLIFIERS SPECIFICATIONS AND INVOLVED NON IDEAL EFFECTS3

ference due to mains and cable movements at the equipment. Usually, 50/60Hz notch filter is used to overcome this conditions [2].

1.2 Preamplifiers Specifications and involved non

ideal effects

Table 1.2: Design Specifications of the Preamplifier for Preprocessing Biopotentials Systems

Gain 1000-10000

Bandwidth (BW) [Hz] 0.05 -10k Dynamic Range (DR) [dB] 60-100 Input Impedance (Zinput) [Ω] >100M

Input Referred noise (IRN) [nV /√Hz] <50 Common Mode Rejection Ratio (CMRR) [dB] >110

In agreement with Table1.10, high-gain low-noise preamplifier circuits are required as the first stage of a recording biopotential system. Unfortunately, noise contributions provide one limitation to precision of biomedical measurements. The degree to which a biosignal is resolvable can be determined by the signal-to-noise ratio at the output of the signal conditioning system. Minimizing the impact of random noise in a measure-ment system often involves an efficient choice of low noise amplifiers and components. Hence, preamplifiers in biomedical signal processing are usually designed in differential mode due to nature of the measure scheme, since the biomedical signals are referred to a reference electrode. Biomedical signals voltages are between 1µV to 100mV, with frequencies bellow to 10kHz [4]. Next, Table 1.10 presents the design specifications for bio-potentials preamplifiers.

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1.2.1 Noise Effects

As mentioned before, noise establishes the minimum signal level that a circuit can process with acceptable quality. Therefore, analog designers have to deal with the problem of noise because it is related to power dissipation, speed and linearity issues [5]. The electrical noise is a current or voltage signal that is unwanted in an electrical circuit. Real signals are the sum of this unwanted noise and the desired signals. [6] The noise components could be classified as follows: (i) Internal noise or inherent circuit noise, which results from the discrete and random movement of charge in a wire or device and has a random nature; (ii) External noise sources, which is generated as a result of the electromagnetic interaction between the circuit and the environment or among different parts of the circuit and, its nature could be random, periodic or intermittent. Although external noise is usually reduced using layout techniques, inherent circuit noise contributions are minimized during design stage by considering each device noise contribution (noise contributions will be described in next chapter). An important consideration that should be noticed due to randomness of noise is that its frequency components are random in both amplitude and phase. Although the long-term rms value can be measured, the exact amplitude at any instant of time cannot be predicted [7]. It is possible to predict the randomness of noise since noise is usually described by a Gaussian or normal distribution of its instantaneous amplitude.

1.2.2 Offset Effects

An important issue that must be taken into account when designing analog circuits is mismatch, which is the process that causes time-independent random variations in physical quantities of identically designed devices, it is a limiting factor in general pur-pose analog signal processing [8]. For an amplifier, as shown in Figure1.1, the mismatch produces input offset contributions whose are differential input voltages that forces the output voltage to go to zero [9]. It affects the figures of merit of the amplifier. For in-stance, the DC power supply rejection ratio (PSRR) and common-mode rejection ratio (CMRR) could be defined as the change of the input referred offset ∆VOS, as can be

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1.2. PREAMPLIFIERS SPECIFICATIONS AND INVOLVED NON IDEAL EFFECTS5

Figure 1.1: Amplifiers with offset: (a)differential input voltage equal to input offset voltage forces output to zero, (b) output offset of an amplifier with shorted inputs.

observed in (1.1) and (1.2) [9], where ∆VDD and ∆VCM are the changes in power supply

voltage and input common-mode voltage. Reciprocally, the offset can also change due to changing input common mode and power supply voltages.

P SRR= ∆VDD ∆VOS

(1.1)

CM RR= ∆VCM ∆VOS

(1.2)

1.2.3 Offset Stabilization Techniques

The input referred offset of typical CMOS amplifiers is at the millivolt range, wich lim-its their accuracy and compromising their usefulness in portable monitoring systems. Hence, several techniques have been developed to solve this issue. The most common of those techniques will be briefly described next and further commented in chapter 2.

In order to design an offset compensated amplifier, electronic designers must keep the circuit implementation as simple as possible while silicon area and power consumption are minimized [9]. At very low frequencies, offset becomes the dominant error. Al-though offset is usually modelled as a time-invariant voltage source, it may change due to aging and temperature variations. This implies that it has a certain bandwidth and can therefore be considered as a very low-frequency noise source [10].

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Therefore, the need of low-offset amplifiers in measurement systems has become usual due to its application in several areas as read-out electronics of strain gauges, ther-mocouples, piezoelectric sensors, Hall sensors, photo diodes and read-out circuits for biomedical signals.

There are different classifications for offset compensation techniques. One of them could be in dynamic (AutoZeroing, Correlated-Double Sampling, Chopper) or non dy-namic (Trimming) techniques. A second one could be made by the way to reduce offset and low frequency noise, rather than sampling or modulation. Having Auto Zeroing (AZ) and Correlated -Double Sampling (CDS) in the first group and Chopper Stabi-lization and Nested Chopper Compensation in the second one [9].

Since precision of static offset compensation techniques such as Fowler Nordheim or trimming circuits are gradually affected due to transistors aging [11], in this work only dynamic compensation techniques, named offset stabilization techniques, will be de-scribed. Also, offset drift with temperature, obligating the use of the dynamic offset stabilization [12].

Dynamic offset stabilization techniques operate in continuous time, preserving the band-width. Figure1.2 represents this technique which consists of an auxiliary amplifiergmc

with input referred offsetVOSc, measures the offsetVOSm of the main amplifiergmm and

it is compensated by applying a voltage in the auxiliary port. With Ac Aaux >> Am,

the input referred offset becomes [12]:

VOS =

Am

AcAaux

VOSm −VOSc ≈

1

Ac

VOSm−VOSc (1.3)

whereAc,AmandAauxare respectively the voltage gains ofgmc,gmm and the auxiliary

port. However, from equation (1.3) Ac must be high and the offset voltage produced

by the auxiliary amplifier VOSm must be reduced by carrying out in gmc auto-zero or

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1.2. PREAMPLIFIERS SPECIFICATIONS AND INVOLVED NON IDEAL EFFECTS7

Figure 1.2: Offset Compensation scheme

a) Auto-zero offset stabilization: Offset is sampled in phase one and subtracted from the signal in another phase. Because of the sampling action this technique is not suitable for continuous time operation. Furthermore, it still presents residual offset as a result of charge injection of switches.

b)Chopper offset stabilization: Offset is modulated in frequency, to be after removed using a low pass. The cost of this technique is a large ripple at the output that penalizes the bandwidth and produces residual offset. Moreover, this filter makes this technique unsuitable for high bandwidth applications.

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To overcome these disadvantages, in this thesis an offset stabilization based on con-tinuous time DC feedback, quasi-infinite resistors and Quasi Floating Gate transistors is proposed. Such technique avoids the need of a high gain compensation loop, modu-lated signals and offset compensation, circumventing charge injection, chopper ripple, noise folding and bandwidth degradation.

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1.3. STATE-OF-THE-ART 9

1.3 State-of-the-Art

In order to recap the reviewed data in the state of the art, Table 1.3 summarized the Offset stabilization techniques.

Table 1.3: Qualitative and Quantitative Comparison of the State of the Art for Offset Compensation and 1/f Noise Reduction Techniques

Technique Offset Noise Drawbacks

Trimming (e.g. with QFG transistors [13])

* Non-standard CMOS process

±25µV 8.9µVrms * Post fabrication treatment are require

* 1/fnoise and dynamic offset are not compensated

* Requires extra settings to clear capacitive memory of the QFG transistors.

Auto−Zero stabilization technique (e.g. Ping Pong [14])

* High power consumption

* Charge injection and switched noise effects

4µV 28nV /sqrtHz * Only applicable in sampled data systems * Low speed

* White noise is increased

* Uses multiple amplifiers

* and multiple phase clocks

* Increases area and power of the system

Large Scale Exitation

* It is used only to reduce 1/fnoise

* it needs a sampled signal

* It can not be simulated or easily calculated

CDS with LSE * Increase the flicker noise instead of reduce it

Chopper Stabilization technique

The passive filters are hard to integrate

1µV [15] 0.8µVrms [16] * Limited to low-band applications

* When it is used nested chopper, the BW is severely reduced

DC Servo Loop

* It operates in DC or very low frequencies

* The accuracy or this approach depends on the value of internal matching resistors

As it can be noticed in the above table, trimming presents the largest offset volt-age, compared with other techniques. Besides, it needs non-standard CMOS process and post fabrication process, which means expensive and complex fabrication. Auto-zero stabilization presents a lower offset voltage compared with trimming, however, its noise power is the highest of both techniques. In addition, its high power consumption and low speed, besides the required complexity and silicon area, makes Auto-zero non practical if a low-power system is desired.

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Chopper presents the lowest noise power in table 1.3, but it requires passive filters which can not be easily integrated. Besides, this technique has a limited operation band frequency and when undergo through nested chopper, badwidth may be reduced. Similarly, DC Servo Loop operation is confined to DC or very low frequencies, and one of the drawbacks consists in the need of well matched resistors.

In the state of the art for biopotentials readout circuits, topologies that do not use chopper modulation suffer from 1/f noise while their CMRR is usually limited by com-ponents mismatch. An alternative is the use of chopper stabilized capacitive-coupled amplifiers which modulate the input signal before applying it to their input capacitors and so attenuate 1/f noise and increase CMRR. The disadvantage of this technique is the reduction of the input impedance, which can be solved by relocating the input chopper to the virtual ground inside the feedback loop. However, this approach limits the CMRR because of the capacitor mismatch. This disadvantages could be overcome using a chopper stabilized current amplifier with voltage follower inputs [2], however the offset rejection capability will be limited.

Next, Tables 1.4, 1.5 and 1.6 present a quantitative and qualitative comparison re-spectively of the biomedical FE acquisition systems reviewed.

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Table 1.4: State of the Art Quantitative Comparison for Biomedical Acquisition Sys-tems

Parameter [17] [18] [19] [20] [21]

Technology 0.5µm 0.5µm 0.5µm 0.5µm 0.5µm

Supply (V) 3.3 ±1.5 3.3 3 3.3

Current (A) 12.8µ - - 20µ 16.5µ

Voltage Gain (dB) 60 67.7/77.1 ** 48-57/75-79 ** 52/58/63/68 ** 48

HPf−3dB(Hz) 30-1K * 0.1-1K * 0.7-1.95 * 0.3-0.34 * 250

LPf−3dB(Hz) 700-10K * 300-5.4K * * 14-15.8 * *

Input Referred Noise (µVrms) 5.1 3.9(10Hz-10KHz) 5.8 2.4

NEF 4.1 - - - 4.2

THD (%) - 1(40% full swing) - 0.45-0.52

-CMRR (dB) - 139 - >120 >107@5KHz

PSRR +/- (dB) - 65/- - >80/>78

-Power (W) - - 13.7µper channel 60µ 54.4µ

Area (mm2₎ _- _- _{0.12 per channel} _1.95

-*tunable frequency, ** tunable gain

Table 1.5: State of the Art Quantitative Comparison for Biomedical Acquisition Sys-tems

Parameter [22] [2] [23] [24] [25] [26] [27]

Technology 90nm 0.18µm 0.18µm 0.18µm 0.35µm 0.35µm 0.35µm

Supply (V) 3 1.8 1.8 1 1 0.8-1.5 1

Current (A) 35.5µ 11µ - 21µ 1.26µ 330n 33n/337n

Voltage Gain (dB) 54/68 ** 40 20/60 ** - 45.7/49.3/53.7/605 ** 40.2 45.6/49/53.5/60 **

HPf−3dB(Hz) 0.4* - - - 0.23-217* 3m 4.5m-3.6 *

LPf−3dB(Hz) * - - - 7.8K 245 31-202

Input Referred Noise (µVrms) 51.4nV /√Hz 0.8(0.5Hz-100Hz) 2.2(1Hz-1KHz) 1.9 4.43(1Hz-12KHz) 2.7 2.5(0.05Hz-460Hz)

NEF 8.5 12.3 - - 2.16 2.8 3.26

THD (%) 0.77 - - - 0.53(full swing) 0.05 0.6

CMRR (dB) 140 82 - 100 58 61/64 >71.2(up to 300Hz)

PSRR (dB) - 40 67 - 40 62/63 >84(up to 300Hz)

Power (W) 106.5µ - 323.5µ 36µ 3.77µper channel 3.4µ 445n-895n

Area (mm2₎ _- _6.48 _11.23 ₉ _- ₁ ₁

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Table 1.6: Qualitative and comparative description of the Biomedical Acquisition Sys-tems in the State of the Art

Scope Features Technique

Active Electrode System for Monitoring [2]

*Front End System *CMRR: Back End CMFB

*Preamplifier with BPF *Offset: Digitally assisted Offset Trimming

*8 Channels System *Noise: Chopper

*Capacitive Feedback *Other: Input impedance boosting

Implantable Neural Recording [25]

*16 Channels FE with PGA *CMRR:

-*tunable HPf−3dbof BFP and *Offset:

-*4 Gain settings *Noise:

-*10 bit-SAR ADC dual capacitive array *Other: Bootstrapped technique

Wireless Neural Recording System [17]

Rectifier, Voltage regulator, clock and command recovery *CMRR:

100-Electrode System, 10-bit charge redistribution ADC *Offset:electrode ac coupled with the amplifier

10x10 array of neural amp and spike detectors *Noise: use large PMOS devices

433-MHz FSK data transmitter

Wireless Neural Recording System [18]

32-ch implantable with adjustable resolution BPF CMRR:

Based on time division multiplexing of PWM signals Offset:

The FE consists of an array of 2 tage capacitvely coupled LNAs Noise:

Low cutt-off tunable via pseudo resistors

Neural Recording Amplifier [19]

*Preamplifier with BPF and simple noninverting amplifier *CMRR:

*Two Programmable Gain and *Offset:

*Two Programmable BW with 2 Bits each one *Noise:

*PMOS resistance and capacitive feedback

Readout FE for Portable Biopotential [20]

*FE for Portable Biopotentials *CMRR: Chopper

*ACCIA, Chopping Spike Filter and VGA stages *Offset: AC Coupling

*Digitally controlable Variable Gain and BW *Noise: Chopper

FE ASIC for EEG [23]

*8 Channels Mixed-Signal FE ASIC for EEG *CMRR:

*Preamplifier with variable gain *Offset: Compensate Digitally by 2 current mode DACs

*RC LPF and Switch Capacitor LPF with 2 selectable bands *Noise: Low noise non inverting Op Amp with resistive feedback

*12 Bit SAR ADC *

Adaptive Interface for Portable Biomedical [24]

*FE IA with BPF, PGA and SAR ADC *CMRR:

*Gain and BW digitally controllable *Offset: ADC

*10 bits adaptable SAR ADC *Noise: Chopper

*Adaptive Control

Biomedical Signal Acquisition IC [26]

*Low noise IA with DC rejection *CMRR

*capacitor array based 11 bit SAR ADC *Offset

*DC rejection using pseudo resistors *Noise: Current steering logic gates to reduce switching noise.

*Start up circuit

Programmable Biomedical Sensor Interface [27]

*Tunable BW - FEA *CMRR

*PGA with 4 levels voltage gain *Offset: Balance Tunable Pseudo-resistor

*12 Bit SAR ADC *Noise:Large gate area input transistors

*Relaxation Oscillator *Other: flip-over capacitor in feedback loop

Neural Recording Amplifier [21]

*Assymetrical Diferential Diference Amplifier (DDA) *CMRR: Assymetrical DDA

*A local feedback at the amplifier output *Offset:Local feedback at the amplifiers output

*DDA realized with 2 OTAs with different transconductance *Noise:

Biopotential Signal Readout FE [22]

*Front stage IA *CMRR:

*Gain and BW adjustable via internal resistor *Offset:Chopper

*AC coupler and Chopper notch filter Noise: Thick and thin oxide of the transistors

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Note that according to the three latter tables, five of twelve state-of-art biomedical acquisituion systems are designed and fabricated using a 0.5µm CMOS technology, and four of them count on tunable frequency and/or tunable gain. A similar case is pre-sented in Table1.5, where it can be noticed that four of the seven works listed, count on the tunablilty feature. Such list shows sub-micrometric front-end systems and [26] with a technology of 0.18µm presents the best power noise value. However, the same table lists the largest power consumption, presented in [23].

In table 1.6 a state of art qualitative description of the biomedical acquisition sys-tem is presented. Note that more than half of the listed works, lack CMRR reduction techniques and one third of the works implement some offset compensation technique. On the other hand, all the works but two in the list, count on certain noise reduction approach.

Table 1.7 represents a quantitative description of biomedical acquisition systems re-viewed, emphasizing on their CMRR, noise and offset performance. Common Mode Rejection Ratio ranges from 58dB to 140dB, while the offset levels are in between 20mV to 50mV. Finally, noise range in table1.7 goes from 0.8µVrms up to 5.8µVrms. The Table 1.7 represents a quantitative description of biomedical acquisition systems reviewed, emphasizing on their CMRR, noise and offset performance.

As it can be observed, the smallest level of noise is presented in [2]. Respect to offset performance, the best achieved value by 4 references is of 100mV; The best CMRR is achieved with a 90nm process technology, up to 140dB.

Equations (1.4) and (1.5) describe the Noise Efficiency Factor and a Figure of Merit commonly used in the blocks of a front-end amplifiers and band pass filters respectively.

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Table 1.7: Quantitative and comparative description of the Biomedical Acquisition Systems in the State of the Art

Reference

CMRR

Offset

Noise

[

2 ]

82db @50Hz

20mV

0.8 µ

Vrms(0.5-100Hz)

[

25 ]

58db

-

4.43 µ

Vrms(1Hz-12KHz)

[

17 ]

-

5.1 µ

Vrms

[

18 ]

139 -

3.9 µ

Vrms(10Hz-10KHz)

[

19 ]

-

5.8 µ

Vrms

[

20 ]

120dB

±

50mV

57 nV /

√

Hz

[

23 ]

-

2.2 µ

V(1Hz-1KHz)

[

24 ]

100dB

100mV

1.9 µ

Vrms(0.1Hz-200Hz)

[

26 ]

61-64dB

100mV

2.7 µ

Vrms(0.05Hz-245Hz)

[

27 ]

71.2dB up to 300Hz

2.5 µ

Vrms(0.05Hz-460Hz)

[

21 ]

>

107dB

2.4 µ

vrms

[

22 ]

140 dB up to 1KHz

±

50mV

51 .

4 nv/

√

Hz

N EF = V rms, in

r

2∗IT otal

π∗UT ∗4kT ∗BW

(1.4)

F oM = P ∗VDD

η∗fc∗DR

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Table 1.8: State of the Art of Notch Filters

Reference [28] [29] [30] [22]

Technology 0.18µm 0.6µm 90nm 90nm

Power Supply Voltage [V] 1.8 - 3 3

Center Rejection Freq [Hz] 50 50 50/60 50

Center attenuation [dB] 55.4 58.5 25/41 41

Q 1.17 - 0.1/0.5

-Input Refered Noise [µV /√Hz] 4.12@(1KHz) - -

-PSRR [dB] 65 - -

-Dynamic Range [dB] 78 - -

-Upper−3dBF req [Hz] 71.6 - -

-Lower−3dBF req [Hz] 29 - -

-Power Consumption [µW] 25.2 - 75

-Die area [mm2_] _0.06 _- _-

-Tables 1.8 and 1.9, summarize the quantitative description of notch and band pass fil-ters respectively, reviewed in the state of the art. Reference [30] summarized in Table 1.8 presents two modes of selectivity in center rejection frequency, center attenuation and quality factor. Reference [28] is the only one that exhibits an input referred noise measurement at 1KHz of 4.12µV /√Hz. Most of works presented are designed to re-ject a 50Hz frequency. In table 1.9 references [31], [32] and [34] present selectivity in bandwidth, a reduced power consumption down to 14.4nW and up to 1.2µW. All these filters are designed with a fourth order topology.

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Table 1.9: State of the Art of Band Pass Filters

Reference [31] [32] [33] [34]

Technology 0.35µm 1.5µm BiCMOS 0.35µm 0.18µm

Power Supply Voltage [V] 1 2.8 2.2 1

Noise [µVrms] - 776/796 19µV /√Hz 50

THD [%] - - - 1

Order 4 4 4 4

Center Freq [Hz] - - 54M-74M 732

DR [dB] - 67.5/65 - 55

Power Consumption [W ] 1.2µ 230n/6.36µ - 14.4n

FoM - - - 0.89×10−13

Area [mm2_] _- _- _- _0.132

BW Hz 40-90 100-200/5K-10K - 523-1024

Sampling Freq [KHz] 1 - -

-In Band Gain [dB] 44.5 - -

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-1.4. GOALS AND DESCRIPTION OF THIS WORK 17

1.4 Goals and Description of this work

− + − + − + OU T SKIN ELECTRODE LNA BPF NOTCH PGA ADC − + − + Vp Vn CMRR Enhancement Circuit

auxport1 auxport2

V outnamp

V outpamp

OFFSET COMPENSATION

FE - Amplifier

Figure 1.3: Block Diagram for an EEG acquisition system

The design and simulation of a Biopotential Acquisition System is presented in this work. Specifically, the design of both, low noise dynamic offset compensated preampli-fier and the proper band limiting filter are described.

The amplifier design will avoid some of the auto-zero stabilization disadvantages (e.g. charge injection, requirement of a multi-phase local oscillator, increase of low frequency noise) and those from chopper stabilization (local oscillator, charge injection, output signal ripple), preserving flicker noise levels low enough to sense signals within ECG, EEG and EMG band frequencies, listed in Table1.1.

Next questions must be answered with aim on making advances on the state-of-the-art of low noise preamplifiers:

• In order to avoid problems related to switches in offset stabilization techniques: is it possible to perform DC Feedback offset compensation, not affecting the input

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equivalent noise and satisfying ECG, EEG and EMG requirements?.

• According to equations1.1 and 1.2, there is a codependency between CMRR and Offset, then: is it possible to incorporate a CMRR enhancement block with the amplifier design, in order to improve the most important figures of merit of the amplifier, such as input equivalent offset, PSRR, THD and power consumption?.

• In order to reduce silicon area and enable the use of on-chip capacitors, is it possible to incorporate HVTR (high resistive elements) with the design of the low-pass filter including in the offset compensation scheme?, does this affect any figure of merit?.

• A low noise folded cascode amplifier is designed, starting from design equations in Chapter 3. A folded cascode amplfier (FCC) topology is selected since it counts on a good tradeoff between gain, bandwidth and hardware complexity. Specifications based on state-of-art of tables 1.4 and 1.5 are listed next:

Montecarlo analyses based on Pelgrom’s missmatch model [35] are performed along with the simulations.

Table 1.10: Design Specifications for the preamplifier based on the state of the art.

Parameter Value

Supplly ±1.65V

Bias Current < 12µA

Gain 40dB

THD < 1%

CMRR >80dB

PSRR >60dB

Static Power

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1.4. GOALS AND DESCRIPTION OF THIS WORK 19

• A CMRR enhancement block is added to the FCC topology, comparing simula-tions performance of the FCC amplifier with and without such block.

• An Offset Compensation DC Feedback circuit is attached to the FCC amplifier. Performance of the original FCC amplifier and the one with offset compensation are compared by simulation.

• Both, Offset and CMRR compensation blocks are attached to the FCC amplifier and simulation results are compared

• Besides of improvements of the figures of merit, the reuse of circuit blocks is attempted. It is particularly desirable exploit the capactive feedback and the input QFG transistors to perform the low-frequency filtering function of the offset compensation.

Based on state-of-the-art tables 1.8 and 1.9, and specs presented in Table 1.1, next research questions are presented, regarding to the band limiting filter:

• Is the filter electrically tunable in order to fulfill the ECG, EMG and EEG fre-quency band requirements?.

• Could the filter be designed including HVTR to achieve all capacitors to be on-chip?.

• Are both filters, notch and bandpass tunable?.

• Is it possible to stablish a very low power consumption of the filter to take as much power as possible in the input stage (preamplifier)?.

Next methodology is presented to design the filters:

• A band-pass topology is chosen, which is made up by a high-pass first stage and a low-pass second stage, in order to have the cut-off frequencies tunability independently one of each other.

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• HVTR elements are used with the aim of achieve cut frequency selectivity. Fea-tures of HVTR allow modification of the system RC constant. This is accom-plished varying the resistivity of such elements, by means of different bias volt-ages.

In order to reduce some undesirable effects in the acquired signal due to external cable motion or mains, a 50/60 Hz stop band filter has been proposed with the next design methodology:

• A twin tee topology with reduction of silicon area and power consumption has been chosen, hence the Q of this filter is directly dependent on its resistances value.

• The large time constants has been obtained with small on chip capacitors an HVTR avoiding the demand of external pads and representing area reductions respectively.

• The use of the HVTR elements working in subthreshold region let us obtain a wide range of tunability ot the resistance, achieving a large tunability in band.

• The stop frequency tunability may be selectable through an HVTR as well as the BW may be selectable by another HVTR independently. The resistance of these HVTRs is selectable trough their voltage control which is tunable with an external bias source with a step of selectivity of 10mV.

• So, with a tunable fc and BW the quality factor (Q) of the notch filter may be

modified. The design specifications of Q has been set at 10, and the RC elements has been sizing to meet with this specification.

The structure of this thesis is organized as follows: Chapter 2 includes the theoretical framework of this work, which consist of the principles of design and techniques. In chapter 3, the proposed design techniques for each block are presented. The preampli-fier consist of a low noise amplipreampli-fier with high gain, and low power consumption based on a Folded Cascode Topology (FCC).

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1.4. GOALS AND DESCRIPTION OF THIS WORK 21

A CMRR enhancement technique presented in [36] is used to achive a high CMRR with the improvement of monte carlo simulations do to mismatch between inverter blocks. An offset compensation scheme performed by an inverter amplifier whose output signal is reinserted in the system throughout the reference voltage node in a quai floating gate (QFG) transistor. The tunable band pass filter is implemented with a three order scheme conformed by OTA amplifiers and a two stage high pass and low pass config-urations made with fixed capacitors and high value tunable resistors. The notch filter is implemented with a twin tee topology, achieving the tunability of this block with the use of high voltage tunable resistors as well as in the previous block. In chapter 4, simulation results for each component of the FE system are presented, with summary tables that presents the performance of the amplifiers used in each block and the main characteristics of each design. The system was design in 0.5um AMI process. Finally, conclusions and future work of this thesis are discussed in chapter 5.

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Chapter 2 Theoretical Framework

2.1 Thermal Noise

Thermal noise is generated only in dissipative systems. Therefore, it is associated with all resistors and lightly doped semiconductor layers [39].

a) Resistor Thermal Noise.

Thermal Noise in resistors is caused by brownian motion of electrons in a conduc-tor, and introduces fluctuations in the measured levels of voltage or current across the resistor. The DC component of the fluctuation is zero [39]. The Nyquist’s Theorem states that for linear resistances in thermal equilibrium at temperatureT, the current or voltage fluctuations are quite independent of the conduction mechanisms, type of material, shape and geometry of the resistor. The generated noise depends exclusively upon the value of the resistance and its temperature T (given in kelvins) [39]. Hence, the spectrum of thermal noise is proportional to the absolute temperature. The thermal noise of a resistor R can be modelled by a series voltage source (Th´evenin equivalent) or parallel current source (Norton equivalent) as shown in Figure 2.1.

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R

+

−

V2 n

N oiseless Resistor

Sv(f)

f

4kT R

Figure 2.1: Thermal noise of a resistor

Assuming ∆f = 1Hz the noise spectral density and the noise voltage and current spectral densities are represented by:

Sv(f) = 4kT R∆f, [V2/Hz] (2.1)

S(Vn) =

V2 n

∆f = 4kT R, [V

2_/Hz_] _(2.2)

S(In) =

i2 n

∆f =

4kT

R = 4kT G, [A 2

/Hz] (2.3)

wherek= 1.38x10−23_[_J/K_{] is the Boltzmann constant. Note that} _S

v(f) is expressed in

V2_/Hz _{and can be written as} _V2 n [5].

b) MOS Thermal Noise.

The most significant thermal noise source in a MOS transistor is the noise generated in the channel. For long-channel MOS devices operating in saturation region, the channel noise can be modelled by the circuit presented in figure2.2with a spectral density given by (2.4).

I2

n= 4kT γgm

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2.2. FLICKER NOISE 25

I2 n =

id2

∆f = 4kT γgds (2.4)

with VDS = 0, gds is the transconductance of the transistor in saturation region. The

correction factorγ is called the excess-noise factor, and it has a value close to unity for the linear region and 2/3 for a long channel-saturated transistor in strong inversion [40]. In weak inversion, the spectral density becomes:

I2 d

∆f = 4kT

gs+gd

2 (2.5)

For a saturated transistor in weak inversion (gs gd) is considered.

2.2 Flicker Noise

All active devices and some passive devices, such carbon resistors, a band of noise at low frequencies, in addition to thermal noise, which is called flicker excess noise (1/f noise) [40]. The 1/f noise has many unique properties, such is the limitless increment of the noise spectral density with the frequency decrement. The main cause of 1/f noise in semiconductor devices is referable to properties of the surface energy states and the density of surface states. Improved surface treatment in manufacturing has decreased 1/f noise, but even the interface between silicon surfaces and grown oxide passivation are noise sources [7].

Unlike thermal noise, the average power of flicker noise cannot be easily predicted. Hence, there is no universal mechanism responsible for 1/f noise. A procedure to deter-mine 1/f noise parameters appart of noise measurements is not known. However some equations for a first hand calculations are presented next.

a) Flicker Noise in Integrated Resitors.

The 1/f noise voltage developed in integrated resistors has the general form given by equation 2.6.

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V2 n =KR

R AR

V_DC2 δf

f (2.6)

where VDC is the DC voltage across the resistor, R is the sheet resistance, AR is the

area of the resistor, andKRis a technological constant. For a diffused or ion-omplanted

resistor,KR∼= 5x10−24[S2cm2], while for thick-film resistors, it is aproximated 10 times

greater [39].

b) Flicker Noise in CMOS devices.

The effect that dominates flicker noise in MOSFETs is when electron tunnel from traps in the oxide to the gate and the conducting channel, and vice versa. It is modelled as a voltage source in series with its gate (see Figure2.3) and its spectral density is roughly given by:

20log

V

2 n

log

f

Figure 2.3: Flicker noise of a CMOS Transistor

V2 g

∆f = KF

CoxW L

1

f (2.7)

whereKF is a process-dependent constant on the order of 10−25[V2F].

The only way to achieve a significantly flicker noise reduction is to lower the surface-state density in the vicinity of the Fermi level. Moreover, 1/f noise increases with decreasing temperature. For MOS transistors operating in strong inversion, flicker noise does not

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2.3. NOISE IN CMOS AMPLIFIERS 27

depend on the gate bias, because the surface potential varies very slowly with gate charge. In this case the only way to significantly lower the noise level is to modify the device geometry [39].

2.3 Noise in CMOS Amplifiers

A conventional CMOS amplifier has a typical input referred noise spectrum, as de-picted in Figure2.4. For rather high frequencies, noise can be considered as frequency independent or white. This is usually called ”thermal noise floor”. At low frequencies, the noise power is increasing almost linearly with decreasing frequency and is therefore commonly called 1/f noise. The frequency at which the 1/f noise becomes dominant over the white noise is called corner frequency (fc), in the case of a mos transistor this

frequency corner is calculated equating the thermal and flicker noise, as follows:

fc=

KF

CoxW L

gm 3

8kT (2.8)

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2.4 Mismatch

Mismatch that can be observed between the parameters of a group of equally designed devices is the result of several random processes which occur during every fabrication phase of the devices [8]. It is well known that this phenomenon conformed a per-formance/yield limitation for any design. Mismatch effects become important when critical dimensions and power supply voltages decrease. MOS transistor matching in analog CMOS applications deals with statical differences between pairs of identically designed devices.

The difference ∆VT between the threshold voltages of a pair of MOS transistors

(mis-match) is usually described by its standard deviation as shown in equation 2.9.

σ∆_VT = AVT

√

W L =

qtoxp2N tdepl

0ox

√

W L (2.9)

However a greatly accepted model for mismatch is the Pelgrom’s−Lovett model, with a normal distribution with zero mean and variance dependent on the effective gate-width,

W =Wdrawn−DW, and the effective gate-lenght,L=Ldrawn−DLof the device, given

by equations 2.10 and 2.11.

σ(∆VT) =

AVT

p

(Wdrawn−DW)(Ldrawn−DL)

(2.10)

σ2₍_β₎ β2 =

A2 W

W2

drawnLdrawn

+ A

2 L

WdrawnL2_drawn

+ A

2 β

WdrawnLdrawn

≈ A

2 β

WdrawnLdrawn

(2.11)

The constants AVT, Aβ, AW and AL are technology dependent. In [42] values for

these parameters for a process AMI 0.5 µm are Aβp = 3% µm, Aβn = 2% µm,

AVTp = 14mV µm and AVTn = 20mV µm. The effective layout area is strongly

cor-related to threshold voltage mismatch because of substrate charge has a strong effect on this parameter. The influence of the first two terms on the right hand side of Equation2.11 could not be neglected when short and wide channel devices are used in submicrometer technologies.

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2.4. MISMATCH 29

Accordingly with Pelgrom in [35], the most important contribution to the propor-tionally constant AVT is the uncertainty in the number of active doping atoms in the

depletion layer (N). The statistical variations inN = (N a+N d) determines the match-ing while control in the net value (N a−N d) determines the threshold voltageVT.

The Monte Carlo analysis allows the evaluation of the variation of desired circuit per-formance, and subsequently, yield predictions.

In order to implement analog circuits, matching must be characterized by two indepen-dent statistical values: threshold mismatch ∆V T which may have in practice a mean

standard deviation ranging from 1 to 20 mV, and ∆β/β mismatch which is usually in the range of 0.5 to 5 percent. From [47] is demonstrated that when two transistors have the same gate voltage, as in a current mirror structure, the mismatch of their drain cur-rents is maximum in weak inversion with (if << 1, and thus with the maximumgm/ID

), whereas the minimum current mismatch, is obtained with the transistors operating deep in strong inversion. This can be observed in equation2.12.

∆ID

ID

= ∆β

β −

gm

ID

∆VT (2.12)

On the other hand, for a differential pair, operation of the transistors in weak in-version results in the minimum mismatch between the gate voltages and it is given by equation2.13.

∆VG = ∆VT0− ID

gm

∆β

β (2.13)

As presented before, mismatch of active and passive devices represents a major limita-tion to the accuracy of analog circuits. Single-stage cascoded OTA’s should be preferred to multistage amplifiers. Notice that in strong inversion wheregm/ID is reduced,

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2.4.1 The Speed, Accuracy and Power Tradeoff

As shown earlier in this text, mismatch can be reduced by increasing the transistor’s dimensions, but the speed-accuracy-power tradeoff is seriously affected. As presented in [42], for most of current and voltage processing circuits, this tradeoff only depends of technological and mismatch parameters as in Equation 2.14.

Speed∗Accuracy2

P ower ∝

1

CoxA2VT

(2.14)

2.5 Dynamic Range and Distortion

2.5.1 Distortion

In analog circuits, precision requirements allow small non linearities, which make possi-ble to approximate the input/output characteristic by a Taylor expansion in the range of interest:

y(t) =α1x(t) +α2x2(t) +α3x3(t) +... (2.15)

For small x, y(t)≈α1x, indicating that α1 is the small-signal gain in the vicinity of x

≈0.

The nonlinearity of a circuit can be also characterized by applying a sinusoid at the input and measuring the harmonic content of the output. In that fashion, if x(t) =Acosωt, then:

y(t) = α1Acosωt+ α2A2

2 [1 +cos(2ωt)] +

α3A3

4 [3cosωt+cos(3ωt)]... (2.16)

It can be observed that higher order terms yield higher harmonics. In particular, even and odd order terms result in even and odd harmonics, respectively. Note that the magnitude of the nth harmonic grows roughly in proportion to the nth power of the input amplitude. This effect called ”harmonic distortion” (HD) is usually quantufied by summing the power or all of the harmonics (except that of the fundamental) and normalizing the result to the power of the fundamental. Such a metric is called the

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2.6. QUASI FLOATING GATE (QFG) TECHNIQUE 31

”Total Harmonic Distortion” (THD). As an example for a third order nonlinearity, from 2.17 [5].

T HD = (α2A

2_/₂₎2_{+ (}_α

3A3/4)2

(α1A+ 3α3A3/4)2

(2.17)

Harmonic Distortion is undesirable in most signal processing applications. An impor-tant property that must be remarked is that differential mode circuits which are driven by a differential signal produces no even harmonics, unlike exhibit an odd-symmetric input/output characteristic. For the Taylor expansion of 2.15 to be an odd function, all of the even order terms, α2j must be zero, as presented in equation 2.18 [5].

y(t) =α1x(t) +α3x3(t) +α5x5(t) +... (2.18)

There are different linearization techniques in the literature, as presented in [5], some of them are: switched capacitor (SC) topologies, source degeneration method, operating transistors in triode region, etc.

2.5.2 Dynamic Range

Dynamic Range (DR) is defined as the ratio between the maximum input signal,

Vrms,max driven by electronic devices to ensure a Total Harmonic Distortion (THD)

lower than a specified value to the device’s input referred noise [4], Vin,noise, i.e.

DR= Vrms,max

Vnoise,in

(2.19)

2.6 Quasi Floating Gate (QFG) Technique

A quasi floating gate MOS (QFGMOS), is a FGMOS transistor whose gate is tied to a very large value resistor that weakly connects it to a voltage to establish the operating point. Figure 2.5 represents a 4 input n-channel QFG [43].

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Figure 2.5: Quasi Floating Gate MOS Equivalent Circuit

VF G=

sRleak

1 +sRleakCT0

(Σi = 1NCi·Vi+CGS·VS) +CGD·VD) (2.20)

where all the voltages have been referred to the bulk and C_T0 is the total capacitance seen by the gate of the Quasi-FGMOS. It follows from2.20that the inputs are high-pass filtered with a cutoff frequency which is inversely proportional toRleak. Hence, as long

asRleak is kept high enough, the gate can be effectively floating for very low frequency

values so that the AC operation is unaffected [43].

The total capacitance seen by the QFG is given by eq. 2.21.

CT =CGD +CGS+CGB + N

X

i=1

Ci (2.21)

Since Rleak is implemented using an active device, its parasitic capacitances should

be added to equation 2.21. It is important to remark two drawbacks of the FGMOS compared with MOS transistor: the reduction of the input transconductance and the output resistance, as well as the high input impedance.

2.7 High-Value Tunable Resistor

Since it is unpractical to realize high value passive resistors due to area implications, the need of integrated high-value resistors or Quasi Infinite Resistors (QIRs) is important. They are used in many applications like biasing purposes or for implementing very low frequency filters. In addition to high resistance, the tuning capability of the resistor value of the QIR is an important design issue [49].

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2.7. HIGH-VALUE TUNABLE RESISTOR 33

Different topologies can be found in recent works [11], [49], [50], four of them will be presented along their principal advantages and disadvantages.

Figure 2.6: Basic Structures of Floating QIRs (a) A Cross section view of a PMOS transistor and its associated PN junctions. (b) QIR Electrical model of Figure 2.6(a). (c)Electrical Model of a Low swing QIR. (d) Electrical Model of a moderate swing QIR. (e)Electrical Model of a Large-Swing QIR.

The basic structure of Floating QIRs is presented in Figure 2.6(a), while its electrical realizattion can be appreciated on Figure 2.6(b) which constitute the first one of the four that will be described.

This first of them is implemented with the reverse biased drain-well junction of a PMOS transistor operating in cutoff region withVC =VDD. One of the problems of this

topol-ogy is the limited swing which should be less than 0.3V in order to prevent the forward bias of the junction which generate a resistance reduction. Another problem is the associated with the reverse biased junction formed by the nwell to p-substrate junction which generate a Rleak which is connected to a power rail, and its resistance forms a

voltage divider with the floating junction implementing RG, which produces an

un-wanted and not predictable DC voltage droping in RG. It is important to notice that

the PNP parasitic transistor will be activated if the junction that generateRGbecomes

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The second realization is shown in Figure2.6(c). It consists of a minimum sized PMOS transistor (MP2), biased to work in weak inversion region by the voltage Vcp. Ergo,

RG Rleak should be assured in order to have a negligible voltage drop in RG.

How-ever the main disadvantaged of this model is that RG values must be limited below

VT H0 so that it keeps MP2 in week inversion.

The third realization, shown in Figure 2.6(d), employs two minimums sized PMOS diode connected transistors with the purpose to increase the signal range which will be now restricted by Vswing > VT H.

To improve the voltage swing of the resistor, Figure 2.6(e) presents a series combi-nation of minimum size PMOS and NMOS transistors. Their control voltagesVcn and

Vcp holdMn2 and MP2 in the weak inversion region. That holds the effective resistance

of the series combination very large, typically in the order of Giga−ohms, in spite of large voltage variations in A and B terminals. For the reason that, under dynamic conditions, variations in either the positive or negative direction tends to turn on one transistor meanwhile turn off the other one. Therefore, to avoid the parasitic resistive divider, to operate in weak inversion forcesRGRleak [42].

2.7.1 Tunable Resistor

R

2

One of the implementations previously presented to obtain an electronically programmable linear resistor, R2, is realized using the channel resistance of a MOS transistor (MP1)

biased to operate in triode region. According to [?], a first order approximation of R2 is given by equation2.22 and its circuit implementation is depicted in Figure 2.7.

R2(Vcq) =

1

β(Vcq−VA− |VT p|)

(2.22)

where β = µpCOX(W/L), VT P and VA are the transconductance factor, threshold

voltage and source voltage, respectively. Vcqis the temperature independent bias voltage

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2.7. HIGH-VALUE TUNABLE RESISTOR 35

Ca Ca

Vcq

A B

M p1 M p2

A B

Vcq

Figure 2.7: Circuit Implementation of Tunable R2

transistor MP3 working as a reverse biased pn junction. The disadvantages of this

configuration are the significant distortion presented in triode mode transistors, the body effect and the mobility degradation. A solution for this problem is the so called ”common mode” linearization technique illustrated in figure2.7. The signal component corresponding to the average of the voltages in terminals A and B is added to the gate voltageVG through two small capacitorsCa, and the gate voltage becomes as equation 2.23. It is important to note that DC componentsVA and VB do not affectVG because

of the action of the low-frequency high-pass filterCa−RDS,M p3.

VG =

(VA+VB)

2 +Vcq (2.23)

The low-frequencyhigh−passfilter conformed by Ca−RDS,M P3 preclude the effect of

the DC componentsVA and VB inVG [?]

2.7.2 High Value programmable resistor

R

g

In this case Rg is conformed by the drain-to-source resistance of the transistor MP2.

The use of three transistors in this model presented in Figure 2.8 has the purpose of prevent large distortion components because of large signal fluctuations across nodes A and B. The temperature-independent quiescent voltage Vcf establishes the DC gate

voltage byMP3 and impose subthreshold operation in transistorsMP2, allowing a

(53)

Ca Ca Vcf

A B

Mp1 Mp2 Mp3

Mp4

A B

Vcf

Figure 2.8: Circuit Implementation of Tunable Rg

showed in [?], the conductance of each transistor can be approximate as follows:

GSD =

ISD nUT     n

(1−exp(−VSD

UT )) −1     (2.24)

GSD0 = (GSD |V SD=0)

I0 UT exp

(VS)−Vcf

nUT

(2.25)

where I0 = 2nP µCox(W/L)UT2exp(− | VT0/nUT |), Cox is the gate oxide capacitance

per unit area, nP the carrier concentration, µ the carrier mobility, UT = kT /q the

thermal voltage, n the slope factor andVT0 the threshold voltage. The Vcf dependence

of GSD0 allows the tuning of Rg.

2.8 Folded Cascode Operational Amplifier (FCC)

A Differential Amplifier is one of the most versatile circuits in analog circuit design. It serves as the input stage to most op amps.

The cascode amplifier has two distinct characteristics, it provides a high output impedance and reduces the effect of the Miller capacitance on the input of the amplifier [44]. In Figure2.9is shown the circuit topology of a FCC op amp, and then the transfer function is given by equation2.26, while its frequency response is determined by equation2.30.

V out V in =

2 +K

2 + 2K

gm2Rout (2.26)

(54)

2.8. FOLDED CASCODE OPERATIONAL AMPLIFIER (FCC) 37

Figure 2.9: Folded Cascode Op Amp Topology

Rout =RII||[gm5rds5(rds3||rds1)] (2.27) K = RII(gds1+gds3)

gm7rds5

(2.28)

RII =gm9rds9rds7 (2.29)

Pout =

−1

RoutCout

(2.30)

The second dominant pole is given by transistorM6 as can be appreciated on equation

2.31. Therefore,M6 must be sized in order to obtain the second pole from three to five

times in frequency far from the dominant pole.

PM6 =

−(gm6rds6gm4) C6

(2.31)

From the Noise analysis of the folded cascode operational amplifier performed by [46], is set that to decrease thermal noise S1 must be made large or I1 must be increasing,

(55)

and consequently 2µnS3 < µpS1, and S7 < S1. It would be easier to get lower thermal

noise if the amp used NMOS input devices, since µn > µp. Some Cascode devices do

not contribute with 1/f noise, W1, L3 and L7 are independent parameters. Therefore

increasing any of these parameters will decrease 1/f noise. AfterL3 andL7 are choosen

for best thermal noise, thenL1 is found by the optimization relation.

In equation2.32 is presented the 1/f noise equation for an FCC Op Amp.

V2 ni=

KFp∆f

µpCox2 W1L1f

"

1 + 2KFn

KFp L1 L3 2 + L1 L7 2# (2.32)

Input devices length is a dependent parameter, therefore can be optimized with equation 2.34.

∂V2 ni

∂L1

= 0 (2.33)

1

L2 1

= 2KFn

KFp 1 L2 3 + 1 L2 7 (2.34)

In the case of thermal noise, it is set by equation2.35.

Vni2 = 4kBT Rn∆f (2.35)

where,

Rn =

4 3gm1

1 +η1+ gm3 gm1

(1 +η3) + gm7 gm1

(1 +η7)

(2.36)

and:

Rn= 4

3p

2µpCoxS1I1

"

1 +η1+

s

2µnS3 µpS1

(1 +η3) +

r

S7 S1

(1 +η7)

#

(2.37)

Input Offset Voltage in FC Opamp has the same form as the variance of the 1/f noise voltage. Therefore W2 and L4 are independent parameters, so increasing either will

decrease input referred offset. AfterL4 is chosen, then L2 is found by the optimization

relation presenter in equation 2.39

∂V_os2 ∂L2

= 0 (2.38)

L2 =

s

µp

µn

AV t,p

AV t,n

A high dynamic range-CMRR and tunable bandwidth front-end amplifier for biomedical applications

Tunable Bandwidth Front-End

Amplifier for Biomedical Applications

Contents

List of Figures

List of Tables

Chapter 1

Introduction

1.1

Analog preprocessing of biomedical signals

1.2

Preamplifiers Specifications and involved non

ideal effects

1.2.1

Noise Effects

1.2.2

Offset Effects

1.2.3

Offset Stabilization Techniques

1.3

State-of-the-Art

Reference

CMRR

Offset

Noise

[

2

]

82db @50Hz

20mV

0.8

µ

Vrms(0.5-100Hz)

[

25

]

58db

-

4.43

µ

Vrms(1Hz-12KHz)

[

17

]

-

-

5.1

µ

Vrms

[

18

]

139

-

3.9

µ

Vrms(10Hz-10KHz)

[

19

]

-

-

5.8

µ

Vrms

[

20

]

120dB

±

50mV

57

nV /

√

Hz

[

23

]

-

-