https://infocenter.nordicsemi.com/pdf/nRF52840_PS_v1.1.pdf

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nRF52840

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Feature list

Features:

• Bluetooth® 5, IEEE 802.15.4-2006, 2.4 GHz transceiver • -95 dBm sensitivity in 1 Mbps Bluetooth® low energy mode

• -103 dBm sensitivity in 125 kbps Bluetooth® low energy mode (long range) • -20 to +8 dBm TX power, configurable in 4 dB steps

• On-air compatible with nRF52, nRF51, nRF24L, and nRF24AP Series

• Supported data rates:

• Bluetooth® 5: 2 Mbps, 1 Mbps, 500 kbps, and 125 kbps • IEEE 802.15.4-2006: 250 kbps

• Proprietary 2.4 GHz: 2 Mbps, 1 Mbps

• Single-ended antenna output (on-chip balun)

• 128-bit AES/ECB/CCM/AAR co-processor (on-the-fly packet encryption) • 4.8 mA peak current in TX (0 dBm)

• 4.6 mA peak current in RX

• RSSI (1 dB resolution)

• ARM® Cortex®-M4 32-bit processor with FPU, 64 MHz

• 212 EEMBC CoreMark score running from flash memory

• 52 µA/MHz running CoreMark from flash memory

• Watchpoint and trace debug modules (DWT, ETM, and ITM)

• Serial wire debug (SWD) • Rich set of security features

• ARM® TrustZone® Cryptocell 310 security subsystem

• NIST SP800-90A and SP800-90B compliant random number generator

• AES-128: ECB, CBC, CMAC/CBC-MAC, CTR, CCM/CCM*

• Chacha20/Poly1305 AEAD supporting 128- and 256-bit key size • SHA-1, SHA-2 up to 256 bits

• Keyed-hash message authentication code (HMAC)

• RSA up to 2048-bit key size

• SRP up to 3072-bit key size

• ECC support for most used curves, among others P-256 (secp256r1) and Ed25519/Curve25519

• Application key management using derived key model • Secure boot ready

• Flash access control list (ACL)

• Root-of-trust (RoT)

• Debug control and configuration • Access port protection (CTRL-AP)

• Secure erase

• Flexible power management

• 1.7 V to 5.5 V supply voltage range

• On-chip DC/DC and LDO regulators with automated low current modes

• 1.8 V to 3.3 V regulated supply for external components

• Automated peripheral power management • Fast wake-up using 64 MHz internal oscillator

• 0.4 µA at 3 V in System OFF mode, no RAM retention

• 1.5 µA at 3 V in System ON mode, no RAM retention, wake on RTC

• 1 MB flash and 256 kB RAM

• Advanced on-chip interfaces

• USB 2.0 full speed (12 Mbps) controller • QSPI 32 MHz interface

• High-speed 32 MHz SPI

• Type 2 near field communication (NFC-A) tag with wake-on field

• Touch-to-pair support

• Programmable peripheral interconnect (PPI)

• 48 general purpose I/O pins

• EasyDMA automated data transfer between memory and peripherals

• Nordic SoftDevice ready with support for concurrent multi-protocol

• 12-bit, 200 ksps ADC - 8 configurable channels with programmable gain

• 64 level comparator

• 15 level low-power comparator with wake-up from System OFF mode

• Temperature sensor

• 4x 4-channel pulse width modulator (PWM) unit with EasyDMA

• Audio peripherals: I2S, digital microphone interface (PDM) • 5x 32-bit timer with counter mode

• Up to 4x SPI master/3x SPI slave with EasyDMA

• Up to 2x I2C compatible 2-wire master/slave

• 2x UART (CTS/RTS) with EasyDMA • Quadrature decoder (QDEC)

• 3x real-time counter (RTC)

• Single crystal operation

• Package variants

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Feature list

Applications:

• Advanced computer peripherals and I/O devices

• Mouse

• Keyboard

• Multi-touch trackpad

• Advanced wearables

• Health/fitness sensor and monitor devices

• Wireless payment enabled devices

• Internet of things (IoT)

• Smart home sensors and controllers

• Industrial IoT sensors and controllers

• Interactive entertainment devices

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Feature list

. . .

ii

1 Revision history

. . .

12

2 About this document

. . .

14

2.1 Document naming and status . . . 14

2.2 Peripheral naming and abbreviations . . . 14

2.3 Register tables . . . 15

2.3.1 Fields and values . . . 15

2.4 Registers . . . 15

2.4.1 DUMMY . . . 15

3 Block diagram

. . .

17

4 Core components

. . .

19

4.1 CPU . . . 19

4.1.1 Floating point interrupt . . . 19

4.1.2 CPU and support module configuration . . . 19

4.1.3 Electrical specification . . . 20

4.2 Memory . . . 20

4.2.1 RAM - Random access memory . . . 21

4.2.2 Flash - Non-volatile memory . . . 21

4.2.3 Memory map . . . 21

4.2.4 Instantiation . . . 23

4.3 NVMC — Non-volatile memory controller . . . 24

4.3.1 Writing to flash . . . 24

4.3.2 Erasing a page in flash . . . 25

4.3.3 Writing to user information configuration registers (UICR) . . . 25

4.3.4 Erasing user information configuration registers (UICR) . . . 25

4.3.5 Erase all . . . 25

4.3.6 Access port protection behavior . . . 25

4.3.7 Partial erase of a page in flash . . . 25

4.3.8 Cache . . . 26

4.3.9 Registers . . . 26

4.4 FICR — Factory information configuration registers . . . 31

4.4.1 Registers . . . 31

4.5 UICR — User information configuration registers . . . 42

4.5.1 Registers . . . 43

4.6 EasyDMA . . . 46

4.6.1 EasyDMA error handling . . . 48

4.6.2 EasyDMA array list . . . 48

4.7 AHB multilayer . . . 49

4.8 Debug and trace . . . 50

4.8.1 DAP - Debug access port . . . 51

4.8.2 CTRL-AP - Control access port . . . 51

4.8.3 Debug interface mode . . . 53

4.8.4 Real-time debug . . . 54

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5 Power and clock management

. . .

55

5.1 Power management unit (PMU) . . . 55

5.2 Current consumption . . . 55

5.3 POWER — Power supply . . . 61

5.3.1 Main supply . . . 61

5.3.2 USB supply . . . 66

5.3.3 System OFF mode . . . 67

5.3.4 System ON mode . . . 68

5.3.5 RAM power control . . . 68

5.3.6 Reset . . . 69

5.3.7 Registers . . . 70

5.4 CLOCK — Clock control . . . 82

5.4.1 HFCLK controller . . . 83

5.4.2 LFCLK controller . . . 84

5.4.3 Registers . . . 87

6 Peripherals

. . .

99

6.1 Peripheral interface . . . 99

6.1.1 Peripheral ID . . . 99

6.1.2 Peripherals with shared ID . . . 100

6.1.3 Peripheral registers . . . 100

6.1.4 Bit set and clear . . . 100

6.1.5 Tasks . . . 100

6.1.6 Events . . . 100

6.1.7 Shortcuts . . . 101

6.1.8 Interrupts . . . 101

6.2 AAR — Accelerated address resolver . . . 102

6.2.1 EasyDMA . . . 102

6.2.2 Resolving a resolvable address . . . 102

6.2.3 Use case example for chaining RADIO packet reception with address resolution using AAR . 103 6.2.4 IRK data structure . . . 103

6.2.5 Registers . . . 103

6.3 ACL — Access control lists . . . 107

6.3.1 Registers . . . 109

6.4 CCM — AES CCM mode encryption . . . 111

6.4.1 Key-steam generation . . . 111

6.4.2 Encryption . . . 112

6.4.3 Decryption . . . 112

6.4.4 AES CCM and RADIO concurrent operation . . . 113

6.4.5 Encrypting packets on-the-fly in radio transmit mode . . . 113

6.4.6 Decrypting packets on-the-fly in radio receive mode . . . 114

6.4.7 CCM data structure . . . 115

6.4.8 EasyDMA and ERROR event . . . 116

6.4.9 Registers . . . 116

6.5 COMP — Comparator . . . 123

6.5.1 Differential mode . . . 124

6.5.2 Single-ended mode . . . 125

6.5.3 Registers . . . 127

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6.6.2 Always-on (AO) power domain . . . 136

6.6.3 Lifecycle state (LCS) . . . 136

6.6.4 Cryptographic key selection . . . 137

6.6.5 Direct memory access (DMA) . . . 137

6.6.6 Standards . . . 138

6.6.7 Registers . . . 138

6.6.8 Host interface . . . 139

6.7 ECB — AES electronic codebook mode encryption . . . 142

6.7.1 Shared resources . . . 142

6.7.2 EasyDMA . . . 142

6.7.3 ECB data structure . . . 142

6.7.4 Registers . . . 143

6.8 EGU — Event generator unit . . . 146

6.8.1 Registers . . . 146

6.9 GPIO — General purpose input/output . . . 148

6.9.1 Pin configuration . . . 149

6.9.2 Registers . . . 151

6.10 GPIOTE — GPIO tasks and events . . . 157

6.10.1 Pin events and tasks . . . 157

6.10.2 Port event . . . 158

6.10.3 Tasks and events pin configuration . . . 158

6.10.4 Registers . . . 159

6.11 I2S — Inter-IC sound interface . . . 163

6.11.1 Mode . . . 164

6.11.2 Transmitting and receiving . . . 164

6.11.3 Left right clock (LRCK) . . . 165

6.11.4 Serial clock (SCK) . . . 165

6.11.5 Master clock (MCK) . . . 166

6.11.6 Width, alignment and format . . . 166

6.11.7 EasyDMA . . . 168

6.11.8 Module operation . . . 170

6.11.10 Registers . . . 173

6.12 LPCOMP — Low power comparator . . . 183

6.12.3 Registers . . . 185

6.13 MWU — Memory watch unit . . . 191

6.13.1 Registers . . . 192

6.14 NFCT — Near field communication tag . . . 205

6.14.1 Overview . . . 206

6.14.2 Operating states . . . 208

6.14.4 EasyDMA . . . 209

6.14.5 Frame assembler . . . 210

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6.14.7 Frame timing controller . . . 212

6.14.8 Collision resolution . . . 213

6.14.9 Antenna interface . . . 214

6.14.10 NFCT antenna recommendations . . . 214

6.14.11 Battery protection . . . 215

6.14.12 References . . . 215

6.14.13 Registers . . . 215

6.15 PDM — Pulse density modulation interface . . . 234

6.15.1 Master clock generator . . . 235

6.15.2 Module operation . . . 235

6.15.3 Decimation filter . . . 235

6.15.4 EasyDMA . . . 236

6.15.5 Hardware example . . . 237

6.15.7 Registers . . . 238

6.16 PPI — Programmable peripheral interconnect . . . 245

6.16.1 Pre-programmed channels . . . 246

6.16.2 Registers . . . 247

6.17 PWM — Pulse width modulation . . . 251

6.17.1 Wave counter . . . 252

6.17.2 Decoder with EasyDMA . . . 255

6.17.3 Limitations . . . 262

6.17.5 Registers . . . 263

6.18 QDEC — Quadrature decoder . . . 271

6.18.1 Sampling and decoding . . . 272

6.18.2 LED output . . . 273

6.18.3 Debounce filters . . . 273

6.18.4 Accumulators . . . 274

6.18.5 Output/input pins . . . 274

6.18.7 Registers . . . 275

6.19 QSPI — Quad serial peripheral interface . . . 286

6.19.1 Configuring peripheral . . . 287

6.19.2 Write operation . . . 287

6.19.3 Read operation . . . 288

6.19.4 Erase operation . . . 288

6.19.5 Execute in place . . . 288

6.19.6 Sending custom instructions . . . 288

6.19.7 Deep power-down mode . . . 289

6.19.8 Instruction set . . . 290

6.19.9 Interface description . . . 290

6.19.10 Registers . . . 295

6.20 RADIO — 2.4 GHz radio . . . 307

6.20.1 Packet configuration . . . 308

6.20.2 Address configuration . . . 309

6.20.3 Data whitening . . . 310

6.20.4 CRC . . . 310

6.20.5 Radio states . . . 311

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6.20.9 Interframe spacing . . . 314

6.20.10 Device address match . . . 315

6.20.11 Bit counter . . . 316

6.20.12 IEEE 802.15.4 operation . . . 316

6.20.13 EasyDMA . . . 324

6.20.14 Registers . . . 325

6.21 RNG — Random number generator . . . 359

6.21.1 Bias correction . . . 360

6.21.2 Speed . . . 360

6.21.3 Registers . . . 360

6.22 RTC — Real-time counter . . . 363

6.22.1 Clock source . . . 363

6.22.2 Resolution versus overflow and the PRESCALER . . . 363

6.22.3 COUNTER register . . . 364

6.22.4 Overflow features . . . 365

6.22.5 TICK event . . . 365

6.22.6 Event control feature . . . 365

6.22.7 Compare feature . . . 366

6.22.8 TASK and EVENT jitter/delay . . . 368

6.22.9 Reading the COUNTER register . . . 370

6.22.10 Registers . . . 371

6.23 SAADC — Successive approximation analog-to-digital converter . . . 376

6.23.1 Input configuration . . . 377

6.23.2 Reference voltage and gain settings . . . 379

6.23.3 Digital output . . . 379

6.23.4 EasyDMA . . . 379

6.23.5 Continuous sampling . . . 381

6.23.6 Oversampling . . . 381

6.23.7 Event monitoring using limits . . . 381

6.23.8 Calibration . . . 382

6.23.9 Registers . . . 382

6.24 SPI — Serial peripheral interface master . . . 398

6.24.1 Functional description . . . 398

6.24.2 Registers . . . 401

6.25 SPIM — Serial peripheral interface master with EasyDMA . . . 406

6.25.1 SPI master transaction sequence . . . 407

6.25.2 D/CX functionality . . . 408

6.25.4 EasyDMA . . . 409

6.25.5 Low power . . . 410

6.25.6 Registers . . . 410

6.26 SPIS — Serial peripheral interface slave with EasyDMA . . . 422

6.26.2 EasyDMA . . . 423

6.26.3 SPI slave operation . . . 424

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6.26.5 Registers . . . 426

6.27 SWI — Software interrupts . . . 439

6.27.1 Registers . . . 439

6.28 TEMP — Temperature sensor . . . 439

6.28.1 Registers . . . 440

6.29 TWI — I2C compatible two-wire interface . . . 446

6.29.2 Master mode pin configuration . . . 447

6.29.4 Master write sequence . . . 448

6.29.5 Master read sequence . . . 448

6.29.6 Master repeated start sequence . . . 449

6.29.7 Low power . . . 450

6.29.8 Registers . . . 450

6.30 TIMER — Timer/counter . . . 459

6.30.1 Capture . . . 460

6.30.2 Compare . . . 460

6.30.3 Task delays . . . 460

6.30.4 Task priority . . . 460

6.30.5 Registers . . . 461

6.31 TWIM — I2C compatible two-wire interface master with EasyDMA . . . 465

6.31.1 EasyDMA . . . 466

6.31.2 Master write sequence . . . 467

6.31.3 Master read sequence . . . 468

6.31.5 Low power . . . 470

6.31.6 Master mode pin configuration . . . 470

6.31.7 Registers . . . 470

6.31.9 Pullup resistor . . . 482

6.32 TWIS — I2C compatible two-wire interface slave with EasyDMA . . . 482

6.32.1 EasyDMA . . . 485

6.32.2 TWI slave responding to a read command . . . 485

6.32.3 TWI slave responding to a write command . . . 486

6.32.5 Terminating an ongoing TWI transaction . . . 488

6.32.6 Low power . . . 488

6.32.7 Slave mode pin configuration . . . 488

6.32.8 Registers . . . 489

6.33 UART — Universal asynchronous receiver/transmitter . . . 499

6.33.4 Transmission . . . 501

6.33.5 Reception . . . 501

6.33.6 Suspending the UART . . . 502

6.33.7 Error conditions . . . 502

6.33.8 Using the UART without flow control . . . 502

6.33.9 Parity and stop bit configuration . . . 503

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6.34.1 EasyDMA . . . 513

6.34.2 Transmission . . . 513

6.34.3 Reception . . . 514

6.34.4 Error conditions . . . 515

6.34.5 Using the UARTE without flow control . . . 515

6.34.6 Parity and stop bit configuration . . . 516

6.34.7 Low power . . . 516

6.34.9 Registers . . . 516

6.35 USBD — Universal serial bus device . . . 529

6.35.1 USB device states . . . 530

6.35.2 USB terminology . . . 531

6.35.3 USB pins . . . 532

6.35.4 USBD power-up sequence . . . 532

6.35.5 USB pull-up . . . 533

6.35.6 USB reset . . . 533

6.35.7 USB suspend and resume . . . 534

6.35.8 EasyDMA . . . 535

6.35.9 Control transfers . . . 536

6.35.10 Bulk and interrupt transactions . . . 539

6.35.11 Isochronous transactions . . . 542

6.35.12 USB register access limitations . . . 544

6.35.13 Registers . . . 545

6.36 WDT — Watchdog timer . . . 570

6.36.1 Reload criteria . . . 570

6.36.2 Temporarily pausing the watchdog . . . 570

6.36.3 Watchdog reset . . . 570

6.36.4 Registers . . . 571

7 Hardware and layout

. . .

575

7.1 Pin assignments . . . 575

7.1.1 aQFN73 ball assignments . . . 575

7.1.2 WLCSP ball assignments . . . 578

7.2 Mechanical specifications . . . 581

7.2.1 aQFN73 7 x 7 mm package . . . 581

7.2.2 WLCSP 3.544 x 3.607 mm package . . . 582

7.3 Reference circuitry . . . 583

7.3.1 Circuit configuration no. 1 . . . 584

7.3.7 Circuit configuration no. 1 for CKAA WLCSP . . . 596

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7.3.13 PCB guidelines . . . 608

7.3.14 PCB layout example . . . 609

8 Recommended operating conditions

. . .

611

9 Absolute maximum ratings

. . .

612

10 Ordering information

. . .

613

10.1 Package marking . . . 613

10.2 Box labels . . . 613

10.3 Order code . . . 614

10.4 Code ranges and values . . . 615

10.5 Product options . . . 616

11 Legal notices

. . .

618

11.1 Liability disclaimer . . . 618

11.2 Life support applications . . . 618

11.3 RoHS and REACH statement . . . 618

11.4 Trademarks . . . 618

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1

Revision history

Date Version Description

February 2019 1.1 _{The following content has been added or updated:}

• Added information for the WLCSP package variant in Pin

assignments on page 575, Mechanical specifications on

page 581, Reference circuitry on page 583, FICR —

Factory information configuration registers on page 31,

Absolute maximum ratings on page 612, and Ordering information on page 613.

• Reference circuitry on page 583: Updated RF-Match in

aQFN™73 reference circuitry for all configurations. Added

optional 4.7 Ω resistor to USB supply.

• UICR — User information configuration registers on page 42: Removed NRFFW[13] and NRFFW[14] registers.

• CPU on page 19: Corrected value of parameter

CMFLASH/mA.

• POWER — Power supply on page 61: Clarified range of voltages in both Normal and High voltage modes. • CLOCK — Clock control on page 82: Corrected value of

parameter PD_LFXO to a less restrictive value.

• EasyDMA on page 46: Added section about EasyDMA error handling. Corrected example code in section EasyDMA array list.

• NVMC — Non-volatile memory controller on page 24: Added note about the necessity to halt the CPU before isuing NVMC commands from the debugger.

• ACL — Access control lists on page 107: Corrected register access to ReadWriteOnce (RWO) for some registers.

• I2S — Inter-IC sound interface on page 163: Removed

invalid values from register MCKFREQ, see parameter fMCK.

Fixed figure for Memory mapping for 8-bit stereo. • SAADC — Successive approximation analog-to-digital

converter on page 376: Corrected description of functionality of SAMPLE task.

• SPIS — Serial peripheral interface slave with EasyDMA

on page 422: Exposed the LIST register. Corrected SPI modes table.

• TWIS — I2C compatible two-wire interface slave with EasyDMA on page 482: Exposed the LIST register. • UART — Universal asynchronous receiver/transmitter on

page 499: Added STOP bit configuration description. • RADIO — 2.4 GHz radio on page 307: Added equations

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Revision history

Date Version Description

radio timing parameters to the electrical specifications. Added sensitivity parameter for 2 Mbit NRF mode. • USBD — Universal serial bus device on page 529:

Pointed that isochronous transfers have to be finished before the next SOF event, or the result of the transfer is undefined.

• Legal notices on page 618: Updated text and image.

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2

About this document

This product specification is organized into chapters based on the modules and peripherals that are available in this IC.

The peripheral descriptions are divided into separate sections that include the following information: • A detailed functional description of the peripheral

• Register configuration for the peripheral

• Electrical specification tables, containing performance data which apply for the operating conditions

described in Recommended operating conditions on page 611.

2.1 Document naming and status

Nordic uses three distinct names for this document, which are reflecting the maturity and the status of the document and its content.

Document name Description

Objective Product Specification (OPS) _{Applies to document versions up to 0.7.}

This product specification contains target specifications for product development.

Preliminary Product Specification (PPS) _{Applies to document versions 0.7 and up to 1.0.}

This product specification contains preliminary data. Supplementary data may be published from Nordic Semiconductor ASA later.

Product Specification (PS) _{Applies to document versions 1.0 and higher.}

This product specification contains final product specifications. Nordic Semiconductor ASA reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.

Table 1: Defined document names

2.2 Peripheral naming and abbreviations

Every peripheral has a unique capitalized name or an abbreviation of its name, e.g. TIMER, used for identification and reference. This name is used in chapter headings and references, and it will appear in

the ARM® Cortex® Microcontroller Software Interface Standard (CMSIS) hardware abstraction layer to

identify the peripheral.

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About this document

2.3 Register tables

Individual registers are described using register tables. These tables are built up of two sections. The first three colored rows describe the position and size of the different fields in the register. The following rows describe the fields in more detail.

2.3.1 Fields and values

The Id (Field Id) row specifies the bits that belong to the different fields in the register. If a field has

enumerated values, then every value will be identified with a unique value id in the Value Id column.

A blank space means that the field is reserved and read as undefined, and it also must be written as 0

to secure forward compatibility. If a register is divided into more than one field, a unique field name is

specified for each field in the Field column. The Value Id may be omitted in the single-bit bit fields when

values can be substituted with a Boolean type enumerator range, e.g. true/false, disable(d)/enable(d), on/ off, and so on.

Values are usually provided as decimal or hexadecimal. Hexadecimal values have a 0x prefix, decimal

values have no prefix.

The Value column can be populated in the following ways: • Individual enumerated values, for example 1, 3, 9.

• Range of values, e.g. [0..4], indicating all values from and including 0 and 4.

• Implicit values. If no values are indicated in the Value column, all bit combinations are supported, or

alternatively the field's translation and limitations are described in the text instead.

If two or more fields are closely related, the Value Id, Value, and Description may be omitted for all but

the first field. Subsequent fields will indicate inheritance with '..'.

A feature marked Deprecated should not be used for new designs.

2.4 Registers

Register Offset Description

DUMMY 0x514 Example of a register controlling a dummy feature

Table 2: Register overview

2.4.1 DUMMY

Address offset: 0x514

Example of a register controlling a dummy feature

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ID D D D D C C C B A A

Reset 0x00050002 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 ID AccessField Value ID Value Description

A RW FIELD_A Example of a field with several enumerated values

Disabled 0 The example feature is disabled

NormalMode 1 The example feature is enabled in normal mode

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Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ID D D D D C C C B A A

B RW FIELD_B Example of a deprecated field Deprecated

Disabled 0 The override feature is disabled

Enabled 1 The override feature is enabled

C RW FIELD_C Example of a field with a valid range of values

ValidRange [2..7] Example of allowed values for this field

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3

Block diagram

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nRF52840

AP

B0

AHB TO APB BRIDGE RADIO CPU ARM CORTEX-M4 AHB-AP RNG TEMP WDT NVMC ANT POWER nRESET RTC [0..2] PPI TIMER [0..4] NVIC UICR FICR SW-DP CODE EasyDMA master QDEC SAADC GPIOTE

P0.0 – P0.31 P1.0 – P1.15

AIN0 – AIN7

LED A B

UARTE [0..1]

SPIS [0..2] _MOSIMISO CSN COMP EasyDMA RXD TXDCTS RTS ETM SysTick TPIU TP EasyDMA LPCOMP EasyDMA master master NFCT NFC1 NFC2 EasyDMA master master SWDIO SWCLK CTRL-AP PWM [0..3] OUT0 – OUT3

I2S MCK LRCK SCL SDOUT SDIN PDM CLK DIN SCK EasyDMA master EasyDMA master EasyDMA master I-Cache sla ve sla ve sla ve sla ve sla ve m as te r CLOCK XL2 XL1 XC2 XC1 USBD D-D+ EasyDMA master VBUS SPIM [0..3] SCK MISO EasyDMA MOSI master

TWIM [0..1] _SDASCL

EasyDMA master

QSPI _IO3IO2

IO1 IO0 EasyDMA master CSN SCK ECB EasyDMA master CCM EasyDMA master AAR EasyDMA master CryptoCell DMA master

TWIS [0..1] _SDASCL

EasyDMA master RAM0 sla ve RAM1 sla ve RAM2 sla ve RAM3 sla ve RAM4 sla ve RAM5 sla ve RAM6 sla ve RAM7 sla ve GPIO sla ve RAM8 sla ve AHB multilayer

P0.0 – P0.31 P1.0 – P1.15

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4

Core components

4.1 CPU

The ARM® Cortex-M4 processor with floating-point unit (FPU) has a 32-bit instruction set (Thumb®-2

technology) that implements a superset of 16- and 32-bit instructions to maximize code density and performance.

This processor implements several features that enable energy-efficient arithmetic and high-performance signal processing, including:

• Digital signal processing (DSP) instructions

• Single-cycle multiply and accumulate (MAC) instructions • Hardware divide

• 8- and 16-bit single instruction multiple data (SIMD) instructions • Single-precision floating-point unit (FPU)

The ARM® Cortex® Microcontroller Software Interface Standard (CMSIS) hardware abstraction layer for the

ARM®Cortex® processor series is implemented and available for the M4 CPU.

Real-time execution is highly deterministic in thread mode, to and from sleep modes, and when handling events at configurable priority levels via the nested vectored interrupt controller (NVIC).

Executing code from flash will have a wait state penalty on the nRF52 series. An instruction cache can be enabled to minimize flash wait states when fetching instructions. For more information on cache, see Cache on page 26. The section Electrical specification on page 20 shows CPU performance

parameters including wait states in different modes, CPU current and efficiency, and processing power and

efficiency based on the CoreMark® benchmark.

The ARM system timer (SysTick) is present on nRF52840. The SysTick's clock will only tick when the CPU is running or when the system is in debug interface mode.

4.1.1 Floating point interrupt

The floating point unit (FPU) may generate exceptions when used due to e.g. overflow or underflow, which in turn will trigger the FPU interrupt.

See Instantiation on page 23 for more information about the exceptions triggering the FPU interrupt. To clear the IRQ (interrupt request) line when an exception has occurred, the relevant exception bit within the floating-point status and control register (FPSCR) needs to be cleared. For more information about the

FPSCR or other FPU registers, see Cortex-M4 Devices Generic User Guide.

4.1.2 CPU and support module configuration

The ARM® Cortex®-M4 processor has a number of CPU options and support modules implemented on the

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Option / Module Description Implemented

Core options

NVIC Nested vector interrupt controller 48 vectors

PRIORITIES Priority bits 3

WIC Wakeup interrupt controller NO

Endianness Memory system endianness Little endian

Bit-banding Bit banded memory NO

DWT Data watchpoint and trace YES

SysTick System tick timer YES

Modules

MPU Memory protection unit YES

FPU Floating-point unit YES

DAP Debug access port YES

ETM Embedded trace macrocell YES

ITM Instrumentation trace macrocell YES

TPIU Trace port interface unit YES

ETB Embedded trace buffer NO

FPB Flash patch and breakpoint unit YES

HTM AMBA™ AHB trace macrocell NO

4.1.3 Electrical specification

4.1.3.1 CPU performance

The CPU clock speed is 64 MHz. Current and efficiency data is taken when in System ON and the CPU is

executing the CoreMark™ benchmark. It includes power regulator and clock base currents. All other blocks

are IDLE.

Symbol Description Min. Typ. Max. Units

WFLASH CPU wait states, running CoreMark from flash, cache

disabled

2

WFLASHCACHE CPU wait states, running CoreMark from flash, cache

enabled

3

WRAM CPU wait states, running CoreMark from RAM 0

CMFLASH CoreMark, running CoreMark from flash, cache enabled 212 CoreMark

CMFLASH/MHz CoreMark per MHz, running CoreMark from flash, cache

enabled

3.3 CoreMark/

MHz CMFLASH/mA CoreMark per mA, running CoreMark from flash, cache

enabled, DCDC 3V

64 CoreMark/

mA

4.2 Memory

The nRF52840 contains 1 MB of flash and 256 kB of RAM that can be used for code and data storage. The CPU and peripherals with EasyDMA can access memory via the AHB multilayer interconnect.

The CPU is also able to access peripherals via the AHB multilayer interconnect, as illustrated in Memory

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Core components RAM3 AHB slave RAM2 AHB slave RAM1 AHB slave RAM0 AHB slave RAM7 AHB slave RAM6 AHB slave RAM5 AHB slave RAM4 AHB slave

AHB multilayer interconnect A

H B sl av e Page 0 Page 1 Page 2 Page 3..254 Page 255 0x0000 0000 0x0000 2000 0x0000 3000 0x000F F000 Flash ICODE/DCODE A H B sl av e N V M C ICODE DCODE Peripheral EasyDMA D M A b us Peripheral EasyDMA D M A b us CPU ARM Cortex-M4 S ys te m b us IC O D E D C O D E AHB2APB AHB APB 0x0000 1000 I-C ac he 0x2000 0000 0x2000 1000 0x2000 2000 0x2000 3000 0x2000 4000 0x2000 5000 0x2000 6000 0x2000 7000 Section 0 Section 1 Section 0 Section 1 Section 0 Section 1 Section 0 Section 1 0x2000 8000 0x2000 9000 0x2000 A000 0x2000 B000 0x2000 C000 0x2000 D000 0x2000 E000 0x2000 F000 Section 0 Section 1 Section 0 Section 1 Section 0 Section 1 Section 0 Section 1

Data RAM_System

0x0080 0000 0x0080 1000 0x0080 2000 0x0080 3000 0x0080 4000 0x0080 5000 0x0080 6000 0x0080 7000 0x0080 8000 0x0080 9000 0x0080 A000 0x0080 B000 0x0080 C000 0x0080 D000 0x0080 E000 0x0080 F000 Code RAM

ICODE / DCODE

Section 0 Section 1 Section 2 Section 3 Section 4 Section 5

0x2001 0000 0x0081 0000 0x2001 8000 0x0081 8000 0x2002 0000 0x0082 0000 0x2002 8000 0x0082 8000 0x2003 0000 0x0083 0000 0x2003 8000 0x0083 8000

RAM8 AHB slave

Figure 2: Memory layout

See AHB multilayer on page 49 and EasyDMA on page 46 for more information about the AHB multilayer interconnect and the EasyDMA.

The same physical RAM is mapped to both the Data RAM region and the Code RAM region. It is up to the application to partition the RAM within these regions so that one does not corrupt the other.

4.2.1 RAM - Random access memory

The RAM interface is divided into 9 RAM AHB slaves.

RAM AHB slave 0-7 is connected to 2x4 kB RAM sections each and RAM AHB slave 8 is connected to 6x32

kB sections, as shown in Memory layout on page 21.

Each of the RAM sections have separate power control for System ON and System OFF mode operation,

which is configured via RAM register (see the POWER — Power supply on page 61).

4.2.2 Flash - Non-volatile memory

The flash can be read an unlimited number of times by the CPU, but it has restrictions on the number of times it can be written and erased and also on how it can be written.

Writing to flash is managed by the non-volatile memory controller (NVMC), see NVMC — Non-volatile

memory controller on page 24.

The flash is divided into 256 pages of 4 kB each that can be accessed by the CPU via both the ICODE and

DCODE buses as shown in Memory layout on page 21.

4.2.3 Memory map

The complete memory map for the nRF52840 is shown in Memory map on page 22. As described in

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Device

RAM

Peripheral

SRAM

Code

Private peripheral bus

AHB peripherals

APB peripherals

UICR

FICR

Data RAM

Code RAM

Flash

0xFFFFFFFF

0x00000000

0x20000000

0x40000000

0x60000000

0x80000000

0xA0000000

0xC0000000

0xE0000000

0x00000000

0x10000000

0x40000000

0x50000000

0xE0000000

0x00800000

0x10001000

0x20000000

XIP

_0x12000000

0x19FFFFFF

System address map

Address map

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Core components

4.2.4 Instantiation

ID Base address Peripheral Instance Description

0 0x40000000 CLOCK CLOCK Clock control

0 0x40000000 POWER POWER Power control

0 0x50000000 GPIO GPIO General purpose input and output Deprecated

0 0x50000000 GPIO P0 General purpose input and output, port 0

0 0x50000300 GPIO P1 General purpose input and output, port 1

1 0x40001000 RADIO RADIO 2.4 GHz radio

2 0x40002000 UART UART0 Universal asynchronous receiver/transmitter Deprecated

2 0x40002000 UARTE UARTE0 Universal asynchronous receiver/transmitter with EasyDMA,

unit 0

3 0x40003000 SPI SPI0 SPI master 0 Deprecated

3 0x40003000 SPIM SPIM0 SPI master 0

3 0x40003000 SPIS SPIS0 SPI slave 0

3 0x40003000 TWI TWI0 Two-wire interface master 0 Deprecated

3 0x40003000 TWIM TWIM0 Two-wire interface master 0

3 0x40003000 TWIS TWIS0 Two-wire interface slave 0

4 0x40004000 TWI TWI1 Two-wire interface master 1 Deprecated

4 0x40004000 TWIM TWIM1 Two-wire interface master 1

4 0x40004000 TWIS TWIS1 Two-wire interface slave 1

5 0x40005000 NFCT NFCT Near field communication tag

6 0x40006000 GPIOTE GPIOTE GPIO tasks and events

7 0x40007000 SAADC SAADC Analog to digital converter

8 0x40008000 TIMER TIMER0 Timer 0

9 0x40009000 TIMER TIMER1 Timer 1

10 0x4000A000 TIMER TIMER2 Timer 2

11 0x4000B000 RTC RTC0 Real-time counter 0

12 0x4000C000 TEMP TEMP Temperature sensor

13 0x4000D000 RNG RNG Random number generator

14 0x4000E000 ECB ECB AES electronic code book (ECB) mode block encryption

15 0x4000F000 AAR AAR Accelerated address resolver

15 0x4000F000 CCM CCM AES counter with CBC-MAC (CCM) mode block encryption

16 0x40010000 WDT WDT Watchdog timer

17 0x40011000 RTC RTC1 Real-time counter 1

18 0x40012000 QDEC QDEC Quadrature decoder

19 0x40013000 COMP COMP General purpose comparator

19 0x40013000 LPCOMP LPCOMP Low power comparator

20 0x40014000 EGU EGU0 Event generator unit 0

20 0x40014000 SWI SWI0 Software interrupt 0

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ID Base address Peripheral Instance Description

26 0x4001A000 TIMER TIMER3 Timer 3

27 0x4001B000 TIMER TIMER4 Timer 4

28 0x4001C000 PWM PWM0 Pulse width modulation unit 0

29 0x4001D000 PDM PDM Pulse Density modulation (digital microphone) interface

30 0x4001E000 ACL ACL Access control lists

30 0x4001E000 NVMC NVMC Non-volatile memory controller

31 0x4001F000 PPI PPI Programmable peripheral interconnect

32 0x40020000 MWU MWU Memory watch unit

33 0x40021000 PWM PWM1 Pulse width modulation unit 1

34 0x40022000 PWM PWM2 Pulse width modulation unit 2

36 0x40024000 RTC RTC2 Real-time counter 2

37 0x40025000 I2S I2S Inter-IC sound interface

38 0x40026000 FPU FPU FPU interrupt

39 0x40027000 USBD USBD Universal serial bus device

40 0x40028000 UARTE UARTE1 Universal asynchronous receiver/transmitter with EasyDMA,

unit 1

41 0x40029000 QSPI QSPI External memory interface

42 0x5002A000 CC_HOST_RGF CC_HOST_RGF Host platform interface

42 0x5002A000 CRYPTOCELL CRYPTOCELL CryptoCell subsystem control interface

45 0x4002D000 PWM PWM3 Pulse width modulation unit 3

47 0x4002F000 SPIM SPIM3 SPI master 3

N/A 0x10000000 FICR FICR Factory information configuration

N/A 0x10001000 UICR UICR User information configuration

Table 3: Instantiation table

4.3 NVMC — Non-volatile memory controller

The non-volatile memory controller (NVMC) is used for writing and erasing of the internal flash memory and the UICR (user information configuration registers).

The CONFIG on page 27 is used to enable the NVMC for writing (CONFIG.WEN = Wen) and erasing

(CONFIG.WEN = Een). The user must make sure that writing and erasing are not enabled at the same time. Having both enabled at the same time may result in unpredictable behavior.

The CPU must be halted before initiating a NVMC operation from the debug system.

4.3.1 Writing to flash

When write is enabled, full 32-bit words can be written to word-aligned addresses in the flash.

As illustrated in Memory on page 20, the flash is divided into multiple pages. The same 32-bit word in

the flash can only be written n WRITE number of times before a page erase must be performed.

The NVMC is only able to write 0 to bits in the flash that are erased (set to 1). It cannot rewrite a bit back

to 1. Only full 32-bit words can be written to flash using the NVMC interface. To write less than 32 bits,

write the data as a full 32-bit word and set all the bits that should remain unchanged in the word to 1.

Note that the restriction on the number of writes (nWRITE) still applies in this case.

Only word-aligned writes are allowed. Byte or half-word-aligned writes will result in a hard fault.

The time it takes to write a word to flash is specified by tWRITE. The CPU is halted if the CPU executes code

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Core components

NVM writing time can be reduced by using READYNEXT. If this status bit is set to '1', code can perform the next data write to the flash. This write will be buffered and will be taken into account as soon as the ongoing write operation is completed.

4.3.2 Erasing a page in flash

When erase is enabled, the flash memory can be erased page by page using the ERASEPAGE on page

27.

After erasing a flash page, all bits in the page are set to 1. The time it takes to erase a page is specified

by tERASEPAGE. The CPU is halted if the CPU executes code from the flash while the NVMC is writing to the

flash.

See Partial erase of a page in flash on page 25 for information on dividing the page erase time into shorter chunks.

4.3.3 Writing to user information configuration registers (UICR)

User information configuration registers (UICR) are written in the same way as flash. After UICR has been written, the new UICR configuration will only take effect after a reset.

UICR can only be written nWRITE number of times before an erase must be performed using ERASEUICR on

page 29 or ERASEALL on page 28. The time it takes to write a word to UICR is specified by tWRITE.

The CPU is halted if the CPU executes code from the flash while the NVMC is writing to the UICR.

4.3.4 Erasing user information configuration registers (UICR)

When erase is enabled, UICR can be erased using the ERASEUICR on page 29.

After erasing UICR all bits in UICR are set to 1. The time it takes to erase UICR is specified by tERASEPAGE. The

CPU is halted if the CPU executes code from the flash while the NVMC performs the erase operation.

4.3.5 Erase all

When erase is enabled, flash and UICR can be erased completely in one operation by using the ERASEALL

on page 28. This operation will not erase the factory information configuration registers (FICR).

The time it takes to perform an ERASEALL command is specified by tERASEALL The CPU is halted if the CPU

executes code from the flash while the NVMC performs the erase operation.

4.3.6 Access port protection behavior

When access port protection is enabled, parts of the NVMC functionality will be blocked in order to prevent intentional or unintentional erase of UICR.

CTRL-AP ERASEALL NVMC ERASEPAGE NVMC ERASEPAGE PARTIAL

NVMC ERASEALL NVMC ERASEUICR

APPROTECT

Disabled Allowed Allowed Allowed Allowed Allowed

Enabled Allowed Allowed Allowed Allowed Blocked

Table 4: NVMC Protection

4.3.7 Partial erase of a page in flash

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When erase is enabled, the partial erase of a flash page can be started by writing to ERASEPAGEPARTIAL

on page 29. The duration of a partial erase can be configured in ERASEPAGEPARTIALCFG on page

29. A flash page is erased when its erase time reaches tERASEPAGE. Use ERASEPAGEPARTIAL N number

of times so that N * ERASEPAGEPARTIALCFG ≥ tERASEPAGE, where N * ERASEPAGEPARTIALCFG gives the

cumulative (total) erase time. Every time the cumulative erase time reaches tERASEPAGE, it counts as one

erase cycle.

After the erase is done, all bits in the page are set to '1'. The CPU is halted if the CPU executes code from the flash while the NVMC performs the partial erase operation.

The bits in the page are undefined if the flash page erase is incomplete, i.e. if a partial erase has started

but the total erase time is less than tERASEPAGE.

4.3.8 Cache

An instruction cache (I-Cache) can be enabled for the ICODE bus in the NVMC.

See the Memory map in Memory map on page 21 for the location of flash.

A cache hit is an instruction fetch from the cache, and it has a 0 state delay. The number of wait-states for a cache miss, where the instruction is not available in the cache and needs to be fetched from

flash, depends on the processor frequency and is shown in CPU on page 19

Enabling the cache can increase CPU performance and reduce power consumption by reducing the number of wait cycles and the number of flash accesses. This will depend on the cache hit rate. Cache will use some current when enabled. If the reduction in average current due to reduced flash accesses is larger than the cache power requirement, the average current to execute the program code will reduce.

When disabled, the cache does not use current and does not retain its content.

It is possible to enable cache profiling to analyze the performance of the cache for your program using the ICACHECNF register. When profiling is enabled, the IHIT and IMISS registers are incremented for every instruction cache hit or miss respectively. The hit and miss profiling registers do not wrap around after reaching the maximum value. If the maximum value is reached, consider profiling for a shorter duration to get correct numbers.

4.3.9 Registers

Base address Peripheral Instance Description Configuration

0x4001E000 NVMC NVMC Non-volatile memory controller

Table 5: Instances

READY 0x400 Ready flag

READYNEXT 0x408 Ready flag

CONFIG 0x504 Configuration register

ERASEPAGE 0x508 Register for erasing a page in code area

ERASEPCR1 0x508 Register for erasing a page in code area. Equivalent to ERASEPAGE. Deprecated

ERASEALL 0x50C Register for erasing all non-volatile user memory

ERASEPCR0 0x510 Register for erasing a page in code area. Equivalent to ERASEPAGE. Deprecated

ERASEUICR 0x514 Register for erasing user information configuration registers

ERASEPAGEPARTIAL 0x518 Register for partial erase of a page in code area

ERASEPAGEPARTIALCFG 0x51C Register for partial erase configuration

ICACHECNF 0x540 I-code cache configuration register.

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Core components

IMISS 0x54C I-code cache miss counter.

4.3.9.1 READY

Address offset: 0x400 Ready flag

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ID A

A R READY NVMC is ready or busy

Busy 0 NVMC is busy (on-going write or erase operation)

Ready 1 NVMC is ready

4.3.9.2 READYNEXT

Address offset: 0x408 Ready flag

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ID A

A R READYNEXT NVMC can accept a new write operation

Busy 0 NVMC cannot accept any write operation

Ready 1 NVMC is ready

4.3.9.3 CONFIG

Address offset: 0x504 Configuration register

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ID A A

A RW WEN Program memory access mode. It is strongly recommended

to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated.

Ren 0 Read only access

Wen 1 Write enabled

Een 2 Erase enabled

4.3.9.4 ERASEPAGE

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Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID AccessField Value ID Value Description

A RW ERASEPAGE Register for starting erase of a page in code area

The value is the address to the page to be erased. (Addresses of first word in page). Note that the erase must be enabled using CONFIG.WEN before the page can be erased. Attempts to erase pages that are outside the code area may result in undesirable behaviour, e.g. the wrong page may be erased.

4.3.9.5 ERASEPCR1 ( Deprecated )

Register for erasing a page in code area. Equivalent to ERASEPAGE.

A RW ERASEPCR1 Register for erasing a page in code area. Equivalent to

ERASEPAGE.

4.3.9.6 ERASEALL

Address offset: 0x50C

Register for erasing all non-volatile user memory

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ID A

A RW ERASEALL Erase all non-volatile memory including UICR registers. Note

that the erase must be enabled using CONFIG.WEN before the non-volatile memory can be erased.

NoOperation 0 No operation

Erase 1 Start chip erase

4.3.9.7 ERASEPCR0 ( Deprecated )

Register for erasing a page in code area. Equivalent to ERASEPAGE.

A RW ERASEPCR0 Register for starting erase of a page in code area. Equivalent

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Core components

4.3.9.8 ERASEUICR

Register for erasing user information configuration registers

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ID A

A RW ERASEUICR Register starting erase of all user information configuration

registers. Note that the erase must be enabled using CONFIG.WEN before the UICR can be erased.

NoOperation 0 No operation

Erase 1 Start erase of UICR

4.3.9.9 ERASEPAGEPARTIAL

Register for partial erase of a page in code area

A RW ERASEPAGEPARTIAL Register for starting partial erase of a page in code area

The value is the address to the page to be partially erased (address of the first word in page). Note that the erase must be enabled using CONFIG.WEN before every erase page partial and disabled using CONFIG.WEN after every erase page partial. Attempts to erase pages that are outside the code area may result in undesirable behaviour, e.g. the wrong page may be erased.

4.3.9.10 ERASEPAGEPARTIALCFG

Address offset: 0x51C

Register for partial erase configuration

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ID A A A A A A A

Reset 0x0000000A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 ID AccessField Value ID Value Description

A RW DURATION Duration of the partial erase in milliseconds

The user must ensure that the total erase time is long enough for a complete erase of the flash page.

4.3.9.11 ICACHECNF

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Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ID B A

A RW CACHEEN Cache enable

Disabled 0 Disable cache. Invalidates all cache entries.

Enabled 1 Enable cache

B RW CACHEPROFEN Cache profiling enable

Disabled 0 Disable cache profiling

Enabled 1 Enable cache profiling

4.3.9.12 IHIT

Address offset: 0x548 I-code cache hit counter.

A RW HITS Number of cache hits

4.3.9.13 IMISS

Address offset: 0x54C I-code cache miss counter.

A RW MISSES Number of cache misses

4.3.10 Electrical specification

4.3.10.1 Flash programming

nWRITE Number of times a 32-bit word can be written before erase 2

nENDURANCE Erase cycles per page 10000

tWRITE Time to write one 32-bit word 411 _µs

tERASEPAGE Time to erase one page 851 ms

tERASEALL Time to erase all flash 1691 ms

tERASEPAGEPARTIAL,acc Accuracy of the partial page erase duration. Total

execution time for one partial page erase is defined as

ERASEPAGEPARTIALCFG * tERASEPAGEPARTIAL,acc.

1.051

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Core components

4.3.10.2 Cache size

SizeICODE I-Code cache size 2048 Bytes

4.4 FICR — Factory information configuration registers

Factory information configuration registers (FICR) are pre-programmed in factory and cannot be erased by the user. These registers contain chip-specific information and configuration.

4.4.1 Registers

Base address Peripheral Instance Description Configuration

0x10000000 FICR FICR Factory information configuration

Table 7: Instances

CODEPAGESIZE 0x010 Code memory page size

CODESIZE 0x014 Code memory size

DEVICEID[0] 0x060 Device identifier

DEVICEID[1] 0x064 Device identifier

ER[0] 0x080 Encryption root, word 0

ER[3] 0x08C Encryption root, word 3

IR[0] 0x090 Identity Root, word 0

IR[3] 0x09C Identity Root, word 3

DEVICEADDRTYPE 0x0A0 Device address type

DEVICEADDR[0] 0x0A4 Device address 0

DEVICEADDR[1] 0x0A8 Device address 1

INFO.PART 0x100 Part code

INFO.VARIANT 0x104 Build code (hardware version and production configuration)

INFO.PACKAGE 0x108 Package option

INFO.RAM 0x10C RAM variant

INFO.FLASH 0x110 Flash variant

INFO.UNUSED8[0] 0x114 Reserved

INFO.UNUSED8[1] 0x118 Reserved

INFO.UNUSED8[2] 0x11C Reserved

PRODTEST[0] 0x350 Production test signature 0

TEMP.A0 0x404 Slope definition A0

TEMP.A2 0x40C Slope definition A2

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Register Offset Description TEMP.B1 0x420 Y-intercept B1

TEMP.B2 0x424 Y-intercept B2

TEMP.B4 0x42C Y-intercept B4

TEMP.T0 0x434 Segment end T0

TEMP.T2 0x43C Segment end T2

NFC.TAGHEADER0 0x450 Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST, and NFCID1_LAST.

NFC.TAGHEADER3 0x45C Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST, and NFCID1_LAST.

TRNG90B.BYTES 0xC00 Amount of bytes for the required entropy bits

TRNG90B.RCCUTOFF 0xC04 Repetition counter cutoff

TRNG90B.APCUTOFF 0xC08 Adaptive proportion cutoff

TRNG90B.STARTUP 0xC0C Amount of bytes for the startup tests

TRNG90B.ROSC1 0xC10 Sample count for ring oscillator 1

TRNG90B.ROSC4 0xC1C Sample count for ring oscillator 4

4.4.1.1 CODEPAGESIZE

Address offset: 0x010 Code memory page size

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ID AccessField Value ID Value Description

A R CODEPAGESIZE Code memory page size

4.4.1.2 CODESIZE

Address offset: 0x014 Code memory size

A R CODESIZE Code memory size in number of pages

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Core components

4.4.1.3 DEVICEID[n] (n=0..1)

Address offset: 0x060 + (n × 0x4) Device identifier

A R DEVICEID 64 bit unique device identifier

DEVICEID[0] contains the least significant bits of the device identifier. DEVICEID[1] contains the most significant bits of the device identifier.

4.4.1.4 ER[n] (n=0..3)

Address offset: 0x080 + (n × 0x4) Encryption root, word n

A R ER Encryption root, word n

4.4.1.5 IR[n] (n=0..3)

Address offset: 0x090 + (n × 0x4) Identity Root, word n

A R IR Identity Root, word n

4.4.1.6 DEVICEADDRTYPE

Address offset: 0x0A0 Device address type

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ID A

Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ID AccessField Value ID Value Description

A R DEVICEADDRTYPE Device address type

Public 0 Public address

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4.4.1.7 DEVICEADDR[n] (n=0..1)

Address offset: 0x0A4 + (n × 0x4) Device address n

A R DEVICEADDR 48 bit device address

DEVICEADDR[0] contains the least significant bits of the device address. DEVICEADDR[1] contains the most significant bits of the device address. Only bits [15:0] of DEVICEADDR[1] are used.

4.4.1.8 INFO.PART

Address offset: 0x100 Part code

A R PART Part code

N52840 0x52840 nRF52840

Unspecified 0xFFFFFFFF Unspecified

4.4.1.9 INFO.VARIANT

Build code (hardware version and production configuration)

A R VARIANT Build code (hardware version and production

configuration). Encoded as ASCII.

AAAA 0x41414141 AAAA

BAAA 0x42414141 BAAA

CAAA 0x43414141 CAAA

AABA 0x41414241 AABA

AABB 0x41414242 AABB

AACA 0x41414341 AACA

AAAB 0x41414142 AAAB

4.4.1.10 INFO.PACKAGE

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Core components

Package option

A R PACKAGE Package option

QI 0x2004 QIxx - 73-pin aQFN

CK 0x2005 CKxx - WLCSP

4.4.1.11 INFO.RAM

Address offset: 0x10C RAM variant

A R RAM RAM variant

K16 0x10 16 kByte RAM

4.4.1.12 INFO.FLASH

Address offset: 0x110 Flash variant

A R FLASH Flash variant

K128 0x80 128 kByte FLASH

K1024 0x400 1 MByte FLASH

K2048 0x800 2 MByte FLASH

4.4.1.13 PRODTEST[n] (n=0..2)

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A R PRODTEST Production test signature n

Done 0xBB42319F Production tests done

NotDone 0xFFFFFFFF Production tests not done

4.4.1.14 TEMP.A0

Address offset: 0x404 Slope definition A0

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ID A A A A A A A A A A A A

Reset 0xFFFFF320 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 0 1 0 0 0 0 0 ID AccessField Value ID Value Description

A R A A (slope definition) register.

4.4.1.15 TEMP.A1

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

4.4.1.16 TEMP.A2

Address offset: 0x40C Slope definition A2

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reset 0xFFFFF35D 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 1 1 0 1 ID AccessField Value ID Value Description

4.4.1.17 TEMP.A3

(37)

Core components

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

4.4.1.18 TEMP.A4

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

4.4.1.19 TEMP.A5

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reset 0xFFFFF37B 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 ID AccessField Value ID Value Description

4.4.1.20 TEMP.B0

Address offset: 0x41C Y-intercept B0

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ID A A A A A A A A A A A A A A

Reset 0xFFFF3FCC 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 0 0 1 1 0 0 ID AccessField Value ID Value Description

A R B B (y-intercept)

4.4.1.21 TEMP.B1

Address offset: 0x420 Y-intercept B1

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reset 0xFFFF3F98 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 0 0 1 1 0 0 0 ID AccessField Value ID Value Description

(38)

4.4.1.22 TEMP.B2

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reset 0xFFFF3F98 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 0 0 1 1 0 0 0 ID AccessField Value ID Value Description

4.4.1.23 TEMP.B3

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reset 0xFFFF0012 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 ID AccessField Value ID Value Description

4.4.1.24 TEMP.B4

Address offset: 0x42C Y-intercept B4

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reset 0xFFFF004D 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 1 ID AccessField Value ID Value Description

4.4.1.25 TEMP.B5

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reset 0xFFFF3E10 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 0 0 0 0 1 0 0 0 0 ID AccessField Value ID Value Description

https://infocenter.nordicsemi.com/pdf/nRF52840_PS_v1.1.pdf

nRF52840

Feature list

Contents

Feature list

ii

1

Revision history

12

2

About this document

14

3

Block diagram

17

4

Core components

19

5

Power and clock management

55

6

Peripherals

99

7

Hardware and layout

575

8

Recommended operating conditions

611

9

Absolute maximum ratings

612

10

Ordering information

613

11

Legal notices

618

1

Revision history

2

About this document

2.1 Document naming and status

2.2 Peripheral naming and abbreviations

2.3 Register tables

2.3.1 Fields and values

2.4 Registers

2.4.1 DUMMY

3

Block diagram

4

Core components

4.1 CPU

4.1.1 Floating point interrupt

4.1.2 CPU and support module configuration

4.1.3 Electrical specification

4.1.3.1 CPU performance

4.2 Memory

4.2.1 RAM - Random access memory

4.2.2 Flash - Non-volatile memory

4.2.3 Memory map

Device

Device

Device

RAM

RAM

Peripheral

SRAM

Code

Private peripheral bus

AHB peripherals

APB peripherals

UICR

FICR

Data RAM

Code RAM

Flash

0xFFFFFFFF

0x00000000

_0x12000000