A Dissertation
Submitted to the Program in Electronics Science, Electronics Science Department
in partial fulllment of the requirements for the degree of
Master of Science in Electronics
at the
Instituto Nacional de Astrofísica, Óptica y
Electrónica
October 2014 Tonantzintla, Puebla
Advisor:
Dr. Esteban Tlelo Cuautle
c
INAOE 2014 All rights reserved
The author hereby grants to INAOE permission to reproduce and to distribute copies of this thesis document in whole or in part
I, José Luis Valtierra Sánchez de la Vega, declare that this thesis titled, 'Design criteria for a discrete time chaos based CMOS true random number generator' and the work presented in it are my own. I conrm that:
This work was done wholly or mainly while in candidature for a research degree at
this Institute.
Where any part of this thesis has previously been submitted for a degree or any
other qualication at this University or any other institution, this has been clearly stated.
Where I have consulted the published work of others, this is always clearly
at-tributed.
Where I have quoted from the work of others, the source is always given. With the
exception of such quotations, this thesis is entirely my own work.
I have acknowledged all main sources of help.
Where the thesis is based on work done by myself jointly with others, I have made
clear exactly what was done by others and what I have contributed myself.
Signed:
Date:
by José Luis Valtierra Sánchez de la Vega
Random number generators are a fundamental component in cryptographic applications such as key generation and digital signatures. Software based solutions have proven ef-fective in some situations, nevertheless, the need for hardware integrated circuit (IC) random number generators based on truly random physical phenomena has been rec-ognized by major information technology companies. Discrete time chaotic dynamical systems exhibit properties such as extreme sensitivity to the initial conditions and noise-like trajectories. These properties in combination with an initial condition set by thermal noise produce a highly unpredictable output suitable for truly random number genera-tion. However, discrete time chaotic systems based IC true random number generators are not without problems. Several design considerations have to be made in order to maintain the properties of the chaotic dynamical system based circuit at the heart of the true random number generator. In this work, design guidelines aimed at guaranteeing the correct operation of a proposed discrete time chaotic circuit are obtained through mathematical modeling. A true random number generation scheme based on the pro-posed circuit is then introduced. Finally, the suitability of the scheme as a true random number generator is validated with the NIST test suite 800-22.
Contents
Declaration of Authorship i
Abstract iii
Acknowledgements iv
Contents v
List of Figures vii
List of Tables ix
1 Introduction 1
1.1 Dynamical systems . . . 1
1.2 Formal denitions of chaos. . . 2
1.3 Characterization of chaos . . . 2
1.3.1 Lyapunov exponent. . . 3
1.3.2 Bifurcation diagram . . . 4
1.3.3 Entropy . . . 4
1.4 Thesis Objective . . . 4
2 On True Random Number Generators 6 2.1 TRNG Characterization . . . 7
2.2 Integrated Circuit TRNG Types . . . 8
2.3 On chaotic oscillators . . . 10
2.4 Piecewise linear 1-dimensional Chaotic Map based TRNGs . . . 11
2.5 Issues of PL1D map based chaotic oscillators . . . 12
2.6 Recent implementations of PL1D map based TRNGs . . . 13
3 The skew-tent map 17 3.1 Dynamics of the skew tent-map . . . 17
3.1.1 Lyapunov exponent. . . 18
3.1.2 Bifurcation diagrams . . . 19
3.1.3 Entropy . . . 21
3.2 Simulink model . . . 21
3.3 Non-idealities modeling of the skew-tent map . . . 22 v
4.3 NIST test results . . . 35
5 A skew-tent map based CMOS true random number generator 37 5.1 True random number generator circuit . . . 37
5.2 Circuit design . . . 38
5.2.1 P-input operational amplier . . . 39
5.2.2 Switch . . . 40
5.2.3 Complementary input operational amplier . . . 41
5.2.4 Behavioral blocks . . . 41
5.3 Chaotic oscillator simulation results. . . 42
5.4 TRNG NIST tests results . . . 42
6 Conclusions 47
A Lyapunov exponent MATLAB script 48
B Bifurcation diagram MATLAB script 50
C Entropy MATLAB script 52
D Op amp Verilog-A code 53
E Switch Verilog-A code 55
F OTA Verilog-A code 56
G Flip op d Verilog-A code 57
H XOR Verilog-A code 58
List of Figures
1.1 Time series for two nearby initial points of the logistic map. . . 3
2.1 Block based description of a true random number generator . . . 6
2.2 Computer hardware compatible TRNG types. . . 9
2.3 Electrical noise based TRNG. . . 9
2.4 Jitter based TRNG. . . 10
2.5 Chaos based TRNG. . . 11
2.6 Bifurcation diagram of a modied logistic map. . . 13
2.7 PL1D chaotic map oscillator . . . 14
2.8 Zhou's extension of the Bernoulli shift. . . 15
3.1 Phase diagram of the skew-tent map . . . 18
3.2 Lyapunov exponent diagram of the skew-tent map. . . 18
3.3 Lyapunov exponent diagram of the Bernoulli shift map. . . 19
3.4 Bifurcation diagram of the skew-tent map. . . 20
3.5 Bifurcation diagram of the Bernoulli shift map. . . 20
3.6 Simulink model for the skew-tent map . . . 21
3.7 Time series of the skew-tent map simulink model for µ= 0.5 . . . 22
3.8 Time series of the skew-tent map simulink model for µ= 1.9 . . . 22
3.9 Phase diagram of the skew-tent map simulink model forµ= 0.5 . . . 23
3.10 Phase diagram of the skew-tent map simulink model forµ= 1.9 . . . 23
3.11 Eect of slope variation on the skew-tent map. . . 24
3.12 Eect of threshold variation on the skew-tent map. . . 24
3.13 Eect of threshold variation on the skew-tent map for ep = 1% and en = 1%. . . 25
3.14 Eect of threshold variation on the skew-tent map foret=−10mV. . . . 26
3.15 Eect of threshold variation on the skew-tent map for ep = −1%, en = −1%andet=−10mV. . . 27
3.16 Eect of threshold variation on the skew-tent map forep = 1%,en=−1% andet= 10mV.. . . 27
3.17 New slope values mps and mns. . . 28
4.1 Block based skew-tent map oscillator. . . 29
4.2 Shift + half delay circuit. . . 30
4.3 Digital control. . . 31
4.4 Signal dependent scaling. . . 32
4.5 Signal dependent change of sign. . . 32
4.6 Phase portrait of the Verilog-A circuit. . . 33
4.7 Time series of the Verilog-A circuit.. . . 33 vii
5.6 Complementary input folded cascode op amp. . . 41
5.7 Complementary input folded cascode op amp i/o transfer characteristics. . 42
5.8 Double edge ip op D transient. . . 43
5.9 Test sine input (yellow), output of the shift + half delay stage (orange). . 43
5.10 Input from previous stage (yellow), output of the signal dependent scaling
stage (orange). . . 44
5.11 Input from previous stage (yellow), output of the signal dependent change
of sign stage (orange). . . 44
List of Tables
3.1 Entropy for the skew tent and Bernoulli shift maps.. . . 21
3.2 Eect of errors on the skew tent map I. . . 25
3.3 Eect of errors on the skew tent map II. . . 25
3.4 Eect of errors on the skew tent map III. . . 26
3.5 Eect of errors on the skew tent map IV.. . . 26
3.6 Eect of errors on the skew tent map V. . . 27
3.7 Eect of errors on the skew tent map VI.. . . 28
3.8 Eect of errors on the skew tent map VII. . . 28
4.1 NIST test suite 800-22 results for chaotic oscillator behavioral implemen-tation. . . 36
5.1 Truth table of the post processing stage. . . 38
5.2 Transistor sizing for the folded cascode p-input op amp. . . 39
5.3 Transistor sizing for the CMOS complementary switch. . . 40
5.4 Transistor sizing for the complementary input folded cascode op amp. . . 41
5.5 NIST test suite 800-22 results for the behavioral TRNG. . . 45
5.6 NIST test suite 800-22 results for the CMOS/Verilog-A TRNG. . . 46
5.7 NIST test suite 800-22 results for the CMOS TRNG. . . 46
a nonlinear dynamical system that displayed high sensitivity to the initial conditions, an essential property of chaotic systems. Ever since then, decades of research have expanded the understanding of this ubiquitous phenomena and produced several appli-cations in dierent areas of engineering such as cryptography [2], data encryption [3] [4] and watermarking [5], carrier modulation [6], neural networks [7] [8], noise generation [9], electromagnetic interference control [10], robotics [11], among others.
Before moving onto the main contributions of this project, the fundamental theoretical notions of chaos theory are introduced.
1.1 Dynamical systems
Dynamical systems describe motion in nature. In the classical sense, motion can be modeled by equations of the following form
˙
x(t) =f(a, x(t)) t >0 (1.1)
and
x(n+ 1) =f(a, x(n)) n∈N (1.2)
The state variables are represented by x(t) and x(n). The possible values of the state variables imply that (1.1) is a dierential equation while (1.2) is a dierence equation or map. In both cases, x represents a q-dimensional state vector, i.e. x∈Rq. The control
parameter a (also called bifurcation parameter) has m components such that a ∈ Rm.
The control parameter aects the evolution of the state variables. The relationship between the parameters and the state variables is dened by a functionf. The range of f is in the same space where the state vector xlives.
Chaos, dened colloquially as irregular an unpredictable behavior, can stem from dy-namical systems as long asf has the suitable properties. Likewise, amust be set to the
appropriate values in order to precipitate a transition to chaos. The chaotic behavior product of dynamical systems is known as deterministic chaos. One could assume that chaotic motion can only be displayed by highly complex systems, however, this isn't the case; as already shown in many research works a simple discrete one dimensional (1-D) system is capable of producing chaotic behavior [12].
1.2 Formal denitions of chaos
The complexity of chaotic phenomena has brought about several denitions that vary in stringentness and mathematical origin (topological or metric spaces, bifurcation theory, etc). However, they all share some characteristics such as a requirement of extremely high sensitivity to the initial conditions.
Devaney's formulation of chaos [13] is widely accepted and consists of the following conditions:
1. Sensitive dependence on the initial conditions 2. Topological transitivity
3. Regularity
The rst condition is clear, sensitive dependence on the initial conditions leads to unpre-dictability. This is commonly known as the buttery eect and involves the generation of completely dierent trajectories by almost identical initial conditions. Figure 1.1 exem-plies this phenomenon for the logistic map with two initial conditions (.3 and .30001). A major consequence of the second condition in Devaney's denition is that the orbits of the system visit all of the phase space. The third condition implies a dense distribution of said orbits.
1.3 Characterization of chaos
Chaos can be proved analytically only for very simple systems. There are other meth-ods to characterize chaotic behavior, namely: Lyapunov exponent, bifurcation diagrams
5 10 15 20 25 30 35 40 0
0.1 0.2 0.3
t
Figure 1.1: Time series for two nearby initial points of the logistic map.
and entropy. These methods analyze the output data of the dynamical system under specied conditions. Their main advantage lies in the fact that they can be compu-tationally implemented. Furthermore, there is a relationship between these tests and formal denitions such as the one introduced in the previous section.
1.3.1 Lyapunov exponent
The Lyapunov exponent, named after Alexander Lyapunov, gives information about the sensitivity to the initial conditions of a dynamical system. It is dened as follows: Denition 1. Letf :R→R be a dierentiable function. The Lyapunov exponent of the
system described by x0 and xn+1 =f(xn) is dened by:
λ(x0) = lim x→∞
1
n n
X
i=1
ln|f0(xi−1)| (1.3)
Let us consider a dynamical system with an innitesimal error on the initial condition
x0. When the Lyapunov exponent is positive, this error will increase (situation of chaos),
1.3.2 Bifurcation diagram
Bifurcation diagrams show the qualitative behavior of a dynamical system. The function is iterated for every control parameter (also called bifurcation parameter) value sepa-rately and the orbit points are plotted [15]. Essentially, bifurcation diagrams represent the possible steady state values the system can take as a function of the bifurcation parameter.
1.3.3 Entropy
Entropy as introduced by Shannon [16], measures the uncertainty in a random variable. The greater the entropy the less certain we are about the outcome. In other words, it is a measure of unpredictability, and it is dened in the following manner:
Denition 2. The Shannon entropy of a discrete random variable X and probability distribution P is dened as:
H(x) =−X
x∈X
p(x)log(p(x)) (1.4)
Other notions of entropy aid us in bridging this denition with formal formulations of chaos. In particular, the Kolmogorov-Sinai (K-S) entropy, which is connected to Shannon's as shown by Frigg [17]. K-S entropy dened in relation to Shannon entropy measures the highest average information received about the present state of the system relative to its former state. According to the Variational Principle [18], a positive K-S entropy leads to sensitive dependence on initial conditions which is an indicator of chaos as introduced previously. Pesin's theorem provides justication for this; he introduced a relationship between K-S entropy and Lyapunov exponents whereby the sum of the positive Lyapunov exponents equals K-S entropy for suciently chaotic systems [19].
1.4 Thesis Objective
Among the great amount of applications of chaos in engineering, this work presents a chaos based integrated circuit application aimed at the generation of truly random num-bers with the purpose of data encryption. The dynamics of chaotic systems can be used as the basis of true random number generators, however, this very same dynamics can sometimes prove dicult to maintain and control. Through the mathematical model-ing of the proposed chaotic dynamical system, this work aims to obtain insight into its
circuit architecture presented and veried in Chapter 4. Chapter 5 presents the true random number generator circuit and validates its performance.
On True Random Number
Generators
True Random Number Generators (TRNGs) are the fundamental component in crypto-graphic systems. They are essential in cryptocrypto-graphic applications such as key generation and digital signatures [20]. An ideal TRNG is able to provide uncorrelated and unbiased innitely long random binary sequences [21] through the harvesting of an entropy source. A random bit sequence could be interpreted as the result of the ips of an unbiased "fair" coin with two sides ("0" and "1"), with each ip having a probability of exactly 1/2 of producing a '0' or a '1'. Furthermore, the ips are independent (uncorrelated) from each other in the sense that the result of any previous coin ip does not aect future ips. Thus, the ideal TRNG generates sequences resembling the described coin ip: all ele-ments of the sequence are generated independently of each other and the value of the next element in the sequence cannot be predicted, regardless of how many elements have already been produced. Figure2.1 depicts the TRNG concept in a general block form.
Figure 2.1: Block based description of a true random number generator
• Entropy source
The entropy source for TRNGs is physical phenomena with complex noise-like behavior. Examples of such phenomena are the Brownian motion, Johnson thermal
• Postprocessing
The postprocessing is considered optional. Its goal is to remove any correlation and bias in the bit sequence introduced by the harvesting mechanism. The complexity of the postprocessing varies but in general, a simple structure is desired. The Von Neumann [22] and XOR correctors are the most commonly used schemes. It should be considered that any postprocessing algorithm is compressive, i.e. their output data rate is lower or equal than the input one.
Programmers typically try to obtain entropy using existing peripherals. For instance, modern OSs have OS-level RNGs based on the timing of kernel input-output (IO) events [23]. These seemingly random events are used as the input seed for pseudo-random number generators (PRNGs). A PRNG is a deterministic algorithm that produces num-bers whose distribution is ideally indistinguishable from uniform [24]. Unfortunately, the quality of the RNG depends on the system's conguration and hardware. In other words, conditions of operation introduce a bias in the quality of the RNG, which directly aects the security of the system.
The need for a well designed, secure and ecient TRNG whose characteristics approxi-mate the ideal as much as possible, has been recognized by major companies. Recently, Intel and VIA have incorporated integrated circuit (IC) TRNGs in their processor cores [25], [26].
2.1 TRNG Characterization
TRNG characterization consists of the statistical analysis of data output in order to determine and characterize its randomness as well as its suitability as a secure compo-nent in cryptographic systems. The most common test is the "Statistical Test Suite for Random and Pseudorandom Number Generators for Cryptographic Applications [27]." This test suite was developed by the Information Technology Laboratory at the National
Institute of Standards and Technology (NIST), a non-regulatory agency of the United States government.
The NIST Test Suite is composed of 15 tests that were developed to test the randomness of (arbitrarily long) binary sequences produced by either hardware or software based cryptographic random or pseudo-random number generators. These tests focus on a va-riety of dierent types of non-randomness that could exist in a sequence. Randomness is a probabilistic property; that is, the properties of a random sequence can be char-acterized and described in terms of probability. The likely outcome of statistical tests, when applied to a truly random sequence, is known a priori and can be described in probabilistic terms. There are an innite number of possible statistical tests, each as-sessing the presence or absence of a pattern which, if detected, would indicate that the sequence is nonrandom. Because there are so many tests for judging whether a sequence is random or not, no specic nite set of tests is deemed complete. In addition, the results of statistical testing must be interpreted with some care and caution to avoid incorrect conclusions about a specic generator
A statistical test is formulated to test a specic null hypothesis (H0), e.g., that the sequence being tested is random. Associated with this null hypothesis is the alternative hypothesis Ha (sequence not random). For each test, a relevant randomness statistic must be chosen and used to determine the acceptance or rejection of the null hypothesis. Under an assumption of randomness, such a statistic has a distribution of possible values. A theoretical reference distribution of this statistic under the null hypothesis is determined by mathematical methods. From this reference distribution, a critical value is determined (typically, this value is "far out" in the tails of the distribution, say out at the 99 the hypothesis is accepted).
2.2 Integrated Circuit TRNG Types
Integrated circuit (IC) TRNGs have the clear advantage of being able to be embedded in any kind of computing device. A classication for TRNGs compatible with current computer architectures is shown in Figure 2.2. IC TRNGs can be classied by the phenomena they are based on as follows:
• Electrical noise
Dierent kinds of noise present in semiconductor devices aid in the design of TRNGs. From thermal noise in resistive components to avalanche, shot and 1/f noise. In general, the goal is to amplify the noise to a manageable level. After-wards, a threshold set by a comparator produces a binary sequence. This scheme
Figure 2.2: Computer hardware compatible TRNG types.
has several disadvantages. First, the frequency of operation is generally very lim-ited. They are also highly sensitive to interfering signals coming from the substrate or power rails. Finally, the amplier stage tends to have a high power consumption.
Figure 2.3: Electrical noise based TRNG.
• Jitter
Jitter based TRNGs are generally implemented in fully digital architectures. In its most basic form, a high frequency oscillator is sampled by one with slower frequency[28]. The jitter in one of them is deliberately enhanced. Jitter is believed to be random because it is caused by thermal noise. They have several advantages. Their throughput can be very high, they can be made highly robust to external phenomena and they are readily integrated with digital systems. However, this approach requires a perfectly matched, 50 % duty cycle low-jitter fast oscillator for generating equiprobable bits. A high-jitter slow oscillator that has jitter-to-period
ratio in the excess of 10% is needed to generate high entropy bits. In addition, large frequency separation is mandatory for reducing potential correlations. Finally and more importantly, since these circuits are purely digital, either they usually do not ensure enough entropy or a high quantity of replicated structures are needed to be used to get acceptable levels of entropy [29].
Figure 2.4: Jitter based TRNG.
• Chaos
As mentioned in Chapter 1, some dynamical systems under certain conditions ex-hibit irregular and unpredictable behavior as well as extreme sensitivity to the initial conditions. This behavior, which is known as chaos, would at rst seem un-desirable but it can be employed as the basis of a true random number generator. In general, an initial condition set by thermal noise is amplied by a non-linear analog or mixed-signal circuit that maps a chaotic dynamical system (a chaotic oscillator). A threshold is then set by a comparator, which produces a long term unpredictable binary sequence. The fact that the chaotic dynamical system can be studied and modeled before the circuit implementation in order to obtain the highest possible entropy as well as maintain its robustness is the biggest advantage. Furthermore, the nonreversible quantization operation necessary to generate a bit sequence from the analog circuit state does not allow us to retrieve precise information on the actual evolution of the system from the observation of the quantized values [30]. Thus, this combination of high security, high randomness and the possibility of a top-down design approach is ideal for its application as a TRNG.
2.3 On chaotic oscillators
Chua's circuit in 1983 [31], was the rst electrical implementation of a chaotic oscillator. It is based on three dierential equations (continuous time dynamical system) and has
Figure 2.5: Chaos based TRNG.
become a staple example in chaotic phenomena . Chaotic oscillators based on a map (discrete time dynamical system) were developed shortly after [32].
From a circuit implementation point of view, several features of chaotic discrete time dynamical systems make them superior to their continuous time counterparts. First, chaos can be produced from 1-dimensional maps whereas continuous systems need to be at least of 3rd order. Moreover, continuous time systems depend upon derivative operators obtained from the constitutive law of capacitors or inductors that require jumps from the voltage domain to the current domain [33]. On the other hand, discrete time circuits do not require derivation, the simpler maps depend only on scaling and threshold operations. It is clear then that continuous time chaos implies greater complexity, which translates as greater area and power consumption in the IC design world.
2.4 Piecewise linear 1-dimensional Chaotic Map based TRNGs
True random number generators based on Piecewise linear 1-dimensional (PL1D) chaotic maps have received great attention in recent years. Their mathematical simplicity yet rich and complex dynamics are perfect for its application as TRNG. PL1D chaotic maps are dened as follows:
xn+1 =
q1+k1(xn−TL) xn< TL q2+k2(xn−TL) xn> TL
(2.1)
wherek1, k2 >1,q1 > TL> q2.
Maps with more piecewise-linear regions are described in a similar manner. The bifur-cation parameterkn determines whether the map behaves as chaotic or not. Notice how
particular, the nonlinear function which is arguably the most important element in the map is just a comparator threshold. This is specially appealing to IC designers when compared to other chaos oscillators. Therefore, assuming correct parameter tuning, one can produce a chaotic output for a specic application from a relatively simple circuit. PL1D chaotic maps are normally implemented in either switched capacitor (SC) or switched current (SI) architectures. SC architectures require op amps, as active de-vices, and linear capacitors, as holding elements. High-quality capacitors (high linearity, reduced voltage, and temperature dependence, and good matching properties) are avail-able in technologies that oer parallel-plate structures separated by thin oxide. In digital process technologies, capacitors are commonly implemented by exploiting the thin-oxide gate capacitance of Metal Oxide Semiconductor (MOS) transistors. MOS-based capaci-tors usually exhibit larger capacitance per unit area and better matching than parallel-plate structures, but suer from signicant nonlinearities and parasitic capacitances, and must be conveniently biased to guarantee a low-resistivity conducting layer under the gate. In SI architectures, capacitors are formed by the input parasitics of transcon-ductors, thus, rendering the approach specially appealing for standard digital processes. Unfortunately, this notable simplication is at the expense of performance degradations [34].
2.5 Issues of PL1D map based chaotic oscillators
Piecewise linear 1-dimensional map based true random number generators are not with-out problems. Non-ideal eects inherent in IC process technologies may degrade or even eliminate the normal behavior of the chaotic oscillator at the heart of the TRNG, ren-dering it useless. The trajectories of the oscillator may either converge to parasitic stable points or diverge entirely after a determined number of iterations. The main culprits are the variations of nominal values of devices such as capacitors and voltage osets product of device mismatch.
The dynamics of some PL1D maps are specially susceptible to these non-ideal eects. Dynamical features such as a low tolerance of values of the bifurcation parameter or periodic regions in between chaotic regions are examples of this. This is shown in Figure
2.6for a piecewise linear version of the logistic map. The bifurcation parameter requires to be set as close as possible to β = 4to operate in chaotic regime. Notice how a small
variation would either reduce the output range of values or take the map out of chaotic regime (it would cause a convergence to zero). The designer must also avoid maps that involve complex and demanding mathematical operations such as logarithms. For this
Figure 2.6: Bifurcation diagram of a modied logistic map.
The simplicity of PL1D chaos oscillators allows for a block based synthesis described by behavioral language that considers non-idealities in order to know their impact previous to an IC implementation. Figure 2.7 shows the block based circuit for equation (2.1) when q1 =−q2 =A, TL = 0 and k1 = k2 =B. The IN I block generatesxn, which is
then multiplied by B and compared against zero. This comparison is made by the N L
block and its output sign depends onxn, the output of this block is then multiplied by A.TheSU M block adds the previous terms to obtainxn+1, which is sampled by theSH
block and then fed back to the nonlinear functionN Lblock. This kind of description is a
useful way to approach the IC design of a chaotic map. The impact of some non-idealities such as oset can be included in the blocks which can later be replaced by their circuit equivalents.
2.6 Recent implementations of PL1D map based TRNGs
As explained in the previous section, the dynamical features of PL1D chaotic maps are a mixed blessing: on one hand, their chaotic dynamics and simple mathematical description is ideal for its application as a TRNG; on the other, they might be fragile against technological process variations. It is no surprise then that the latest research
Figure 2.7: PL1D chaotic map oscillator
of PL1D map based TRNGs is focused on keeping the correct operation of the chaotic oscillator against non-idealities.
Dierent kinds of techniques have been employed to guarantee the chaotic dynamics of the oscillator. They can be either mathematical methods or IC design techniques. For instance, Zhou [35] proposed a new map based on the Bernoulli shift, described by equation (2.2). Zhou's map, described by (2.3), adds new regions to the classic form of the Bernoulli shift with the aim of improving its robustness. Figure 2.8 depicts the Bernoulli shift extension.
xn+1 =
Bxn−Asign(xn) xn<0 Bxn−Asign(xn) xn>0
(2.2)
xn+1=
−2C xn≤ −A−C Bxn+ 2A −A−C < xn≤ −A Bxn+A −A < xn<0 Bxn−A 0≤xn< A Bxn−2A A≤xn< A+C
2C xn≥A+C
(2.3)
The Bernoulli shift in its classic form diverges after a small noise perturbation, the goal of the new regions is to conne this divergent trajectories and keep them inside the map.
Figure 2.8: Zhou's extension of the Bernoulli shift.
It can clearly be seen that by adding this new regions, the complexity of the circuit increases.
In [36], a new form of the map proposed by [37] which is described by (2.4) is im-plemented. The authors model the variations previous to the circuit implementation to achieve robustness. The circuit architecture proposed is, however, highly complex, requiring the pipeline of four chaotic oscillators.
xn+1=
−m(xn+|m2|) −1< xn≤ −|m1| mxn |m1| < xn≤ |m1|
−m(xn−|m2|) |m1| < xn≤1
(2.4)
In [38], the authors use a modied version of the tent map, as described by (2.5). The dynamics of this version known as skew-tent suggest better tolerance to integrated circuit process variations. Finally, the authors nd the optimum threshold for random bit generation through the study of the map's statistics.
xn+1=
µxn 0≤xn≤ µ1 µ
µ−1(1−xn) 1
µ < xn≤1
When it comes to IC design techniques aimed at improving the performance of PL1D map based TRNGs, the work of Katz [39] stands out. In [39], the authors use the classic version of the Bernoulli shift described by (2.2) but aim to improve its robustness through the use of a fully dierential architecture.
Its mathematical description suggests ease of implementation and high tolerance to non-idealities inherent in IC process technology.
3.1 Dynamics of the skew tent-map
Although there are several variants of skew-tent maps, the one introduced in this section will be referred for the rest of the document as the skew-tent map. The equation for this map is depicted in (3.1) and its phase diagram is shown in Figure3.1.
xn+1 =
mp(xn−Et) + 1 xn< Et
−mn(xn−Et) + 1 xn> Et
(3.1)
The positive and negative slopes of the map are mp = µ and mn = µ−µ1, respectively,
and the threshold is Et= 1µ. The parameterµis the bifurcation parameter.
As explained in Chapter2, it is necessary to understand the dynamics of the map before an IC implementation. This is done with the techniques introduced in Chapter 1. Fur-thermore, the same tests will be applied to the widely used Bernoulli shift to compare their behavior and demonstrate the better suitability of the skew-tent for IC application. The Bernoulli shift map is repeated in this section for convenience.
xn+1 =
Bxn−Asign(xn) xn<0 Bxn−Asign(xn) xn>0
(3.2) 17
x(n+
1)
Et
x(n)Figure 3.1: Phase diagram of the skew-tent map
3.1.1 Lyapunov exponent
The Lyapunov exponent for both maps is plotted against their respective bifurcation parameter . A MATLAB program (listed in Appendix A) for the computation of the Lyapunov exponent was implemented for each map.
The Lyapunov exponent for the skew-tent is shown in Figure3.2. It gradually rises until it reaches a xed point at µ = 1 where λbecomes positive and the map enters chaotic
regime.
μ
λ
β
λ
Figure 3.3: Lyapunov exponent diagram of the Bernoulli shift map.
The evolution of the Lyapunov exponent for both maps is quite similar, however, the transition into chaos is smoother in the case of the Bernoulli shift.
3.1.2 Bifurcation diagrams
Bifurcation diagrams were obtained with a program implemented in MATLAB (listed in Appendix B). A random initial condition was generated and the function was iterated 500 times for relevant values of the bifurcation parameter.
The bifurcation diagram for the skew-tent is shown in Figure 3.4. Its dynamics are observed for µ∈[0,2]. The map behaves in a very straightforward manner, forµ <1 it
is not chaotic and becomes so forµ >1.
The Bernoulli shift is observed for β ∈ [0,2] in Figure 3.5 with A = 1. The output of
the system for 0 < β <1 has its values determined by two periodic orbits that end at |x| ≈1. For1< β <1.4the map is chaotic but its values are conned to three distinct
regions. For values of β > 1.4 the map is chaotic with the output taking values from [−1,1].
x(n)
μ
Figure 3.4: Bifurcation diagram of the skew-tent map.
β
x(n)
Figure 3.5: Bifurcation diagram of the Bernoulli shift map.
It can be seen that for the skew-tent map, the bifurcation parameter is more tolerant to variations when adjusted to operate in chaotic regime. This is one of the best features of the map and represents a clear advantage over the Bernoulli shift as well as the logistic map as seen previously in Figure 2.6, and the classic form of the tent map[43]. Other maps with similar tolerance are described by more complex equations [36].
Moddemeijer [44]. The script (listed in Appendix C) analyzes the output of 10,000 iterations for each map in their chaotic regime. The results are shown in Table3.1. The entropy for both cases is the maximum possible. According to Pesin [19] the maximum achievable entropy for 1-D chaotic maps is limited by ther single Lyapunov exponent,
ln(2) = 0.69.
A more thorough study of these maps and others of common use in relation to their suitability for integrated circuit application is available in [45].
3.2 Simulink model
A simulink model for the skew-tent map is shown in Figure 3.6. Its purpose is to verify the behavior of the map in a high-level environment.
Figure 3.6: Simulink model for the skew-tent map
The time series and phase portrait of the model are shown in Figures 3.7 to 3.10 for 200 iterations. The eect of the bifurcation parameter µ can be seen clearly. The time
series output is useless and converges to zero for µ= 0.5 (value out of chaotic regime).
In other words, the map is not oscillating. The opposite case occurs when µ= 1.9, the
map oscillates in chaotic region as expected from bifurcation and Lyapunov exponent diagrams.
0 50 100 150 200 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 (n) x(n)
Figure 3.7: Time series of the skew-tent map simulink model for µ= 0.5
0 50 100 150 200
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 (n) x(n)
Figure 3.8: Time series of the skew-tent map simulink model for µ= 1.9
3.3 Non-idealities modeling of the skew-tent map
The skew-tent map, like any other chaotic map, may suer from the inherent non-idealities of the integrated circuit fabrication process. This might cause the deforming of its shape, which can induce a divergence of trajectories or convergence to parasitic stable points. To be specic, a variation of the values of mp and mn may reduce the
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0
0.02 0.04 0.06
x(n)
Figure 3.9: Phase diagram of the skew-tent map simulink model forµ= 0.5
0 0.2 0.4 0.6 0.8 1
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
x(n)
x(n+1)
Figure 3.10: Phase diagram of the skew-tent map simulink model forµ= 1.9
number of points in the phase space visited by trajectories inside the map eectively limiting its entropy [13] or in the worst case, the trajectories may diverge, which would result in the elimination of chaotic behavior. A variation of the thresholdEtmay cause a
discontinuity at the point where the slopes meet each other which may cause a divergence of trajectories. These parameter errors are depicted in Figures3.11 and3.12.
x(n+
1)
x(n)
Figure 3.11: Eect of slope variation on the skew-tent map.
x(n+
1)
Et+e
x(n)
Figure 3.12: Eect of threshold variation on the skew-tent map.
The sources of these errors depend on the circuit architecture. As already mentioned in Chapter1, chaotic maps are implemented in either switched current (SI) or switched capacitor (SC) architectures. Thus, the mp and mn errors may come from variation
in either transconductance or capacitor ratios. Variations of Et come from comparator
osets.
The threshold and slope variations can be included in (3.1) as follows
xn+1 =
(µ+ep)(xn−(µ1 +er)) + 1 xn< µ1 +et (−µ−µ1 +ep)(xn−(1µ+er)) + 1 xn> µ1 +et
(3.3)
Where ex represents the errors introduced by non-idealities. The errors for each slope
are correlated with the value of µ as follows: ep =eµ and en =eµ−µ1. The correlation
0 0 -10 0 X
0 0 0 10 X
0 0 0 -10 X
Table 3.3: Eect of errors on the skew tent map II.
osets not related to µ. Tables3.2 to 3.6and Figures3.13 to 3.16show the behavior of
the map under dierent error conditions withµset to operate in chaotic regime.
0 0.2 0.4 0.6 0.8 1
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
x(n)
x(n+1)
Figure 3.13: Eect of threshold variation on the skew-tent map for ep = 1% and
en= 1%.
3.4 Design criteria
The results of the previous section paint a pretty bleak picture on the performance of the map. Almost any combination of non-ideal eects tends to destroy its chaotic dynamics. Further observation of the results, however, suggest a workaround this issue. Notice how in Tables 3.2 to 3.6, the map oscillates when the error on both slopes is negative (with one exception in Table3.4). Considering that the slopes' errors (ep and en) come
−18 −16 −14 −12 −10 −8 −6 −4 −2 0 2 x 1058 −18 −16 −14 −12 −10 −8 −6 −4 −2 0 2x 10
58
x(n)
x(n+1)
Figure 3.14: Eect of threshold variation on the skew-tent map foret=−10mV.
ep(%) en(%) et(mV) er(mV) map oscillation
-1 -1 10 0 X -1 1 10 0 X 1 -1 10 0 X
1 1 10 0 X
-1 -1 -10 0 X -1 1 -10 0 √ 1 -1 -10 0 X 1 1 -10 0 X
Table 3.4: Eect of errors on the skew tent map III.
ep(%) en(%) et(mV) er(mV) map oscillation
-1 -1 0 10 √ -1 1 0 10 X 1 -1 0 10 X
1 1 0 10 X
-1 -1 0 -10 √ -1 1 0 -10 √ 1 -1 0 -10 X 1 1 0 -10 X
Table 3.5: Eect of errors on the skew tent map IV.
transconductance ratios, this parameter can eectively function as an additional design variable.
The tests of Table3.4are repeated in Table3.7for an increased slope error. Notice how the map oscillates and therefore keeps its chaotic dynamics in every situation where both slopes have negative errors. This means that every divergent trajectory is forced back into the map. Table3.8further validates this assumption.
0 0.2 0.4 0.6 0.8 1 0
0.1
x(n)
Figure 3.15: Eect of threshold variation on the skew-tent map for ep = −1%,
en=−1%andet=−10mV.
−2.5 −2 −1.5 −1 −0.5 0 0.5 1
x 1027 −2.5
−2 −1.5 −1 −0.5 0 0.5
1x 10
27
x(n)
x(n+1)
Figure 3.16: Eect of threshold variation on the skew-tent map for ep = 1%, en =
−1%and et= 10mV.
ep(%) en(%) et(mV) er(mV) map oscillation
0 0 10 10 √ 0 0 -10 -10 √
Table 3.6: Eect of errors on the skew tent map V.
IC Design considerations are thus obtained from the mathematical modeling of the skew-tent map:
• From the bifurcation diagram, it can be seen that the value of the bifurcation
ep(%) en(%) et(mV) er(mV) map oscillation
-10 -10 10 0 √ -10 10 10 0 √ 10 -10 10 0 √ 10 10 10 0 X -10 -10 -10 0 √ -10 10 -10 0 √ 10 -10 -10 0 X 10 10 -10 0 X
Table 3.7: Eect of errors on the skew tent map VI.
ep(%) en(%) et(mV) er(mV) map oscillation
-10 -10 0 50 √ -10 -10 0 -50 √ -10 -10 50 0 √ -10 -10 -50 0 √ -10 -10 10 10 √ -10 -10 -10 -10 √ -10 -10 -50 -50 √ -30 -30 -10 20 √
Table 3.8: Eect of errors on the skew tent map VII.
• Normally, the designer aims at obtaining the maximum entropy from the oscillator.
This is done by setting the bifurcation parameter as close as possible toµ= 2 as
can be seen from the gradual rise ofλin the Lyapunov exponent diagram.
• In order to guarantee the chaotic dynamics of the map under the inuence of
non-idealities, a negative slope error must be taken into account. This is done by considering a certain negative error percentage in both slopes and setting it as the new value. Figure3.17shows this technique.
mp mps mn mns x(n+ 1)
Et
x(n)Figure 3.17: New slope valuesmpsand mns.
For example, settingµ= 1.9 would yield mp = 1.9 and mn= 2.11. Considering a
In this chapter a circuit implementation of the skew-tent map is introduced. Its validity is veried with behavioral modeling of electrical devices described by Verilog-A.
4.1 Block Based Circuit
Figure 4.1 shows the block based circuit for the skew-tent map. Two non overlapping clock signals (”o”and ”e”) drive the map's dynamics. The circuit is composed of three
major analog signal processing blocks and a digital control module. The rst two signal processing blocks are implemented as switched capacitor stages and the last one as agmC
stage. The digital control module produces the control signalz. The circuit requires a full
clock period to yield xn+1. Details for each stage are given in the following subsections.
x-Et m(z) (x-Et)
-sgn(z)
-sgn(z)
sgn(x-Et) Z
shift + half delay
digital control
scaling change of sign
signal dependent
x(n) [m(z) (x-Et)
-sgn(z)]
Figure 4.1: Block based skew-tent map oscillator.
4.1.1 Shift + half delay
The rst stage is a switched capacitor sample and hold as introduced by Gregorian [46] and shown in Figure4.2. During phaseo,CH is charged to
VCH =xn−Et. (4.1)
During phase e, CH delivers the previously stored charge to the output node. As the
name of the stage implies, the output is delayed by half a period.
Figure 4.2: Shift + half delay circuit.
4.1.2 Digital Control
A switched capacitor comparator as shown in Figure 4.3 encodes the sign of (4.1) in z
as follows,
z=
0, xn−Et<0 1, xn−Et>0
(4.2)
The value ofz is then delayed by a D ip-op. This will makez available during both
phases.
4.1.3 Signal dependent scaling
The stage depicted in Figure 4.4is a switched capacitor gain and adder circuit. During phasee,CP andCN are charged to (4.1). Charge inCY depends onz as follows,
Figure 4.3: Digital control.
VCY =
1, z= 0 φ=e
−1, z= 1 φ=o
(4.3)
During phaseo, the charge of eitherCP orCN is delivered toCT or to ground, depending
on the value of z. The ratios mp = CT/CP and mn = CT/CN are the positive and
negative slopes respectively. Considering CT=CY, the output of this stage is delayed
half a period and is as below,
V =
mp(xn−Et) + 1, z= 0 mn(xn−Et)−1, z= 1
(4.4)
4.1.4 Signal dependent change of sign
Agm−ccontinuous time stage as shown in Figure4.5realizes a change of sign as follows,
gm gm =
1 z= 0
−1 z= 1
(4.5)
The output of this stage yields the skew-tent map after one clock period as seen below.
xn+1=
mp(xn−Et) + 1 z= 0
−mn(xn−Et) + 1 z= 1
CY
Figure 4.4: Signal dependent scaling.
Figure 4.5: Signal dependent change of sign.
4.2 Behavioral simulation
The circuit is implemented in SPICE with Verilog-A. Verilog-A is a hardware design language for analog circuits and systems design [47]. Each device is described after their electrical model. Thus, for instance, switches are dened as a voltage-controlled conductance. Moreover, the models allow for the introduction of non-idealities as is the
0 0.2 0.4 0.6 0.8 1 0
0.1 0.2 0.3 0.4
x(n)
Figure 4.6: Phase portrait of the Verilog-A circuit.
0 500 1000 1500 2000
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
(n)
x(n)
Figure 4.7: Time series of the Verilog-A circuit.
4.2.1 Behavioral simulation with non-idealities
Oset is typically the main non-ideality in these type of circuits. The expected output of any comparator, OPAMP, or OTA stage can be modied by a small value. Often, when characterizing such circuit blocks before the system implementation, said oset value falls in the accepted range. However, due to the closed-loop nature of the discrete chaotic oscillator, the error will be propagated throughout several iterations. Even when fully dierential architectures are used, this error can reach a level enough to cause a divergence on the map's trajectories. It is for this reason that the focus of the following tests are on the oset of the devices. By making the circuit robust against oset, it
is expected that it will be robust against other non-idealities that may bring about divergence in trajectories such as devices non-linearity and charge injection.
As presented in Chapter 3, one of the criterion for the design of a skew-tent map based circuit consists on setting the slopes on the circuit implementation to a value that includes an error (design safeguard). Thus, in the presented switched capacitor architecture this error will be included in the values of the capacitor ratios. Simulations where made for
µ = 1.9. Figures 4.8 and 4.9 show results of simulation (200 iterations) considering a
10mV oset for all OPAMPs in the circuit. Figure 4.8 depicts the expected behavior, all trajectories stay inside the map. Notice the opposite case in Figure 4.9, the phase diagram looks less dense, this is due to trajectories diverging after a few iterations.
x
(n+
1
)
x(n)
Figure 4.8: Phase portrait of the circuit considering negative slope error.
x
(n+
1
)
Figure 4.9: Phase portrait of the circuit not considering negative slope error.
Figures4.10and4.11shows the results for a 2000 iterations simulation considering oset in every OTA and OPAMP. A negative error of 5% is included in the capacitor ratios values for Figure 4.10. The circuit with safeguard is able to maintain every trajectory
x(n)
Figure 4.10: Phase portrait of the circuit considering negative slope error.
x
(n+
1
)
x(n)
Figure 4.11: Phase portrait of the circuit not considering negative slope error.
4.3 NIST test results
200 kbits were generated from the behavioral implementation of the skew-tent map oscil-lator. They were divided into groups of 10 kbits and tested with the NIST randomness suite. The results are presented in Table 4.1. A test is passed if its P-value is greater than 0.01. It can be seen that 10 out of 14 tests are passed. This suggests what was expected: the proposed circuit based on the skew-tent map can be used as the basis of a true random number generator.
Test P-value Proportion of passed tests Frequency 0.739918 19/20
Block Frequency 0.803787 20/20 Cumulative Sums 0.739918 20/20 Cumulative Sums 0.834308 20/20 Runs 0.000000 1/20 Longest Run 0.035174 20/20
Rank 0.048716 19/20 FFT 0.275709 19/20 Overlapping Template 0.122325 20/20 Universal 0.017912 0/20 Approximate Entropy 0.000000 0/20 Serial 0.000000 4/20 Serial 0.122325 19/20 Linear Complexity 0.275709 19/20
Table 4.1: NIST test suite 800-22 results for chaotic oscillator behavioral implemen-tation.
This chapter presents a true random number generator based on the chaotic oscillator introduced in Chapter 4. The behavioral abstractions of the oscillator were replaced by electrical devices in TSMC 180nm process technology biased by VDD =−VSS = 1.65V
operating at 2 MHz. The design criteria introduced in Chapter3was considered in order to maintain the chaotic dynamics of the oscillator. A post-processing stage is used to remove possible statistical bias. Finally, the validity of the TRNG is veried with the NIST randomness test suite.
5.1 True random number generator circuit
The block diagram for the proposed TRNG is shown in 5.1. It is based on two chaotic oscillators whose purpose is to nonlinearly amplify their respective initial condition set by thermal noise. The comparator blocks sample the output of the oscillators and set a threshold in order to produce a binary output. The circuit that performs this operation is the same as the digital control stage introduced in Chapter 4 shown again in Figure
5.2.
The simplest form of the XOR corrector is implemented as the basis for the post pro-cessing stage. The truth table for the corrector operation is shown in Table5.1. In the statistical sense, the XOR inputs (random input streams) have an ideal mean value of 1/2. However, the mean value of a practical implementation is never the ideal one. The goal of the corrector is to reduce this dierence from the mean value [48]. Equation (5.1) shows this operation,
chaotic
oscillator
chaotic
oscillator
comparator comparator
post-processing
Figure 5.1: True Random Number Generator Block Diagram.
CP
Figure 5.2: Comparator circuit.
X Y Output 0 0 0 0 1 1 1 0 1 1 1 0
Table 5.1: Truth table of the post processing stage.
E(X⊗Y) = 1
2 −2(E(X)− 1
2)(E(Y)− 1 2)−(
1
2)corr(X, Y) (5.1)
where X and Y are independent random variables. It can be seen that as long as the correlation between both streams is small, the bias will tend to the ideal value. The main advantage from this post processing scheme is its simplicity and the fact that it keeps the bit rate of the input streams.
5.2 Circuit design
A folded cascode p-input operational amplier as shown in Figure 5.3 was used for the following four stages: shift plus half delay, signal dependent scaling, digital control and comparator. The input dierential pair (M1,M2) is followed by common gate stages (M3, M4), current sources (M9,M10) and a self biased cascode current mirror (M5-M8).
M
11M
1M
2M
9M
10M
3M
4M
7M
5M
6M
8V
DDV
SSVB1
VB2
VB3
VB4
Figure 5.3: Folded cascode p-input op amp.
Transistor sizes are shown in Table 5.2. Frequency response of the op amp is shown in Figure5.4.
Figure 5.4: Frequency response of the folded cascode p-input op amp.
W( µm ) L (µm)
MN 2 .7
MP 6 .7
Table 5.3: Transistor sizing for the CMOS complementary switch.
5.2.2 Switch
A complementary switch as shown in Figure 5.5 was used as the switching element in the circuit. The sizing of the switches is the same throughout the circuit and is as shown in Table 5.3
MP MN
the gmC based signal dependent change of sign continuous time stages. The circuit is
shown in Figure 5.6 and is based on the one introduced in [49]. It is composed of a complementary input stage (M1-M4) and a folded cascode summing stage (M5-M12).
The circuit is biased by a couple of current sources (IBias1=IBias2=30µA). Source
degeneration (SD) is achieved with resistors (R1=R2=R3=R4=1kΩ) connected at the
source of each transistor in the input pairs. The goal of the SD resistors is to increase the transconductance of the pair in order to obtain a wider linear region. Transistor sizes are given in Table5.4. The DC transfer curve of the op amp is shown in Figure 5.7.
M9
M10
M3 M4
M7
M5 M
6 M8 VSS VB1 VB2 VB3 IBias1 IBias2 M1 M2 R1 R3 R2 R4 M11 M12
Figure 5.6: Complementary input folded cascode op amp.
5.2.4 Behavioral blocks
The ip op circuit in the digital control stage was implemented as a behavioral abstrac-tion described by Verilog-A as shown in Appendix G. The described circuit is a double edge triggered D ip op. Transient simulation results are shown in5.8.
Figure 5.7: Complementary input folded cascode op amp i/o transfer characteristics.
5.3 Chaotic oscillator simulation results
Transient simulation results at operation frequency (2M Hz) and bifurcation parameter
set to µ= 1.99 (Ct=300fF, Cp=510fF, Cn=520fF) for each stage of the CMOS chaotic
oscillator considering a sine input are presented in Figures5.9to 5.11. The output of the chaotic oscillator is shown in5.12.
5.4 TRNG NIST tests results
The TRNG circuit was tested with the NIST randomness test suite in order to validate the suitability of the proposed circuit as a true random number generator. A test is passed if its P-value is greater than 0.01. First, a stream of 50 kbits divided in groups of 5 kbit was generated from behavioral implementation of the TRNG, NIST tests results are presented in Table 5.5.
Results that consider every major block (amplier) as a CMOS implementation and switches described with Verilog-A are shown in Table5.6. 100 kbits divided in groups of 10 kbits were generated for this test.
Figure 5.8: Double edge ip op D transient.
Shift + half delay output
t(s)
0.0 500n 1u 1.5u 2u 2.5u 3u 3.5u 4u 4.5u 5u 5.5u 6u 6.5u 7u 7.5u 8u 8.5u 9u 9.5u 10u
(V)
−1.5 −1.0 −0.5 0.0 0.5 1.0 1.5
(V) : t(s) v(xn)
v(b)
Figure 5.9: Test sine input (yellow), output of the shift + half delay stage (orange).
NIST test results for a 100 kbit stream divided in groups of 10 kbits from the full CMOS implementation are shown in Table5.7.
NIST test results show that the most basic tests are passed for all implementations. The higher level (Verilog-A) implementation is superior in the sense that most tests are passed (12 out of 14). On the other hand, the lower level (CMOS) implementation passes 7 out of 14 tests. This is clearly due to non-idealities inherent in electrical models. Finally, the mid level (CMOS/Verilog-A mix) tests results suggest that a more thorough design may greatly improve the performance of the lower level implementation.
Signal dependent scaling
t(s)
0.0 500n 1u 1.5u 2u 2.5u 3u 3.5u 4u 4.5u 5u 5.5u 6u 6.5u 7u 7.5u 8u 8.5u 9u 9.5u 10u
(V)
−1.5 −1.0 −0.5 0.0 0.5 1.0 1.5
(V) : t(s) v(7)
v(b)
Figure 5.10: Input from previous stage (yellow), output of the signal dependent scaling stage (orange).
Signal dependent change of sign
t(s)
0.0 1u 2u 3u 4u 5u 6u 7u 8u 9u 10u
(V)
−1.5 −1.0 −0.5 0.0 0.5 1.0
(V) : t(s)
v(7)
v(12)
Figure 5.11: Input from previous stage (yellow), output of the signal dependent change of sign stage (orange).
0 50 100 150 200 −0.1
0 0.1 0.2 0.3 0.4
(n)
x(n)
Figure 5.12: Output of the CMOS chaotic oscillator.
Test P-value Proportion of passed tests Frequency 0.350485 10/10
Block Frequency 0.911413 10/10 Cumulative Sums 0.213309 10/10 Cumulative Sums 0.350485 10/10 Runs 0.350485 9/10 Longest Run 0.122325 10/10
Rank 0.122325 10/10 FFT 0.739918 10/10 Overlapping Template 0.534146 10/10 Universal 0.000000 0/10 Approximate Entropy 0.000000 1/10 Serial 0.534146 10/10 Serial 0.213309 10/10 Linear Complexity 0.350485 10/10
Test P-value Proportion of passed tests Frequency 0.739918 10/10
Block Frequency 0.534146 10/10 Cumulative Sums 0.213309 10/10 Cumulative Sums 0.911413 10/10 Runs 0.350485 10/10 Longest Run 0.350485 10/10 Rank 0.213309 10/10 FFT 0.534146 10/10 Overlapping Template 0.035174 10/10 Universal 0.000000 0/10 Approximate Entropy 0.000003 6/10 Serial 0.122325 10/10 Serial 0.122325 9/10 Linear Complexity 0.066882 10/10
Table 5.6: NIST test suite 800-22 results for the CMOS/Verilog-A TRNG.
Test P-value Proportion of passed tests Frequency 0.350485 9/10
Block Frequency 0.122325 9/10 Cumulative Sums 0.911413 10/10 Cumulative Sums 0.350485 10/10 Runs 0.534146 9/10 Longest Run 0.008879 9/10 Rank 0.000000 0/10 FFT 0.000000 1/10 Overlapping Template 0.000000 0/10 Universal 0.000000 0/10 Approximate Entropy 0.000000 0/10 Serial 0.000000 0/10 Serial 0.000000 0/10 Linear Complexity 0.213309 10/10
are better suited for integrated circuit implementation than the most commonly used ones. Design guidelines were successfully obtained from mathematical modeling that considered non-idealities. These guidelines are fundamental for the subsequent IC design for they provide the necessary information to tune and adjust the circuit to operate at the maximum available entropy in the presence of non-ideal phenomena that may cause the elimination of chaotic behavior.
A new mixed signal switched capacitor chaotic oscillator circuit based on the skew-tent map was introduced. It is composed of three switched capacitor stages and agmC stage.
The oscillator is relatively simple and most sub-circuit blocks can be reused throughout the circuit's dierent stages.
A new true random number generator based on the skew-tent map chaotic oscillator was presented. It consists of two oscillators and a simple post-processing. The proposed scheme is less complex than most of the reported discrete time chaotic TRNGs. Fur-thermore, the post-processing stage maintains the bitrate of its inputs. The scheme was implemented in TSMC 180nm process technology.
Simulation results show that the CMOS implementation of the TRNG passes the most basic NIST tests while the mixed CMOS/Verilog-A implementation passes most of them. Future work might consider a more sophisticated post-processing stage in order to obtain better results. Finally, a dierential architecture variant of the proposed oscillator may also be considered in order to achieve a better performance.
Lyapunov exponent MATLAB script
lyap=zeros(1,1000); j=0;
for(r=0.001:0.001:2) l=1/r+.005; xn1=rand(1); lyp=0; j=j+1;
ep=-.01*r; en=-.01*r/(r-1); %
mp=r+ep; mn=r/(r-1)+en;
for(i=1:10000) xn=xn1; % skew tent
if (xn(i)-l)<=0.0 % xn1(i+1)=r*xn(i);
xn1(i+1)=mp*(xn(i)-l)+1; end
if (xn(i)-l)>0.0
% xn1(i+1)=(r)/(r-1)*(1-xn(i)); xn1(i+1)=-mn*(xn(i)-l)+1;
end
end end
%calculate lyapunov lyp=lyp/10000; lyap(j)=lyp; end
r=0.001:0.001:2; plot(r,lyap);
Bifurcation diagram MATLAB
script
a = 0.01:0.005:2; %interval of parameter x0 = rand(1); %initial condition N=500; %number of iterations
x(1) = x0; %the first entry is the initial condition %computation of the orbit
figure(2);hold on; ep=0;en=0;
for i=1:length(a) for j=1:N
l=1/a(i)-.01; ep=-.1*a(i); en=-.1*a(i)/(a(i)-1); mp=a(i)+ep;
mn=a(i)/(a(i)-1)+en;
% skew tent,
if (x(j)-l)<=0.00 % x(j+1)=a(i)*x(j)+1;
% mp=a(i)+ep;
x(j+1)=mp*(x(j)-l)+1;
end hold off
Entropy MATLAB script
mu=0:0.005:1.9; % l=1/mu;
x0=rand(1); % Initial condition N=10000;
x(1)=x0;
for i=1:length(mu) l(i)=1/mu(i); for ic=1:N
% l(i)=1/mu(i);
if x(ic)>=0&&x(ic)<=l(i) x(ic+1)=mu(i)*x(ic);
end
if x(ic)<=1&&x(ic)>l(i)
x(ic+1)=(mu(i))/(mu(i)-1)*(1-x(ic)); end
end
g(i)=entropy(histogram(x)); end
plot(mu,g) h=histogram(x); entropy(h)
input vref, vspply_p, vspply_n; inout vout, vin_p, vin_n;
electrical vout, vref, vin_p, vin_n, vspply_p, vspply_n; parameter real gain = 100e3;
parameter real freq_unitygain = 100.0e6; parameter real rin = 1e6;
parameter real vin_offset = 0.0; parameter real ibias = 0.00; parameter real iin_max = 100e-6; parameter real slew_rate = 0.5e6; parameter real rout = 80;
parameter real vsoft = 0.1; real c1;
real gm_nom; real r1; real vmax_in; real vin_val; electrical cout; analog begin
@ ( initial_step or initial_step("dc") ) begin c1 = iin_max/(slew_rate);
gm_nom = 2 * 3.1416 * freq_unitygain * c1; r1 = gain/gm_nom;
vmax_in = iin_max/gm_nom;
end
vin_val = V(vin_p,vin_n) + vin_offset; // Input stage.
I(vin_p, vin_n) <+ (V(vin_p, vin_n) + vin_offset)/ rin; I(vref, vin_p) <+ ibias;
I(vref, vin_n) <+ ibias; // GM stage with slewing
I(vref, cout) <+ V(vref, cout)/100e6; if (vin_val > vmax_in)
I(vref, cout) <+ iin_max; else if (vin_val < -vmax_in) I(vref, cout) <+ -iin_max; else
I(vref, cout) <+ gm_nom*vin_val ; // Dominant Pole.
I(cout, vref) <+ ddt(c1*V(cout, vref)); I(cout, vref) <+ V(cout, vref)/r1; // Output Stage.
I(vref, vout) <+ V(cout, vref)/rout; I(vout, vref) <+ V(vout, vref)/rout; // Soft Output Limiting.
if (V(vout) > (V(vspply_p) - vsoft))
I(cout, vref) <+ gm_nom*(V(vout, vspply_p)+vsoft); else if (V(vout) < (V(vspply_n) + vsoft))
I(cout, vref) <+ gm_nom*(V(vout, vspply_n)-vsoft); end
output out;
electrical in,out,clk; real clka,cond;
analog begin clka=V(clk); if (clka<=.5) cond=1e-9;
else if (clka>.5) cond=1;
I(in,out)<+V(in,out)*transition(cond,0,10p); end
endmodule
OTA Verilog-A code
module nlota(ip,in,o); output o;
input ip,in;
electrical ip,in,o;
parameter real eos=.1,id=.0005,vod=.2,lambda=1.56; real va,gnl,gm,rout;
analog begin
//@(initial_step) begin gm=id/vod;
//end
va=V(ip,in)-eos;
rout=1/((lambda)*(id));
gnl=gm*(va-(va*va*va)*1/(vod*vod)*1/8); I(o) <+ gnl;
end endmodule
output q,qbar;
voltage q, qbar, clk, d;
parameter real tdelay = 0n from [0:inf), ttransit = 5n from [0:inf),
vout_high = 1.65,
vout_low = 0 from (-inf:vout_high), vth = .5;
integer x; analog begin
@(initial_step) x = 0;
@(cross(V(clk) - vth, 0.0 )) x = (V(d) > vth);
V(q) <+ transition( vout_high*x + vout_low*!x, tdelay, ttransit ); V(qbar) <+ transition( vout_high*!x + vout_low*x, tdelay, ttransit ); end
endmodule
XOR Verilog-A code
module xor_va(in1,in2,out); input in1,in2;
output out;
electrical in1,in2,out; real Vin1,Vin2,vout; parameter real trise=10f, tfall=10f,
vouthigh=1, voutlow=0;
analog begin Vin1=V(in1); Vin2=V(in2);
if (Vin1<=.5) begin if (Vin2<=.5)
vout=voutlow; else
vout=vouthigh; end
else if (Vin1>.5) begin
if (Vin2<=.5) vout=vouthigh; else
vout=voutlow; end
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