with higher complication forces us to enhance the performance, area, efficiency and practicality of arithmetic **logic** **circuits**. Several efforts are targeted on the development of adder styles [4]. Since the utilization of carry look-ahead principle for **high**-**speed** arithmetic units, one in all, the challenges in VLSI processor style these days is structured for constructing CLA **circuits**, exactly for the 8-bit **circuits** while not limiting the purposeful flexibility. A coffee power **high** performance FTL circuit technique is projected in [5] for reducing power dissipation and decreasing propagation delay in domino **logic**. The low power FTL dynamic **logic** is achieved with the help of feed through dynamic **CMOS** **logic** structure [6]. Wang, Tsai [7] used the 8-bit CLA victimization- the dual-Vt domino **logic** blocks that are organized in a very PLA- like manner and synchronously triggered. It is enforced on chemical element to verify the facility reduction also because of the preservation of **high** speeds [8]. Proposed an 8-bit pipelined CLA victimization- the dual- Green Mountain State domino **logic** blocks to scale back the facility dissipation. Dual-Vt Domino **Logic** **Circuits** foreseen for reducing sub-threshold discharge current in domino **logic** **circuits** is projected in [9]. Sleep switch twin threshold voltage domino **logic** with reduced sub-threshold **logic** gate compound discharge current is projected and tried in [10]. The **high** **speed** arithmetic circuit obtained victimization FTL **logic** in [11]. Normally, domino **CMOS** **logic** is widely employed in **high** performance integrated **circuits**. It reduces the device count and chemical element space, and improves performance in comparison to the quality totally complementary static **CMOS** **logic** [12].

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TABLE II represents the truth table of proposed full adder. If we compare TABLE I and TABLE II of standard and proposed full adder, the functionality achieved by substituting XOR gate in place of OR gate is same as standard full adder. Therefore, XOR gate can be used to generate final CARRY output. Now the proposed and standard full adder **logic** **circuits** are implemented using **CMOS** **logic** in Cadence Virtuoso tool to compare the average power and delay generated. The **circuits** are implemented in 180nm technology with supply voltage as 1.8V.

The second adder is complementary pass transistor **logic** (CPL) uses 32 transistors with swing restoration. Most CPL gates can have an complexity in interconnection at the layout level with the increase in power and delay. For low power applications Pass Transistor **Logic** (PTL) is best suitable technique and explanation was given in .The advantage of Pass Transistor **Logic** (PTL) is that either PMOS or NMOS is enough to implement a complete design [6]-[8] and so number of transistors gets decreased and also smaller input loads, especially for NMOS network and also by this PTL we can eliminate short circuit energy dissipation.

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The wish to improve the performance of **logic** **circuits**, once based on traditional Complementary Metal Oxide Semiconductor (**CMOS**) technology, resulted in the development of many **logic** design techniques during the last two decades. One form of **logic** that is popular in low- power digital **circuits** is Pass Transistor **Logic** (PTL). Formal methods for deriving pass-transistor **logic** have been presented for n-channel Metal Oxide Semiconductor Field Effect Transistor (NMOS). They are based on the model, where a set of control signals is applied to the gates of nMOS transistors. Another set of data signals are applied to the sources of the n-transistors. Some of the main advantages of PTL over standard **CMOS** design are 1) **high** **speed**, due to the small node capacitances; 2) low power dissipation, as a result of the reduced number of transistors; and 3) lower interconnection effects due to a small area. But the implementation of PTL has two basic problems: 1) slow operation at reduced power supply as the threshold voltage drop across the single channel pass transistor results in low drive current, 2) the **high** input voltage level at the regenerative inverter is not V dd , the p-channel

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Abstract—A new design of adiabatic circuit, called Energy Efficient Adiabatic **Logic** (EEAL) is proposed [1]. In adiabatic **logic**, which dissipates less power than static **CMOS** **logic**, have been adiabatic **circuits** called energy efficient adiabatic **logic** introduced as a promising new approach in low power circuit design[2]. In this paper, my primary aim is to improve power delay product (PDP) of the proposed adiabatic **circuits** as compared with conventional **CMOS** **circuits**. In this paper work, we use two phase split level sinusoidal power supply which is used for low power **high** **speed** adiabatic **circuits** and diode is replaced by MOS transistor at charging and discharging path whose gate is controlled by power clock. By using this technique power dissipation of the diode is eliminated. In this paper we have designed and simulated EEAL Based Master-Slave JK Flip Flop, and EEAL Based 3- bit Counter .All the simulation in this paper have been implemented by VIRTUOSO SPECTRE simulator of cadence with the 0.18 micrometer UMC technology MOS transistor model under 1.8- volts peak to peak split level sinusoidal power clock supply. From the simulation result, we have find that proposed **logic** **circuits** can save significant amount of energy compared to **CMOS**.

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Dynamic **logic** style is popular due to its fast processing **speed** and less power dissipation in **high** performance circuit design as compared to static complementary metal-oxide-semiconductor (**CMOS**) **logic** style. However, dynamic **logic** has less noise tolerance and charge sharing problems and hence it is not widely accepted for all **high** **speed** applications. As a consequence, a domino **logic** circuit is proposed for applications such as **high**-**speed** adder, comparator and arithmetic and **logic** unit (ALU) design. Furthermore, the proposed domino **logic** circuit provides multi standard advantages such as less propagation delay, less power dissipation and **high** fan out capability. The proposed circuit is simulated and tested in T SPICE with 45 nm technology. Moreover, it is compared with other domino **logic** **circuits** in terms of power dissipation and propagation delay.

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After comparing results of PFAL and ECRL basic gates with **CMOS** gates we got good improvement in results. As industry demands devices with low power and fast operating ECRL and PFAL **logic** gates are most suitable and useful in any circuitry. This basic gates ca be used in building adder, full adder, multiplexer, flip-flop. Here we have made 2:1 mux using PFAL and ECRL gate which is very fast in operation and less power consuming.

The rapid development of portable digital applications, the demand for increasing **speed**, compact implementation and low power dissipation triggers numerous research efforts. The wish to improve the performance of **logic** **circuits**, once based on traditional **CMOS** technology resulted in the development of many **logic** design techniques during the last two decades. In the era of mobile electronics we require digital **circuits** with **high** **speed**, low circuit density and low power dissipation Modifications are performed on conventional **CMOS** design which has **high** noise immunity and no static power dissipation. Many researches are going on this area [1].

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This paper describes a **high** **speed** boosted **CMOS** differential **logic** which is used in ripple carry adders. The proposed **logic** style improves switching **speed** by boosting the gate–source voltage of transistors along timing-critical signal paths. Test sets of **logic** gates were designed in a 0.18-μm **CMOS** process, whose comparison results indicated that the energy–delay product of the proposed **logic** style was improved by up to 50% compared with conventional **logic** styles at supply voltage of 1.8V. The experimental result for 32 bit ripple carry adder using the proposed **logic** style revealed that the addition time is reduced as compared with the conventional **CMOS** **circuits**.

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The necessity to design SET based **logic** **circuits** with its simulation besides fabrication oriented research show tremendous impact to replace present day **CMOS** technology in near future. Eminent Researchers have comprehended this importance and thus have now stirred their focus on realizing application oriented SET design. Undoubtedly, it is a much new approach and very few of the Researchers have tried their hands in this sector. Employing SET technology in real life applications is not only thrilling but also a challenging field to explore. Accomplishment of SET **logic** devices for real time circuit realization is still lagging far behind; even though it is a rising field of low dimensional device structure oriented research that has opened a new horizon for present and future device application. In the present day to deal with the desire of low power consuming **high** **speed** nano

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Abstract :- The need for **high** **speed** digital **circuits** became more prominent as portable multimedia and communication applications incorporating information processing and computing. The drawback of modern computers lead to the deterioration in performance of arithmetic operations such as addition, subtraction, division, multiplication on the aspects of carry propagation time delay, **high** power consumption and large circuit complexity. This system explores the carry free n digits addition/subtraction as the carry propagation delay is most important factor regarding the **speed** of any digital system. In this paper, Quaternary signed digit (QSD) numbers whose radix is 4 are used in arithmetic operations to achieve the carry free arithmetic operations. The range of QSD number is from -3 to 3.In any n digit QSD number ,each digit can be represented by a number from the digit set [-3,-2,-1,0,1,2,3]. In this paper , we are improving the performance of the QSD addition by apply reversible **logic** gate . QSD addition is performing for the 4 bit,8 bit . In the normal condition QSD adder gives the **high** delay performance . We have to reduce the delay of the 4 bit,8 bit QSD adder . For reduce the delay we apply pipelining and Peres reversible **logic** gate . Pipelining and Peres reversible gate will be able to reduce the delay of the 4 bit , 8 bit QSD adder .

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which has a lower leakage and higher noise immunity without dramatic **speed** degradation for wide fan-in gates. In this domino circuit a chain of evaluation network uses well known stacking effect technique to reduce the leakage. The stacking effect and current mirror makes the circuit more noise immune and considerably improves the Power Delay Product (PDP) as compared to the other existing domino **logic**. The leakage current is also decreased by exploiting the footer transistor in diode configuration, which results in increased noise immunity. DCLCR domino circuit reduces the leakage power consumption by maintaining the same level of delay. By connecting the gate of the transistor M K1 to its drain power is

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As per Landauer, for irreversible **logic**, each bit of information lost generates kTln2 Joules of heat energy, where k is Boltzmann's constant and T is absolute temperature at which the computation is performed. For room temperature T, the amount of heat dissipated for one bit is small i.e. 2.9×10- 21 J. The current processors, first of all dissipate 500 times this amount of heat every time a bit is lost. Secondly, assuming every transistor out of more than 4×107 dissipates heat at the processor frequency of 2GHz, the figure becomes 4×1019*kTln2 J/sec. Bennett [9] showed that if a computation is carried out in Reversible **logic** zero energy dissipation is possible, as the amount of energy dissipated in a system is directly related to the number of bits erased during computation. The design that does not result in information loss is irreversible. The number of outputs in a reversible gate or circuit has the same as the number of inputs. While constructing reversible **circuits** with the help of reversible gates, some restrictions should be strictly maintained:

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It exists in literature a relatively small number of func- tion synthesizer **circuits** implemented in **CMOS** technol- ogy [4,33,44-46], these applications being dedicated to the realization of a limited number of mathematical functions. In [44], the approximation of the implemented function can be obtained by adding the weighted output currents of a number of basic building blocks, built around a basic current squarer, and a constant current, the circuit pre- senting the disadvantage of a relatively large complexity. The circuit proposed in [45] is based on approximating the required function using the first three terms of its Tay- lor series expansion. The approximations can be imple- mented by adding the output currents of a weighted current square, a weighted current amplifier (or attenu- ator), and a constant current. The errors are mainly caused by the small value (two) of the approximation order and, in consequence, they are relatively large. Add- itionally, from the same reason, the range of the input

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Abstract: Class-AB **circuits**, which are capable of dealing with currents several orders of magnitude larger than their quiescent current, are good candidates for low-power and **high** slew-rate analog design. This paper presents a novel topology of a class AB Flipped Voltage Follower (FVF) that has better slew rate and the same power consumption as the conventional class-AB FVF buffer previously presented in literature. It is thus suitable for low-voltage and low-power stages requiring low bias currents. These buffers have been simulated using 0.5 µm **CMOS** Technology models provided by IBM. The buffer consumes 16 µA from a 0.9 V supply and has a bandwidth of 52 MHz with an 18 pF load. It has a slew rate of 10.3 V/µs and power consumption of 36 µw.

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is in consumption power and falling and rising times so this subject looks simple due to the difference in NMOS and PMOS transistors **speed** .After the simulation, the layout of circuit is drawn. By the post simulation result along with a few corrections have achieved in sizes that the circuit has an accurate operation. Simulation results are performed by HSPISE based on 0.18µm **CMOS** technology. The power supply is 1.8v. The 5% variation of power supply is tested. This design is also compatible with transistor size 10% variation. In the table II, comparison of similar works and their results have been there. The snapshot of the waveforms at 1.8v is shown in figure 5.

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"Adiabatic" is taken from a Greek word and it describes thermodynamic process that shows no energy exchange with the surroundings. In real-time systems such perfect processes cannot be obtained due to some factors which causes dissipation. But dissipation can be decreased by reducing the operational **speed** and conditional transistor switching. It is also called as "Energy recovery **CMOS**", since it reuses the stored energies in the load capacitors. The ideal condition of the adiabatic process is achieved when the switching process is retarded. Practically energy dissipation cannot be reduced to be zero because the charge cycle is always associated with an adiabatic and a non-adiabatic component. The conservation of energy is achieved in the circuit rather than dissipation.

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In order to reduce the dynamic power, an alternative approach to the traditional techniques of power consumption reduction, named adiabatic switching, has been proposed in the last years. In such approach, the process of charging and discharging the node capacitances is carried out in a way so that a small amount of energy is wasted and a recovery of the energy stored on the capacitors is achieved. In literature, various kinds of adiabatic **circuits** proposed all of them can be grouped into two fundamental classes: fully adiabatic **circuits** and quasi- adiabatic or partial energy recovery **circuits**. In the first class, in particular working conditions can consume asymptotically zero energy for operation, the large area occupation and the design complexity make these **circuits** not competitive with traditional **CMOS** where as in second class **circuits** designed to recover large portion of the energy stored in the circuit node capacitances. This energy loss drawback however allows a good trade-off between circuit complexity and then area occupation.In this paper different circuit are presented, and comparison of conventional **CMOS** adder **circuits** [1][2][4][5][6], 2PASCAL [10] ,and also comparison of adiabatic families[3][7][8][9] is done. In this work we analyzed the performance of conventional and adiabatic adder circuit’s in-terms of power consumption.

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