system-on-chip (SoC)

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Control automático adaptativo por medio del ciclo MAPE-K, en el Internet de las cosas, usando el System On Chip ESP32

Control automático adaptativo por medio del ciclo MAPE-K, en el Internet de las cosas, usando el System On Chip ESP32

La elecci´ on del SoC ESP32 result´ o satisfactoria en la creaci´ on de un sistema de control autom´ atico basado en el Internet de las Cosas. El uso de sus ADCs y DACs permiti´ o rea- lizar un control el´ ectrico en el rango de voltaje seleccionado. La programaci´ on basada en el IDE ARDUINO permiti´ o una compaginaci´ on con el lenguaje C++ lo que ampl´ıa la compatibilidad de los desarrollos realizados para el ESP32 al ESP8266. El shield ESP32 weekworm, ver figura 7-3, dot´ o a los primeros experimentos de la versatilidad necesaria para realizar cambios r´ apidos de conexi´ on entre las plantas de control y los otros equipos electr´ onicos probados. El siguiente shield ESP32 Devkitv1, mostrado en figura 7-4, se desa- rroll´ o para construir un tarjeta de control electr´ onico m´ as acorde a las necesidades de un entorno industrial, bajo el rango de voltaje de 0V a 3,3V . Las protecciones basadas en el amplificador operacional Lm324, revisar figura 7-6, trabajaron seg´ un lo esperado y evitaron da˜ nos durante las experimentaciones. La toma de los datos de la salida del DAC, por medio de otro ADC, estudiar figura 7-7 permiti´ o realizar las tareas del ciclo MAPE-K de forma m´ as acertada. Otro aspecto a resaltar en la elecci´ on del SoC ESP32 es su reducido pre- cio con respecto a otros sistemas con similares caracter´ısticas, El System On Chip ESP32 se puede conseguir por un valor de $40,000 pesos en el mercado colombiano, en tanto que otras soluciones como la Raspberry pi o similares en valores superiores a los $100,000 pesos.

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System On Chip para la reconstrucción de señales con sensado compresivo

System On Chip para la reconstrucción de señales con sensado compresivo

En la comunicaci´ on dentro del SoC el maestro AXI es siempre quien inicia la tran- sacci´ on, mientras que el esclavo responde a ella. Esto se cumple para procesos de escritura y lectura por igual. La interfaz utiliza la arquitectura de canales como se ve en la Figura 4.3. Para los protocolos que utilizan mapeo de memoria (AXI4-Full y AXI4-Lite), la informaci´ on puede moverse simult´ aneamente en ambas direcciones; ya que existen conexiones de datos y direcciones separadas. A nivel de Hardware, AXI4 permite diferente se˜ nales de clock para cada par mestro/esclavo. Adem´ as, los protocolos admiten la inserci´ on de etapas de pipeline para asistir con requerimien- tos de timing (Sincronizaci´ on temporal). Por otra parte, AXI-Stream define un solo canal para datos, ya que puede realizar transmisi´ on sin interrupciones en un ´ unico sentido (Figura 4.4). A pesar de ser un protocolo punto a punto, cuando existen va- rios dispositivos AXI pueden ser todos conectados entre s´ı utilizando una estructura llamada AXI-Interconnect. Existe un bloque IP de Xilinx que cumple esta funci´ on, incluyendo varias interfaces maestro y esclavo para rutear distintas transacciones de datos [68].

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Desarrollo de aplicaciones basadas en Linux Embedded en una arquitectura basada en Cyclone V SoC (System on Chip) de Altera

Desarrollo de aplicaciones basadas en Linux Embedded en una arquitectura basada en Cyclone V SoC (System on Chip) de Altera

Before installing it, locate the downloaded Quartus II file. Right click on it and access to Properties. On the Permissions section, select the box "Allow executing file as a program". If we do not select it, Ubuntu OS will try to open this file instead of executing it, so it will not find any application to open it. After that, to begin installation we have to execute the file with root user privileges (sudo command); otherwise, we will see a message indicating that there were troubles with the installation (for example, the uninstaller file will not be created correctly). Thus, despite these errors may not have a negative impact on the tools operation, we will execute it as root to make sure that everything is installed correctly so we will not have unexpected issues afterwards. Open a terminal in Ubuntu, navigate to the directory where the file is (it will be stored on "/home/<user>/Downloads" by default) and execute the following command:

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Integración de internet de las cosas en sistema embebido system on chip, con aplicación a domótica

Integración de internet de las cosas en sistema embebido system on chip, con aplicación a domótica

En muchas investigaciones encontradas, se ha abordado el tema de Internet de las Cosas, como una tendencia de investigación, estas investigaciones las han realizado tocando los diferentes aspectos que lo componen, como por ejemplo: definiciones de IoT, conceptos relacionados, Arquitecturas, Tecnologías, Protocolos, gama de aplicaciones, entre otros aspectos; no en forma global, sino independiente o asociando algunos de los aspectos; la mayoría han sido desarrollados teóricos y de fundamentación, se empieza a trabajar con 802.15, 802.11, GSM y otros protocolos, pero no se enfatiza en conectividades de corto alcance integradas en el mismo chip como soluciones IoT, aunque el 802.11 promete en un futuro cercano, ser de mucha más baja potencia al momento de la presentación de esta propuesta se evalúo la utilización de una plataforma de alto rendimiento, con capacidades de desempeño interesantes, relevantes en una realidad nacional donde el costo y desempeño, impactan las soluciones para un mercado ávido de soluciones en áreas de uso masivo como la domótica.

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Diseño e implementación de un temporizador para un sistema en chip (SOC) en lenguaje Verilog

Diseño e implementación de un temporizador para un sistema en chip (SOC) en lenguaje Verilog

Digital electronic timers have been used for time control tasks since the invention of integrated circuits, there are individual timers encapsulated in a single chip, others are included within other systems, the study of this research is to design a timer module to form part of a system on chip (SOC). These on-chip systems are very common in the market of mobile computing, vehicle control and internet of things (IoT), due to their low cost, specific function and generally low power consumption, built around a microprocessor together with other peripherals. In this work the design of the digital timer is made to generate and treat different events related to the time that also includes generation of PWM signals (modulation by pulse amplitude), the applications of this device are: generation of time signals (Triggers) for initiation of analog / digital conversions in an ADC, Watch Dog protection circuit (watchdog), start of UART data transmission sequences (serial communication), event counting in the input ports of a SoC, timing for wakeup from low consumption mode in a microcontroller, generation of PWM signal, this timer has a data sheet for data reference so it can be used to integrate this module correctly within a system on chip (SOC) along with other components. This document contains the operating characteristics of the timer described in later chapters. It also has the respective tests with the Cadence NCSIM software and hardware level in an Altera FPGA DE2-115.

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The design and implementation of the UPMSAT-2 Attitude Control System

The design and implementation of the UPMSAT-2 Attitude Control System

Software validation usually includes testing the system under real operating conditions. However, for obvious rea- sons, on-board space software cannot be tested in this way. In order to achieve a testing environment as close as possible to the space operating conditions, simulation models are commonly used. This is the approach that has been adopted in the UPMSat-2 project, where the varia- tions of the Earth’s magnetic field, the spacecraft dynamics and a number of disturbances have been incorporated in a comprehensive environment model. An incremental validation process has been defined, in which the ACS is first simulated together with environment model, and then the software is run on the OBC hardware interfacing with the simulation model. In the final validation stage the full satellite hardware is tested against the environment model. 4.2 Model-in-the-loop validation

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Diseño y Evaluación de Arquitecturas de Enrutador Basado en Tablas de Enrutamiento Estáticas Orientadas al uso en \Network on Chip

Diseño y Evaluación de Arquitecturas de Enrutador Basado en Tablas de Enrutamiento Estáticas Orientadas al uso en \Network on Chip

A pesar de la separaci´ on de funcionalidades de un bus distribuido esto no es suficiente para cumplir con las nuevas necesidades de procesamiento, paralelismo y velocidad de transferencia de datos que pueden tener al- gunos sistemas, as´ı que se debe buscar una nueva arquitectura de co- municaci´ on para m´ ultiples dispositivos que mejore el ancho de banda de transmisi´ on de datos. Tomando en cuenta que te´ oricamente la mayor velocidad de transferencia de datos posible la podemos alcanzar usando una red de conexi´ on punto a punto y que el menor uso de l´ıneas de datos se puede alcanzar usando una arquitectura de interconexi´ on tipo bus, se puede pensar en la uni´ on de ambos conceptos, al compartir las l´ıneas de los buses entre los diferentes dispositivos usando paquetes de informaci´ on, de forma similar a como se hace en las redes de computa- doras est´ andar. de esta manera se introduce el concepto de Networks on chip(NoC).

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EVOLUTION OF SOIL ORGANIC CARBON DURING A CHRONOSEQUENCE OF TRANSFORMATION FROM CACAO (THEOBROMA CACAO L.) PLANTATION TO GRASSLAND

EVOLUTION OF SOIL ORGANIC CARBON DURING A CHRONOSEQUENCE OF TRANSFORMATION FROM CACAO (THEOBROMA CACAO L.) PLANTATION TO GRASSLAND

In fact, in a previous work, a chronosequence of grassland from 3 to 56 years of age, was evaluated. Their results indicated that 15 year old grasslands had a higher amount of C and N due to the age, the grassland system accumulated more SOM, coming specifically from plant and root organic wastes, which generated a higher SOC contribution and other nutrient uptake. After that age, there was a decrease in the release of chemical elements in such systems (Cheng & Shao (2015); Jie, Cheng, Li & Liu (2012); Tadakatsu, Ohkura & Matsumoto (2015)). Alternatively, Huang et al. (2010), mentioned that over the years, grasslands lose their vocation to accumulate SOC due to a decrease in the system productivity, mainly due to an increasing degradation of its properties, motivated by cattle overgrazing and the type of grassland established. Accordingly to Goodrick et al. (2015), some tropical agroforestry systems slowly reduce the SOC content due to the higher N contents that legumes procure (which speeds up the mineralization processes). In addition, a higher STN concentration and higher mineralization, reduces the C/N ratio, resulting in a greater SOM decomposition. Other research has documented that under certain conditions, by switching from crop to grassland, an increase in SOC levels, which can be achieved by 26% (Don et al., 2011). On the other hand, Johnson et al. (2007), conducted a study in which they revealed the SOC amount, which can be stored in the soil as a function of the organic wastes amount produced and entering into the soil, for instance, soil composition and soil decomposition rate, noting that roots of the grasses decomposition have allowed a great amount of recalcitrant compounds.

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TLM para la verificación de integración en SoC

TLM para la verificación de integración en SoC

Mientras que en el trabajo [79] se enuncia un flujo de dise˜ no tanto para el hardware como para el software que va a correr sobre ´este. En la especificaci´ on del sistema se realiza una descripci´ on inicial de ´este en un lenguaje (C++), posteriormente se realiza una descripci´ on en un nivel de abstracci´ on alto, el particionado de las partes dele sistema ya sean estas de hardware o de software y finalmente la simulaci´ on del sistema. El flujo completo implica retroalimentaci´ on entre la etapa de simulaci´ on y la de particionado, logrando de esta forma el realizar una verificaci´ on del mismo. Una vez que se logra obtener una representaci´ on adecuada del sistema y este esta verificado se procede a la s´ıntesis del mismo. En enfoque abordado por el autor difiere de los existentes en ese momento, en lugar de utilizar la descripci´ on del sistema (C++) como entrada de un sintetizador de alto nivel (HLS, por sus siglas en ingles); se propone seleccionar manualmente las clases que podr´ıan ser potenciales m´ odulos de hardware a fin de realizar la codificaci´ on de ´estas en VHDL y as´ı llevar a cabo la s´ıntesis del sistema.

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A Recommender System for Learning Objects on a Learning Management System: Implementation Experience

A Recommender System for Learning Objects on a Learning Management System: Implementation Experience

De modo que aprovechar los recursos generados por otros profesores y profesionales representa una necesidad. En este sentido, los repositorios de objetos de aprendizaje constituyen una oportunidad ante la creciente demanda de educaci´on en todos los pa´ıses, la capacidad limitada de la ense˜nanza tradicional, el esfuerzo y costo que implica la construcci´on de materiales de aprendizaje multimedia [14]. En la actualidad existen m´ultiples iniciativas para estanda- rizar los OA y convertirlos en elementos portables entre las plataformas y muchas de estas iniciativas se basan en el uso de metadatos para describir el contenido de cada ´ıtem. Dos de las iniciativas m´as importantes en cuanto a est´andares para intercambiar y recuperar informaci´on digital son LOM- IEEE y Dublin Core (DC), aunque exiten otros formatos con amplia difusi´on como los son MODS, MARC XML y ORE con especial difusi´on en el ambiente bibliotecario.

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Integración de bloques IP en diseños SoC

Integración de bloques IP en diseños SoC

En la metodología de diseño System-on-a-Chip (SoC) el diseñador combinará bloques pre- diseñados y pre-verificados en un chip para implementar funciones complejas, poseyendo un limitado conocimiento de la estructura interna de esos bloques. Debe asegurarse entonces, el correcto diseño físico (temporizados, potencia, tamaño) y un comportamiento funcional verificable del sistema.

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Human endocrine system modeling based on ontologies

Human endocrine system modeling based on ontologies

One advantage of the work done is that we were able to cope with time by connecting our Bio OntoCAPE with MatLab platform using the java application developed, we were able to simulate patients evolution over time. This is an important issue since we need to know how to construct this kind of biological models but through their computer implementations we are able to predict in certain time horizon the dynamic behavior of the most criti- cal variables. In this context, we have in mind as future work to analyze if it could be necessary to develop a new ontology based on the ideas of [21] who presented an ontology-based framework to support intelligent data analysis of recorded temporal data. They have shown how a process condition can be inferred when qualita- tive temporal patterns are available. These skills are very useful for doing recommendations each time the patient is out of the healthy range of glycemia. Another possibility is to take into account the work of [17] who proposed a fuzzy framework for encoding un- certainty in clinical decision-making to analyze insulin dosage and meals and recommend corrections to both.

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A proposal from the point of view of information visualization and human computer interaction for the visualization of distributed system load

A proposal from the point of view of information visualization and human computer interaction for the visualization of distributed system load

An effective visualization must allow the user to know intuitively what sector of the distributed system he/she is looking at. Because of this, it is import to maintain the context of the user location at all times. All undistorted techniques present a lack of context which makes them a poor selection for our objective. Among distorted techniques, those ones with a non continuous magnification fail to provide a smooth transition between the focus areas and the context areas and force the user to mentally create this transition, increasing the cognitive overhead.

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Interaction system based on an avatar projected on a pyramidal display

Interaction system based on an avatar projected on a pyramidal display

of the pyramid. The interaction system has been discussed, as well as its node-based architecture and the way the avatar is controlled though ROS. The different expressions have been generated using the FACS, and to this end, the number of action units has been refined to perform the six basic emotions. The animations are built by using shape keys and bones, grouped in actions. The system have been developed following a methodology with a clear robotic orientation based on the use of (virtual) bones-type actuators and the FACS human expression model, as opposed to the usual approaches used in animation. Therefore, the current approach allows the results to be directly applied to the development of physical robotic heads.

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Diffractive sidewall grating coupler: towards 2D free-space optics on chip.

Diffractive sidewall grating coupler: towards 2D free-space optics on chip.

Beam expanders, devices that change the mode spot size, are fundamental to connect the wide fiber-chip couplers (~15 𝜇𝑚) to the narrow standard silicon wire waveguide (500 𝑛𝑚). The simplest and most straightforward way to implement this expansion is using linear tapers. However, this approach obtains extremely long devices (∼ 150𝜇𝑚) since a steep change in width would cause power transfer to undesired higher order modes. Extensive research has been made to obtain compact and efficient spot-size converters 14 . In this work we propose a new compact architecture for

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Acoplamiento de una celda de combustible nanofluídica con un microsistema lab-on-a-chip para la conversión y adecuación de energia

Acoplamiento de una celda de combustible nanofluídica con un microsistema lab-on-a-chip para la conversión y adecuación de energia

In recent years, laminar flow membranless microfluidic fuel cells (LMμFFC by its acronym) which consists of two electrodes, an anode where oxidation of a fuel occurs and a cathode where an oxidant is reduced ( commonly oxygen) have emerged as a promising solution for energy demand of small-scale devices such as; laptops, mobile phones, sensors and medical implants. In this paper presents the evaluation physicochemical analysis by SEM and XRD and electrochemical through cyclic voltammetry and impedance, conducted two types of diffusers (nanofoam and Toray carbon paper) to electrodes of Pt and Pd for a LMμFFC as well as the evaluation in complete cell fed with formic acid as a fuel and optimizing parameters such as stoichiometry, molarity and injection flow rate of fuel and oxidant. Two types of diffusers were evaluated resulting best performing the Toray paper, since due to the structure of this impregnation technique of the catalysts used was more efficient. The energy generated by the LMμFFC requires a conditioning process to be used as a power source, in this work the development and evaluation of a micro lift coupled to the cell voltage occurs. Resulting in an integrated capable of converting chemical energy into electrical energy to innovation having a microelectronic integrated interface capable of raising and adjust the voltage to a commercial application of low power consumption system.

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On bounding a nonlinear system with a monotone positive system

On bounding a nonlinear system with a monotone positive system

The obtention of componentwise bounds for linear time- invariant (LTI) systems with disturbances has been addressed in [13] for the case of constant (and also for some specific state-dependent) disturbance bounds. The main method in [13] has been tailored to sampled-data systems with quantization [4] and extended to switched systems [6], [7]. Also, discrete- time [8], [13] and probabilistic [11], [12] extensions are available. All of these previous works are essentially based on the analysis of a perturbed LTI system. The essential procedure consists in (a) finding a linear coordinate change under which the LTI system’s A-matrix becomes simpler, e.g. diagonal or triangular; (b) bounding the magnitude of each component of the transformed system state; (c) linearly transforming back into the original coordinates. One key feature of this procedure is that the componentwise bounding step (b), which requires the transformed A-matrix to be “simpler”, is guaran- teed to produce a convergent bound whenever the nominal (i.e. undisturbed) system is asymptotically (hence globally exponentially) stable. The bounding step of the procedure, namely (b), is applicable only to an LTI system, with no obvious way to extend it to nonlinear systems.

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Full Potentiostat System with wireless communication in a Programmable System On a Chip and a PC

Full Potentiostat System with wireless communication in a Programmable System On a Chip and a PC

Nowadays, Dryden et al. had reached one of the lowest current detection limit (600 fA) in the literature [10]. That device can take 30,000 samples per second using one of the fastest ADC reported. The careful selection of the electronic components was a key to enhancing the potentiostat system performance. It has an analog multiplexor of 10 for each channel in on mode, a -Converter of 24 bits, a femtoampere input bias current for the Transimpedance Amplifier (TIA), and low offset rial-to-rial OPAMPs. Thus, the limits of detection drop drastically. However, the size of the Printed Circuit Board (PCB) and the lack of wireless data transmission are unwanted features for certain applications. In the market, there are several potentiostat instruments. However, PalmSens has one of the smallest called EmStat [18]. This instrument has an area of 5.5 cm x 4.1 cm, turning it into an interesting option for embedded applications such a Lab-on-a-Disc and POCT. However, for wearable monitoring systems, the size could be an issue. Moreover, the device can execute nine electrochemical techniques with a range of detection from 100 mA to 1 pA. The main drawback of this device is the power consumption of 2.5 W and the price difference compared to homemade potentiostats.

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Towards a complete Lab-On-Chip system using integrated Mach-Zehnder interferometers

Towards a complete Lab-On-Chip system using integrated Mach-Zehnder interferometers

micro/nano dimensions, based on Total Internal Reflection (TIR) propagation. MZI sensors, that have  already shown their high sensitivity for biosensing applications, are currently being implemented in  a  multiplexed  configuration.  We  present  here  the  first  results  of  the  design  and  simulation  of  a  multiplexed  MZI  platform  with  4  channels  for  the  simultaneous  detection  of  different  analytes.  Moreover,  we  describe  a  novel  phase  modulation  technique  which  solves  some  of  the  problems  inherent to standard MZI sensor. This modulation technique does not require additional fabrication  process  and  will  directly  provide  a  linear  phase  response.  Concerning  the  light  coupling  into  the  waveguides, it is achieved by the use of diffraction grating couplers, favoring the passage from bulky  laboratory equipment to delocalized applications. We also describe an optimized process for surface  biofunctionalization  to  bind  the  bioreceptors  for  target  recognition  and  its  validation  with  an  immunoassay. 

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Procesamiento de imágenes cerebrales en GPU

Procesamiento de imágenes cerebrales en GPU

New computing technologies put an imperative effort on reducing power consump- tion. The search of low power platforms derives from an older perspective which focused the increment of computers performance. This idea continued until too many resources were necessary to feed the machine. At this moment, an inflection point occurred in the device targets: instead of computational power they started to concentrate on efficiency. Having more performance is not a forgotten objective but it is now driven by a reasonable power budget.

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