[PDF] Top 20 Minería de datos en redes sociales por medio de un correlacionador de datos
Has 10000 "Minería de datos en redes sociales por medio de un correlacionador de datos" found on our website. Below are the top 20 most common "Minería de datos en redes sociales por medio de un correlacionador de datos".
Novel Low Power Logic Gates using Sleepy Techniques
... ground using sleep transistors (figure ...leakage power reduction but loses the state information when it enters in to sleep ...mode. Sleepy Keeper approach introduces additional keeper transistors ... See full document
23
Design and Implementation of Dual Mode Logic Based Phase Locked Loop with Sleepy Stack Approach
... with low power techniques which aim at reducing the leakage power of the ...Two low power novel techniques called sleepy stack approach and dual mode ... See full document
154
A Novel Code Compression for Embedded Systems Using Reversible Logic Gates
... cases, low code density architecture which contains a high number of unique instructions a large LUT is required to compress the ...additional power consumption, a long LUT latency, and a long codeword ... See full document
36
Design and Analysis of Low Power Subtractor Circuits using P XOR Logic Gates with Sleep Approach
... adders using novel XOR and XNOR gates in combination with the existing ...less power in high frequencies, while three new adders consistently consume on average 10% less power and have ... See full document
25
A Low Power 32-Bit Ripple Carry Adder Using Dynamic DML CMOS Logic Gates
... DML gates achieve very high speed in dynamic operation at the outlay of increased power ...static logic family gate, which can be a conventional CMOS gate, and an additional ...DML gates have ... See full document
42
1. design of low voltage, low power and high speed logic gates using modified gdi technique
... In low-voltage and low-power applications, optimization of several devices for speed and power is a significant ...reducing power consumption, delay and area of digital circuits, while ... See full document
11
Performance analysis of artificial neural network using leakage power reduction techniques for DSP applications
... complexity, low cost and it reduces the time for ...basic logic gates and basic digital circuits as shown in ...designed using 130nm CMOS ... See full document
19
Design of 8X1 Low Power Multiplexer by using Transmission Gates
... ABSTRACT: Low power and very high speed digital circuits are basic the needs for any of digital circuit, Multiplexer is a basic circuit for any digital ...different techniques of multiplexer designs ... See full document
76
Design Of Low Power Adder And Multiplier Using Reversible Logic Gates
... Robert Wille et al., [9] explored two techniques from irreversible equivalence checking applied in the reversible circuit domain. (i) Decision diagram Technique equivalence checking for quantum circuits and (ii) ... See full document
154
Ultra Low Power Logic Gates
... of logic gates are integrated, constant and continuous works is being carried out by different experts to reduce the power ...very low power ...the power dissipation base on ... See full document
5
Fine-Grain Power-Gated Logic for Asynchronous Circuit Using Partial Charge Reuse
... be power gated at the gate level of granularity [5], ...are power gated, and the other hardware still suffers leakage ...adiabatic logic (AAL) was ...the logic part of the stage, and a control ... See full document
63
Novel High Speed Low Power Binary Multiplier Designs using Reversible Logic Gates
... The paper proposes efficient MOS implementation for the basic reversible gates namely, Feynman, Toffoli, and Peres gates and employs the proposed circuits in the reversible binary multip[r] ... See full document
7
Title : Pipelining With Asynchronous Fine-Grain Power-Gated Logic Using ECRLAuthor (s) :Jagatheswari.S,Sakthi shree.E,Suganya.s
... improvement power dissipation has become an important concern in nano scale CMOS VLSI ...circuits Power dissipation will be divided into dynamic dissipation and static ...switching power caused by ... See full document
5
Design of low power network on chip using data encoding techniques
... overall power dissipation is due to the interconnection ...dynamic power dissipation in a NoC ...the power efficient of complex SoC compared to other ...switching techniques and works on an ... See full document
40
A novel null convention logic (NCL) gates architecture based on basic gates
... design got a normal decrease of 8% and 19% at the point when contrasted individually with the designs of Fig. 4 and Fig. 7; looking at the dynamic power utilization, the proposed design acquired a normal decrease, ... See full document
10
A Low Power Multiple Valued Logic SRAM Cell Using Single Electron Devices
... design using unique negative differential conductance (NDC), with emphasis on power ...standby power dissipation. For instance, the memory cell using an NDC element from [5] works at liquid ... See full document
23
LOW POWER DESIGN OF DOUBLE TAIL COMPARATOR USING SLEEPY STACK TECHNIQUE
... In power gating technique a low threshold CMOS circuit is connected to the high threshold module known as sleep ...virtual power supply and ground to perform the normal ... See full document
48
High Speed Multioutput 128bit Carry-Lookahead Adders Using Domino Logic
... arithmetic logic units, but also in other parts of the processor, where they are used to calculate addresses, table indices, and similar ...digital logic gates and circuits designed using ... See full document
15
Low Power Hybrid Full Adder Using Transmission Gates
... optimize power of the circuit, the energy consumption has been minimized in the proposed ...the power consumption could be minimized by mainly sizing the transistors in inverter circuits, while the carry ... See full document
8
Multi Threshold Low Power SRAM Using Floating Gates
... During cell hold state, the node at '0' value is connected to ground through to series connected NMOS off transistors. So, leakage current reduces due to stack effect. Similarly the leakage current flowing through PMOS ... See full document
41
Related subjects