º. Deberes de los colegiados Los colegiados tendrán los siguientes deberes:

When embedded systems are deployed in safety critical situations we need to document how the system was tested, and provide proof it is functioning as intended. We will illustrate the process with the example from module 2. In Lab02 the goal was to create a system that toggled the light at 5 Hz. This means the red LED should be on for 0.1 sec and off for 0.1 sec. If we look at the LED with our eyes it looks like it is running correctly. If we look at the signal on the oscilloscope or logic analyzer, again it looks correct. But can we prove it? In this first debugging process we will dump the value of PF1 in one array and the time difference in a second array, see Program 9.9. When we run this program, it reveals all 49 measurements where the average time difference is 1,599,996 bus cycles, which is 0.09999975 seconds, which is close to the desired time of 0.1 second.

// first data point is wrong, the other 49 will be correct unsigned long Time[50];

unsigned long Data[50];

int main(void){ unsigned long i,last,now;

// initialize PF0 and PF4 and make them inputs PortF_Init(); // make PF3-1 out (PF3-1 built-in LEDs)

SysTick_Init(); // initialize SysTick, runs at 16 MHz i = 0; // array index

Program 9.9. Instrumentation to record the first 49 time differences (debugging shown in bold).

However compelling this data is, it doesn’t prove it is always 0.1 sec. Let’s further specify the desire is to create a system that is accurate to ±0.01%. This means any time difference 1,600,000±160 cycles is acceptable. In Program 9.10 we will count the number of times the time difference is unacceptable. If we run this program for a month we can observe its behavior over 25 million times. Furthermore, we can leave this debugging code into the deployed system, and verify the system is running as expected for the entire life of the system.

// first data point is wrong, the others will be correct long Errors;

#define CORRECT 1600000

#define TOLERANCE 160

int main(void){ unsigned long last,now,diff;

// initialize PF0 and PF4 and make them inputs PortF_Init(); // make PF3-1 out (PF3-1 built-in LEDs)

SysTick_Init(); // initialize SysTick, runs at 16 MHz Errors = -1; // no errors (ignore first measurement) last = NVIC_ST_CURRENT_R;

while(1){

Led = GPIO_PORTF_DATA_R; // read previous Led = Led^0x02; // toggle red LED GPIO_PORTF_DATA_R = Led; // output

now = NVIC_ST_CURRENT_R;

diff = (last-now)&0x00FFFFFF; // 24-bit time difference if((diff<(CORRECT-TOLERANCE))||(diff>(CORRECT+TOLERANCE)){

Error++;

}

last = now;

Delay();

} }

Program 9.10. Instrumentation to count the number of mistakes (debugging shown in bold).

One interesting feature we could add to this system is to implement the Error count in ROM. The flash ROM allows the running program to change its value. The disadvantage of storing data in ROM is it takes over 1ms to cause the change. In situations where we have infrequent but important data, this 1ms overhead is not significant. The advantage of storing infrequent but important debugging information in ROM is that this data is available even if power is removed and restored. For example, if the embedded system were to be involved in a loss of life accident, the data stored in ROM could be recovered to determine if any run-time errors might have contributed to the accident. Conversely, this data stored in ROM could verify that no errors in the operation of the embedded system had occurred prior to the accident. If you wish to write to flash ROM, look at example projects called “flash” on http://users.ece.utexas.edu/~valvano/arm/.

Chapter 10: Finite State Machines Embedded Systems - Shape the World Jonathan Valvano and Ramesh Yerraballi

Time is a critical parameter in an embedded system. In this chapter, we will further develop SysTick as a means to control time in our embedded system. We will activate the phase-lock-loop (PLL) for two reasons. First, by selecting the bus frequency we can tradeoff power for speed. Second, by creating a bus clock based on an external crystal, system time will be very accurate. An effective development process will be to separate what the system does from how it works. This abstraction will be illustrated during the design of finite state machines (FSM). All embedded systems have inputs and outputs, but FSMs have states. We will embody knowledge, “what we know” or “where we’ve been”, by being in a state. A traffic light and vending machine will be implemented using FSMs. Finally, we will introduce stepper motors and show how to use a FSM to control the motors.

Learning Objectives:

 Learn how to activate the PLL so the microcontroller has an accurate time base

 Use SysTick to produce accurate time delays

 Learn how to organize data on the computer using structures

 Develop a design strategy for building Finite State Machines

 Explain how stepper motors work using two motors to make an autonomous robot 10.1. Phase-Lock-Loop

Normally, the execution speed of a microcontroller is determined by an external crystal. The Stellaris®

EK-LM4F120XL and EK-TM4C123GXL boards have a 16 MHz crystal. Most microcontrollers include a phase-lock-loop (PLL) that allows the software to adjust the execution speed of the computer.

Typically, the choice of frequency involves the tradeoff between software execution speed and electrical power. In other words, slowing down the bus clock will require less power to operate and generate less heat. Speeding up the bus clock obviously allows for more calculations per second, at the cost of requiring more power to operate and generating more heat.

The default bus speed for the LM4F/TM4C internal oscillator is 16 MHz ±1%. The internal oscillator is significantly less precise than the crystal, but it requires less power and does not need an external crystal. The TExaS real-board grader has been turning on the PLL, and in this section we will explain how it work. If we wish to have accurate control of time, we will activate the external crystal (called the main oscillator) use the PLL to select the desired bus speed.

There are two ways to activate the PLL. We could call a library function, or we could access the clock registers directly. In general, using library functions creates a better design because the solution will be more stable (less bugs) and will be more portable (easier to switch microcontrollers). However, the objective of the class is to present microcontroller fundamentals. Showing the direct access does illustrate some concepts of the PLL.

An external crystal is attached to the LM4F/TM4C microcontroller, as shown in Figure 10.1. Table 10.1 shows the clock registers used to define what speed the processor operates. The output of the main oscillator (Main Osc) is a clock at the same frequency as the crystal. By setting the OSCSRC bits to 0, the multiplexer control will select the main oscillator as the clock source.

The main oscillator for the LM4F/TM4C LaunchPad will be 16 MHz. This means the reference clock (Ref Clk) input to the phase/frequency detector will be 16 MHz. For a 16 MHz crystal, we set the XTAL bits to 10101 (see Table 10.1). In this way, a 400 MHz output of the voltage controlled oscillator (VCO) will yield a 16 MHz clock at the other input of the phase/frequency detector. If the 400 MHz clock is too slow, the up signal will add to the charge pump, increasing the input to the VCO, leading to an increase

in the 400 MHz frequency. If the 400 MHz clock is too fast, down signal will subtract from the charge pump, decreasing the input to the VCO, leading to a decrease in the 400 MHz frequency. Because the reference clock is stable, the feedback loop in the PLL will drive the output to a stable 400 MHz frequency.

Figure 10.1. Block diagram of the main clock tree on the LM4F/TM4C including the PLL.

XTAL Crystal Freq (MHz) XTAL Crystal Freq (MHz)

0x0 Reserved 0x10 10.0 MHz

0x1 Reserved 0x11 12.0 MHz

0x2 Reserved 0x12 12.288 MHz

0x3 Reserved 0x13 13.56 MHz

0x4 3.579545 MHz 0x14 14.31818 MHz

0x5 3.6864 MHz 0x15 16.0 MHz

0x6 4 MHz 0x16 16.384 MHz

0x7 4.096 MHz 0x17 18.0 MHz

0x8 4.9152 MHz 0x18 20.0 MHz

0x9 5 MHz 0x19 24.0 MHz

0xA 5.12 MHz 0x1A 25.0 MHz

0xB 6 MHz (reset value) 0x1B Reserved

0xC 6.144 MHz 0x1C Reserved

0xD 7.3728 MHz 0x1D Reserved

0xE 8 MHz 0x1E Reserved

0xF 8.192 MHz 0x1F Reserved

Address 26-23 22 13 11 10-6 5-4 Name

$400FE060 SYSDIV USESYSDIV PWRDN BYPASS XTAL OSCSRC SYSCTL_RCC_R

$400FE050 PLLRIS SYSCTL_RIS_R

31 30 28-22 13 11 6-4

$400FE070 USERCC2 DIV400 SYSDIV2 PWRDN2 BYPASS2 OSCSRC2 SYSCTL_RCC2_R

Table 10.1. Main clock registers (RCC2 in LM4F/TM4C only).

Program 10.1 shows the steps 0 to 6 to activate the LM4F123/TM4C123 Launchpad with a 16 MHz main oscillator to run at 80 MHz. 0) Use RCC2 because it provides for more options. 1) The first step is to set BYPASS2 (bit 11). At this point the PLL is bypassed and there is no system clock divider. 2) The

second step is to specify the crystal frequency in the four XTAL bits using the code in Table 10.1. The OSCSRC2 bits are cleared to select the main oscillator as the oscillator clock source. 3) The third step is to clear PWRDN2 (bit 13) to activate the PLL. 4) The fourth step is to configure and enable the clock divider using the 7-bit SYSDIV2 field. If the 7-bit SYSDIV2 is n, then the clock will be divided by n+1.

To get the desired 80 MHz from the 400 MHz PLL, we need to divide by 5. So, we place a 4 into the SYSDIV2 field. 5) The fifth step is to wait for the PLL to stabilize by waiting for PLLRIS (bit 6) in the SYSCTL_RIS_R to become high. 6) The last step is to connect the PLL by clearing the BYPASS2 bit.

To modify this program to operate on other microcontrollers, you will need to change the crystal frequency and the system clock divider.

Checkpoint 10.1: How would you change Program 10.1 if your microcontroller had an 8 MHz crystal and