Año Específico (No. 4)

Leakage reduction is a crucial problem in deep sub micron regime. In chapter 3, we have formulated the low leakage vector identification technique based on interval propagation at register transfer level. Using this technique, significant subthreshold leakage savings with no area overhead are achieved successfully. We also proposed a self similarity based module characterization which makes this technique scalable to more complex datapaths. We conclude that our low leakage vector determination technique achieves significant leakage optimization in RTL datapaths of any level of complexity if one could invest in a few hours of pre-characterization time. As part of future work, a correlation between a circuit and self similarity property of the input space could be derived. The origin of self similarity property in VLSI circuits can be examined based on the structure of the circuits. The difference of self similarity in bit sliced designs and random designs can be researched. Interval propagation technique can be adopted to identify minimum NBTI vector to achieve NBTI minimization at high level. Input design space exploration can be conducted with self similarity based characterization to acquire NBTI and leakage co-optimized vector.

Input vector control is a common leakage reduction technique which reduces the leakage by controlling transistor stacking with a given input vector. Since NBTI is effected by transistor stacking as well, co-optimization of both the objectives is considered. In chapter 4, an alternative vector cycling technique is developed with simulated annealing and a back tracking algorithm for NBTI and leakage co-optimization. The technique is implemented in gate level combinational

circuits. The periodic recovery for critical path transistors under stress alleviates NBTI degradation. This technique successfully achieved significant NBTI improvement with minimum leakage overhead. We conclude that our technique optimizes NBTI and leakage effects on gate level circuits. The technique can be further extended to high-k circuits where PBTI phenomenon is dominant as well. NBTI, PBTI and leakage can be co-optimized.

State encoding in FSMs has a strong control on circuit area and performance. It can be adopted to optimize NBTI degradation as well. In chapter 5, a simulated annealing algorithm is devised to obtain NBTI optimization in finite state machines at gate level. State probability parameter is used to reduce the input space. Significant NBTI improvement is achieved for minimum area and power overhead. The same technique can be extended to PBTI optimization as well. As a part of future work, NBTI aware synthesis as described in [48] can be performed on the benchmarks in addition to NBTI optimization. This might alleviate NBTI further.

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APPENDIX A: SELF SIMILARITY PLOTS FOR 8b ADDER AND 8b MULTIPLIER

Figures A.1–A.5 present the Hurst parameters and grid level leakage distribution of 8b multiplier when the input space is divided into cells along both axes (2 x 2 grid). Figures A.6–A.10 present the Hurst parameters and grid level leakage distribution of 8b adder when the input space is divided into cells along both axes (2 x 2 grid).

If the same input space is divided into 4 grid cells along one axis, we have the following grid cells: [0, 0 - 63, 255], [63, 0 - 127, 255], [127, 0 - 191, 255], and [191, 0 - 255, 255]. Figures A.11–A.15 present the grid level distribution of a multiplier when the input space is divided along one axis (4 x 1 grid). Figures A.16–A.20 present the grid level distribution of a multiplier when the input space is divided along one axis (4 x 1 grid). Figures A.21–A.37 present the grid level distribution of 8b multiplier when the input space is divided along both axes (4 x 4 grid). Figures A.38–A.54 present the grid level distribution of 8b adder when the input space is divided along both axes (4 x 4 grid). If the bit-width of the module is doubled, the number of cells on each axis is doubled as well. Hence, the characterization is scalable.

Figure A.2: Multiplier Distribution in Grid Cell 1 (2 x 2 Grid)

Figure A.4: Multiplier Distribution in Grid Cell 3 (2 x 2 Grid)

Figure A.6: Hurst Parameter in Adder with 4 Cells (2 x 2 Grid)

Figure A.8: Adder Distribution in Grid Cell 2 (2 x 2 Grid)

Figure A.10: Adder Distribution in Grid Cell 4 (2 x 2 Grid)

Figure A.12: Multiplier Distribution in Grid Cell 1 (4 x 1 Grid)

Figure A.14: Multiplier Distribution in Grid Cell 3 (4 x 1 Grid)

Figure A.16: Hurst Parameter in Adder with 4 Cells (4 x 1 Grid)

Figure A.19: Adder Distribution in Grid Cell 3 (4 x 1 Grid)

Figure A.21: Hurst Parameter in Multiplier with 16 Cells (4 x 4 Grid)

Figure A.23: Multiplier Distribution in Grid Cell 2 (4 x 4 Grid)

Figure A.25: Multiplier Distribution in Grid Cell 4 (4 x 4 Grid)

Figure A.27: Multiplier Distribution in Grid Cell 6 (4 x 4 Grid)

Figure A.29: Multiplier Distribution in Grid Cell 8 (4 x 4 Grid)

Figure A.31: Multiplier Distribution in Grid Cell 10 (4 x 4 Grid)

Figure A.33: Multiplier Distribution in Grid Cell 12 (4 x 4 Grid)

Figure A.35: Multiplier Distribution in Grid Cell 14 (4 x 4 Grid)