Actividades Durante la Ejecución de Obra

Each IC is gold wire bonded to a 400MHz ceramic dil package. For testing the circuits, custom built PCBs w ere used. As these circuits are used for signals in excess of 250MHz, the layout of the PCBs needs to be done w ith great care. In the layout of PCBs for high speed circuits, the layout of ground connections is

4. IC FABRICATION

d o u b le -sid e d copp er-clad p rin te d circuit b o ard w as u sed . E v ery p a r t of th e b o a rd n o t u s e d for co m p o n e n ts o r connections fo rm s p a r t o f a c o n tin u o u s g ro u n d plane. This g ro u n d p lan e covers both sides of the b o a rd a n d is jo in ed a ro u n d the ed g e by a con tin u o u s soldered seal of tin n ed c o p p e r foil. E ach of the signal connections are m ad e via gold-plated SMA sockets, m o u n te d as close to the relev an t IC p in s as possible. To elim inate noise o n DC p o w e r su p p lies, these are capacitively decoupled to the g round p lan e u sin g O.lpF surface m o u n t capacitors connected directly to the p o w er su p p ly pins. Low freq u en cy rip p le is m in im ised by fu rth e r deco u p lin g u sin g 22)iF ta n ta lu m capacitors. B oth of these ty p es of cap acito r h av e hig h reso n an t frequencies, e n s u rin g th a t th e y m a in ta in th e ir ch aracteristics over the hig h frequency ran g es in v o lv e d . In ad d itio n , incom ing noise on each DC su p p ly is m inim ised by co n n ectin g th ese th ro u g h a series O.ljiH inductor. A typical PCB b o a rd is sh o w n in Figs. 4.11a and 4.11b.

4. IC FABRICATION

5. M E A SU R E D RESULTS

C H A P T E R 5

M e a s u r e d R e s u l t s

This ch a p ter contains m e asu re d resu lts a n d HSPICE sim u latio n s for all of the circuits described in ch ap ter 3. It begins by describing th e m easu rem en ts m ad e u p o n th e electronic a n d optical test structures, an d co n tin u es w ith a w id e range of tests on the O S /H circuits. These tests are d esig n e d to give an in sig h t into the action of the circuits an d hig h lig h t th eir qualities an d deficiencies. W here p o ssib le th e m e a su re d re su lts are co m p ared d irectly to sim u latio n s a n d the calculations m ad e in ch ap ter 3.

5.1 Ci r c u i t b u i l d i n g b l o c k s

Before testin g the S / H circuits a series of m e a su re m e n ts w ere m a d e on the electronic an d optical test stru ctu res inclu d ed on the test chips. In p artic u la r, the characteristics o f th e cu rre n t sources an d p h o to d io d e s w ere m e a su re d so th a t th e co rrect b ias v o ltag es for th e S / H circuits c o u ld be d e te rm in e d . A n u m b e r of p re lim in a ry tests h av e b een m ad e on th ese circuits an d the resu lts are p re se n te d here.

5.1.1 U nity G ain B uffer

As th e u n ity gain b u ffe r is a key co m p o n en t in all of th e O S /H circuits, its p erfo rm an ce w ill affect each of these circuits. A series of m easu rem en ts have sh o w n th a t in key areas of perfo rm an ce the b u ffer fu nctions correctly, a n d is a p p ro p ria te for use in the O S /H s. C om parisons w ith the SPICE sim ulations are m a d e w h ich h ig h lig h t th e sim ilarities (and differences) b etw een th e m easu red an d sim u lated results. A test jig w as b u ilt consisting of a dil socket m o u n ted on p la in m atrix b o ard . In o rd e r to d a m p u n w a n te d o scillatio n s tin n ed c o p p er s h ie ld in g is u se d as a g ro u n d p la n e, DC co n n ectio n s are m a d e v ia lOjiH in d u c to rs, a n d all D C p o in ts are d e c o u p le d d ire c tly to g ro u n d w ith O.ljiF surface m o u n t capacitors. A dditionally, all u n u sed p in s are connected to either Ov o r - 5v as ap p ro p riate.

5. MEASURHIJ R[-SUi;rS

(i) Frequency Response

The frequency response of the buffer w as sim ulated using HSPICE w ith a IV peck to peak input signal sw ept from IH z to lOGHz, as show n in Fig. 5.1. This sim ulation uses the dispersive MESFET m odel show n in Eig. 2.12. At low frequencies (< -lOOHz) the o u tp u t conductance takes the DC value of 96.5|iS giving a gain of 0.999 (-8.69mdB). At frequencies above IkH z the o u tp u t conductance increases to 300|iS, reducing the gain to 0.994 (-0.052dB) and indicating a gain error of about 0.5%. This is equivalent to the gain error calculated in section 3.6. The - 3dB frequency is in excess of lOGHz.

Bootstrapped buffer

-0 .5

Basic follow er circuit

- 1 -

- 1 .5

10 1 0' 1 0 1 0

Frequency (Hz)

10 10

Fig 5.1 Sim ulated frequency resp o n se of ttie unity gain buffer. Tfiis stiow s the effect of frequency dependent drain conductance.

The frequency response w as m easured in a 50D env iro n m en t using a H ew lett-Packard 500MHz netw ork analyser delivering a OdBm (224mV rms.) output. To correct for the effects of the PCB board, cables etc, a calibration was perform ed by replacing the buffer chip w ith a straight-through connection. Fig. 5.2 show s the results of these m easurem ents, revealing a frequency response which is flat to w ithin 0.5dB and 4° up to 500MHz, su p p o rtin g the