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When an interrupt is actually received, there are several steps the processor must take to ensure the rest of the program and any stored data is not lost

due to the interrupt. Below is an example of an ISR which acts as an adder, summing the values of the PINA and PINB registers, and using the result to set PORTC. Immediately below the ISR is the assembly code, which will be broken down into segments and explained along with the steps the processor must take. Assembly is an intermediate step between a programming language such as C and the machine code that is written to the microcontroller. In assembly, each line is an individual instruction stored in the program memory and executed in one or more cycles. The first column is the memory address of the instruction, and the following hexadecimal value is the instruction stored there. To the right of that are the human readable opcodes and arguments that correspond to the hexadecimal instructions. Descriptions of all the opcodes for the ATmega644p are in chapter 28 of the datasheet [11]. Different processors may have different instruction sets, so what works for one processor or microcontroller likely will not work for a different type.

ISR ( T I M E R 0 _ C O M P A _ v e c t ) { // l o a d a r g u m e n t s ( PINA , B ) c h a r i = P I N A ;

c h a r j = P I N B ;

// sum the two and o u t p u t P O R T C = i + j ;

}

000000a4 <__vector_16>:

a4: 1f 92 push r1 ; This register not actually needed

a6: 0f 92 push r0 ; Used in saving status register

a8: 0f b6 in r0, 0x3f ; 63 (Status register SREG)

aa: 0f 92 push r0 ; push SREG

ac: 11 24 eor r1, r1 ; clears register

ae: 8f 93 push r24 ; store registers used in ISR

b0: 9f 93 push r25

b2: 90 b1 in r25, 0x00 ; 0 Load PINA (address 0)

b4: 83 b1 in r24, 0x03 ; 3 Load PINB

b6: 89 0f add r24, r25 ; Sum PINA, PORTB. Save to r24 b8: 88 b9 out 0x08, r24 ; 8 Set PORTC

ba: 9f 91 pop r25 ; restore registers used in ISR

bc: 8f 91 pop r24

be: 0f 90 pop r0 ; pop old SREG value

c0: 0f be out 0x3f, r0 ; 63 restore SREG

c2: 0f 90 pop r0 ; pop old values

c4: 1f 90 pop r1

c6: 18 95 reti ; return to previous function

1. The first step of the interrupt process is the actual receipt of the interrupt signal. If the individual interrupt is enabled, and interrupts are enabled globally by the I bit of the SREG register, the process continues after the currently executing instruction completes. If either are disabled than the flag is set but no interrupt service routine is called.

2. The global interrupt enable is cleared to prevent further interrupts from occurring while one is being serviced.

3. The instruction pointer is pushed to the stack. This is handled by hard- ware and does not appear anywhere in the program. The instruction pointer must be saved in order to restore the system to the next instruc- tion that would have executed had the interrupt not occurred.

4. The program counter is set to the beginning of the ISR. This is also handled by hardware, however the addresses of all ISRs are stored in the program memory. If the requisite ISR does not exist, the software resets and begins again from the start of the main function.

5. The previous program context is saved. This involves pushing the values of any registers that will be used during the course of the ISR onto the stack for later retrieval. If this is not done, then when the ISR exits some of the data required by the main program may have changed and can cause problems to occur. Furthermore, the current value of the status register SREG must be saved. This register contains carry, overflow and other ALU (arithmetic logic unit) result flags. Failing to save this information can result in errors in the main program. This process is handled by the instructions in the memory block 0xa4 through 0xb0 in the above example.

a4: 1f 92 push r1 ; This register not actually needed

a6: 0f 92 push r0 ; Used in saving status register

a8: 0f b6 in r0, 0x3f ; 63 (Status register SREG)

aa: 0f 92 push r0 ; push SREG

ac: 11 24 eor r1, r1 ; clears register

ae: 8f 93 push r24 ; store registers used in ISR

b0: 9f 93 push r25

6. Finally the actual code in the ISR is executed. In this example it is the reading of PINA and PINB, the addition of the same and saving the result to PORTC. These registers are accessed using their memory addresses: 0x00, 0x03 and 0x08 respectively.

b2: 90 b1 in r25, 0x00 ; 0 Load PINA (address 0)

b4: 83 b1 in r24, 0x03 ; 3 Load PINB

b6: 89 0f add r24, r25 ; Sum PINA, PORTB. Save to r24 b8: 88 b9 out 0x08, r24 ; 8 Set PORTC

7. After the ISR has completed, the previously stored context of the main function must be restored by poping the previously stored values off the stack and returning them to their previous registers. This is step 4 in reverse, including restoring SREG to its previous state.

ba: 9f 91 pop r25 ; restore registers used in ISR

be: 0f 90 pop r0 ; pop old SREG value c0: 0f be out 0x3f, r0 ; 63 restore SREG

c2: 0f 90 pop r0 ; pop old values

c4: 1f 90 pop r1

8. Finally the ISR returns to the main function. The previously stored in- struction pointer value is reloaded, global interrupts are re-enabled and the main function picks up where it left off, unaware of the interruption. This is all handled by hardware when the reti instruction occurs.

c6: 18 95 reti ; return to previous function