2.5 V OLATILIDAD 42
2.6.4 Adyuvante modificador de la utilidad
When considering system faults, the pole-to-ground DC-link fault is more likely compared to the pole-to-pole DC-link fault. However, the pole-to-pole fault is more critical in the symmetrical monopole HVDC configuration and needs evaluated for worst case peak currents, [72]. The pole-to-pole fault is located in Figure 3.13. The important features of Figure 3.13 for the explanation to follow include the bypass switch (BPS) and AC circuit breaker – the two mechanisms of mechanical protection in the circuit. Some details of the analysis are purposely omitted with only observations noted.
Transformer
Arm reactance
Vdc
Overhead Line Submodule
Phase A Phase B Phase C
Phase Voltage Upper Arm uk1 Ls Ls Ls Ls Ls Ls Cell Capacitor Bypass Switch IGBT FWD Phase Voltage Lower Arm uk2 ik ik1 ik2 + - O AC AC Breaker Overhead Line
When a fault is identified in the system, the AC circuit breaker (ACCB) and BPS are introduced into the circuit and converter controllers do not regulate any longer but gate block. Assume the HVDC system is operating at steady-state and suddenly a pole-to-pole fault occurs. The first action of the controllers is to gate block (microsecond time scale), the BPS close on all submodules to protect the semiconductors (millisecond time scale), and finally the ACCB open on both ends of the system isolating the unit from the rest of the grid. For pole-to-ground faults, the bypass switches are not needed since a natural ground occurs for current to flow towards. For the pole-to-pole fault, bypass switches are necessary because the current is continuously circulating through the unit. The component operating sequences are provided in Table 3.2.
Table 3.2: Circuit Breaker and BPS Operating Sequence after Fault Occurs
Fault Voltage Source Converter 1 Voltage Source Converter 2
ACCB BPS Controller ACCB BPS Controller
OFF Close Open Regulation DC Close Open Regulation Power
ON Close Open Regulation DC Close Open Regulation Power
ON Close Open GB Close Open GB
ON Close Close GB Close Close GB
ON Open Close GB Open Close GB
ON Open Close GB Open Close GB
The analysis presented from this point forward shows the sensitivity of transformer reactance, BPS speed response, and lumped inductance (arm and DC line reactance) on fault current magnitudes. A 25% transformer reactance, 0 mH DC line reactance, 10% arm reactance along the lower arms (asymmetric configuration), and 10 ms BPS operation speed is utilized to establish the base case DC peak current of 13.4 kA. The overhead line parameters associated with the study are taken from [84] and an electro-geometric model was built within PSCAD. Only pole-to-pole fault studies are evaluated and peak DC currents emphasized. Other variables
often considered by manufacturers include (1) the time to reach the maximum peak current, (2) rate of change in the current, (3) peak currents through the submodule diodes, and (4) I2T for the diodes.
3.2.1 Transformer Impedance Impact on Peak DC Current
The transformer reactance was varied from 10% to 25% per unit impedance with increments of 5% resulting in four cases. The peak DC currents for the four scenarios evaluated are provided in Figure 3.14. From experience, transformers within the United States market typically are designed for 25% impedance. These results support this design criteria. Peak DC current when pole-to-pole faults are applied are quite sensitive to the transformer impedance rating.
Figure 3.14: Transformer Reactance Impact on Peak DC Current
3.2.2 Bypass Switch Impact on Peak DC Current
The BPS speed of operation was varied from 5 ms to 11 ms. The peak DC currents for the seven scenarios evaluated are provided in Figure 3.15. Intuitively, these results make sense. The longer the BPS is inactive in the circuit, the more time the DC current has to reach its peak
potential. The purpose of the BPS is to protect the submodules by introducing an alternative path (short circuit) for the current to flow. The faster the BPS can be introduced into the network, the quicker the transient current can be suppressed resulting in a faster decay towards zero from which system restart could then be achieved. Peak DC current when pole-to-pole faults are applied are quite sensitive to BPS operation speed.
Figure 3.15: Bypass Switch Speed Impact on Peak DC Current
3.2.3 Reactor Impact on Peak DC Current
There are two reactor sets introduced into the MMC HVDC converter design – arm reactors placed either in an asymmetrical configuration (only along the bottom arm of each phase) or symmetrical configuration (both upper and lower arm placement) and the DC line reactors. Figure 3.16 provides the sensitivity results on the DC positive rail current if the DC line reactor varies from 0 to 100 mH. Similarly, Figure 3.17 provides the peak DC current results if the arm reactor varies from 5% to 10% per unit impedance. Interestingly, the peak DC currents are insensitive to changes in arm reactor size. Before the onset of the study, it is well known that DC line reactors contribute to fault current control – hence the name current limiting reactors (CLR) – and was conducted for completeness.
Figure 3.16: DC Line Inductor Impacts on Peak DC Current
Figure 3.17: Asymmetrical Arm Reactor Impact on Peak DC Current
Other exhaustive system studies on circuit component sensitivites can be evaluated including impacts of increasing overhead line length, system strength, and many others. These were conducted but only the most dramatic results from particular system components have been shown. Although not related to high power design (utility scale), a nice study was conducted in [85] showing the fault current dependence on cable length, chosen bus voltage, and number of interconnected sources within a meshed DC system.
3.3 ELECTRIC CHARACTERISTIC PREDICTION WITH REDUCED