ALTERNATIVAS DE SOLUCIÓN PARA EL MACRO PROCESO DE MANTENIMIENTO EN CAMPO

The Status register provides information about the primary interface to the system. Table 3-3 provides the specific details for each bit as they apply to a bridge.

Table 3-3: Status Register Status

Register

Bit Bit Function PCI-to-PCI Bridge Specific Notes

3::0 reserved These bits are reserved for future use by the PCI SIG and must be implemented as read-only bits, which return 0 when read.

4 Capabilities List

This bit indicates whether or not the bridge implements a Capabilities Pointer register pointing to a linked-list data structure of new capabilities. Support of the Capabilities List by a bridge is optional.

0 - the bridge does not support the Capabilities List 1 - the bridge supports the Capabilities List (Offset

34h is the pointer to the data structure)

5 66 MHz

Capable

This bit indicates whether or not the primary interface of the bridge is capable of operating at 66 MHz. Support of 66 MHz operation by a bridge is optional. This bit must be

implemented as a read-only bit.

0 - the primary interface of the bridge is not capable of 66 MHz operation

1 - the primary interface of the bridge is capable of 66 MHz operation

6 reserved This bit is reserved for future use and must be implemented as a read-only bit which returns 0 when read.

7 Fast Back-to-Back Capable

This bit indicates whether or not the primary interface of the bridge is capable of decoding fast back-to-back transactions when the transactions are from the same master but to different targets. (A bridge is required to support fast back-to-back transactions as a target from the same master.) This bit must be implemented as a read-only bit.

0 - the primary interface of the bridge is not capable of decoding fast back-to-back transactions to different targets

1 - the primary interface of the bridge is capable of decoding fast back-to-back transaction to different targets

8 Master Data Parity Error

This bit is used to report the detection of a parity error by the bridge when it is the master of the transaction. This bit is set if the following three conditions are all true:

• The bridge is the bus master of the transaction on the primary interface;

• The bridge asserted PERR# (read transaction) or detected PERR# asserted (write transaction); and

• The Parity Error Response bit in the Command register is set.

Once set, this bit remains set until it is reset by writing a 1 to this bit location. A bridge must implement this bit and the default state is 0 after reset.

0 - no parity error detected on the primary interface 1 - parity error detected on the primary interface 10::9 DEVSEL#

Timing

This read-only bit field encodes the timing of the primary interface DEVSEL# as listed below. The encoding must indicate the slowest response time that the bridge uses to assert DEVSEL# on its primary interface when it is responding as a target to any PCI transaction except¹ a Configuration Read or Configuration Write.

00 - fast DEVSEL# decoding 01 - medium DEVSEL# decoding 10 - slow DEVSEL# decoding 11 - reserved

11 Signaled Target-Abort

This bit reports the signaling of a Target-Abort termination by the bridge, when it responds as the target of a transaction on its primary interface. Once set, this bit remains set until it is reset by writing a 1 to this bit location. A bridge must implement this bit and the default state is 0 after reset.

0 - Target-Abort not signaled by the bridge on its primary interface

1- Target-Abort signaled by the bridge on its primary interface

1 The exception is for configuration commands since these are not subtractive decoded. By specifying the slowest time of all devices on a bus segment, the subtractive decode agent may be able to move in the time in which subtractive decode can occur.

12 Received Target-Abort

This bit reports the detection of a Target-Abort termination by the bridge when it is the master of a transaction on its primary interface. Once set, this bit remains set until it is reset by writing a 1 to this bit location. A bridge must implement this bit and the default state is 0 after reset.

0 - Target-Abort not detected by the bridge on its primary interface

1 - Target-Abort detected by the bridge on its primary interface

13 Received Master-Abort

This bit reports the detection of a Master-Abort termination by the bridge, when it is the master of a transaction on its primary interface. Once set, this bit remains set until it is reset by writing a 1 to this bit location. A bridge must implement this bit and the default state of this bit is 0 after reset.

0 - Master-Abort not detected by the bridge on its primary interface

1 - Master-Abort detected by the bridge on its primary interface

14 Signaled System Error

This bit reports the assertion of SERR# by the bridge on its primary interface. Once set, this bit remains set until it is reset by writing a 1 to this bit location. A bridge must implement this bit and the default state is 0 after reset.

0 - SERR# not asserted by the bridge on its primary interface

1 - SERR# asserted by the bridge on its primary interface

15 Detected Parity Error

This bit reports the detection of an address or data parity error by the bridge on its primary interface. This bit must be set when any of the following three conditions is true:

• Detects an address parity error as a potential target;

• Detects a data parity error when the target of a write transaction; or

• Detects a data parity error when the master of a read transaction.

The bit is set regardless of the state of the Parity Error Response bit (bit 6) in the Command register. Once set, this bit remains set until it is reset by writing a 1 to this bit location.

A bridge must implement this bit and the default state is 0 after reset.

0 - address or data parity error not detected by the bridge on its primary interface

1- address or data parity error detected by the bridge on its primary interface