Although the 1-dimensional style proposed by Uehara and vanCleemput [Uv81] and variations thereof has dominated theoretic advances as well as practical implementation of transistor-level layout tools, some authors have considered layout styles that extend to the 2-dimensional plane without be- ing restricted to prescribed rows and without being constrained to a highly regular structure as employed by gate matrices or PLAs.
3.9. FREE-FORM TWO-DIMENSIONAL LAYOUTS 45 cells is due to Luhukay and Kubitz [LK82]. The placement strategy comprises a set of heuristics that arrange standard cells in a “better than random” way and applying local optimization steps. However, the geometry generation phase does not just insert handcrafted layouts from the standard cell library, but uses algorithmically defined “subcells” to generate the shapes based on design rules and device sizes. It is also worth mentioning, because uncom- mon at the time, that one of the possible layout schemes uses two instead of just one metal layer for the wiring.
The toolset presented in [WNMD83] has several characteristics of more mod- ern VLSI tools aimed at a higher hierarchy level. It consists of a force-directed placement routine working directly on transistors, a torque-directed orienta- tion routine rotating the placement objects, a wiring phase that connects nets with minimum spanning trees or a track-based method, an assignment of 2- point connections to the available layers and a routing step that heuristically realizes 2-point connections with L shapes such that the number of shorts is as small as possible.
In [NJ85] the netlist is transformed to several auxiliary graphs to which sev- eral algorithms are applied in order to obtain a realizable embedding of the netlist into the three available layers, namely diffusion, polysilicon and metal. The techniques include a partitioning into maximal 2-vertex-connected com- ponents, a subroutine of the planarity testing algorithm by Hopcroft and Tarjan [HT74] that generates a hierarchy of paths covering a graph, and a 2-coloring satisfying certain properties.
A 2-dimensional layout scheme which is based on the formation of n-FET/p- FET pairs is proposed in [MAU86]. The placement algorithm first computes a heuristic 1-dimensional array of the transistor pairs and then folds this row in a zig-zag fashion. Later, local improvement steps are applied. The routing module consists of a modified maze router [Lee61] that works on the single metal layer which is not used by the transistors themselves.
Poirier [Poi89] describes a system that arranges arbitrary CMOS netlists be- tween two horizontal power strips. However, the distance of the power strips is not fixed and the tool is able to place FETs in more than two rows. The heuristic method groups transistors to clusters and enumerates possible placements of those clusters, including possibilities to fold single FETs. In [FSA95] transistors are grouped by simulated annealing into chains which can be placed without diffusion gaps. The chains are abstracted as rectangles and placed with a floorplanning technique that involves recursively slicing the cell area with vertical and horizontal cuts. The transistor chains can be rotated by multiples of 90 degrees such that layouts are generated that have gate contacts with non-uniform direction. After the routing step, which is based on a depth first search on a regular grid graph, a final compaction method transforms the symbolic layout into geometric shapes.
Rekhi et al. [RTL95] describe what they call 1-1
2-dimensional cells. Here a
tal power rails bordering the cell outline at the top and the bottom side, but instead of forcing the n-FETs near the GND potential and the p-FETs near the VDD potential, n-FETs and p-FETs are allowed to mix in both of the transis-
tor rows. The algorithm uses a heuristic to pair transistors that may be of the same type, then computes groups of transistor pairs that can be placed without diffusion gap, and finally places the groups in a branch and bound method minimizing the number of connections which have to cross a gap. AKORD, a software by Serdar and Sechen [SS99], combines the free-form 2-
dimensional layout style involving vertical and horizontal gates with tran- sistor folding. In addition, “black boxes” are supported—already laid out circuits that can be inserted into a layout and form a new level of hierarchy. The placement method is based on simulated annealing and primarily targets the total wire length. In this approach, transistor grouping and folding can be handled within the placement phase and must not be fixed in advance. Riepe and Sakallah [RS99, RS03] describe a full 2-dimensional cell layout tool, TEMPO, that rotates transistors by multiples of 90 degrees. Similar to pre-
vious 2-dimensional approaches, the placement step is based on simulated annealing. However, it allows more degrees of freedom as it does not rely on statically formed chains of transistors but reconfigures chains and reassigns transistors within the placement phase. Other differences to earlier systems are that TEMPO uses the sequence pair representation of rectangle packings
([MFNK95]) to explore the search space and that it allows for more complex cases of geometry sharing between three or more transistors.