3.5 ANALISIS ESTADISTICO
3.4.3 ETAPA EXPERIMENTAL
3.4.3.4 ANÁLISIS DEL ALIMENTO (PASTIZAL)
When coding in Verilog for synthesis, sometimes a designer may want to code a memory array. Coding a memory array is common in behavioral coding and synthesizable coding, but for synthesis, the memory array may be limited to only a small array.
In synthesis, when a one-bit memory cell is coded, it is synthesized to a multiplexer and a flip-flop. Representation of a one-bit memory cell with a multiplexer and a flip-flop is definitely a waste of silicon real estate. However, even though a memory cell is rather large in terms of die area, it is still common for a designer to code a memory array provided that the array is small. A good example would be when a designer needs a small set of regis-ters to store certain values. Or a designer may also code a memory array for synthesis when designing a microcontroller or microprocessor that may need a small register file.
Figure 4.34 shows a diagram of a synthesized logic for a one-bit memory cell. Synthesizing a large array of memory cells is a waste of silicon area. However, synthesizing memory cells is rather simple when coding in synthesizable Verilog compared with schematic capturing of the same array.
Example 4.60 shows a Verilog code for a 1-kilobyte memory module that is synthesizable. However, the designer can take note that, although the Verilog code is simple and easy, synthesis of the code may take several minutes
MEMORY ARRAY 127
longer than it does on other simple Verilog code, because this short piece of code synthesizes to 1 kilobyte of memory.
Example 4.60 Verilog Code for a 1-kilobyte Memory Array
module memory (addr, data_in, data_out, write, read, clock, reset);
// 1kbyte memory module - 128 address x 8 bits input [6:0] addr;
input [7:0] data_in;
input write, read, clock, reset;
output [7:0] data_out;
reg [7:0] data_out;
reg [7:0] memory [127:0];
integer i;
// asynchronous reset
always @ (posedge clock or posedge reset) begin
if (reset) begin
D
CLK
Q input
select
output
clock
FIGURE 4.34. Diagram showing synthesis representation of a one-bit memory cell.
data_out = 0;
// to initialize all memory to zero for (i=0; i<128; i=i+1)
memory[i] <= 0;
end else
begin
if (read)
data_out <= memory [addr];
else if (write) begin
data_out <= 0;
memory [addr] <= data_in;
end end
end
endmodule
Example 4.61 shows a Verilog test bench that can be used to simulate the memory module shown in Example 4.60.
Example 4.61 Verilog Test Bench Module “memory_tb” to Simulate Module “memory”
module memory_tb ();
reg [6:0] address, addr;
reg [7:0] data, data_in;
reg write, read, clock, reset;
wire [7:0] data_out;
parameter cycle = 20;
integer i;
initial begin
addr = 0;
reset = 0;
read = 0;
write = 0;
data_in = 0;
clock = 0;
forever #20 clock = ~clock;
end
MEMORY ARRAY 129
initial begin
// for reset reset = 0;
#cycle;
reset = 1;
#cycle;
reset = 50;
#cycle;
for (i=10; i<15; i=i+1) begin
address = i;
data = i;
memory_write (address, data);
#cycle;
end
for (i=14; i>=10; i=i-1) begin
address = i;
memory_read (address);
#cycle;
end
$stop;
end
task memory_write;
input [7:0] data;
input [6:0] address;
begin
addr = address;
data_in = data;
write = 0;
#cycle;
write = 1;
read = 0;
repeat (2) #cycle;
write = 0;
#cycle;
$display ("Completed writing data %h at address
%h", data_in, addr);
end endtask
Declaration of task
“memory_write” for writing data to memory at location “address”
task memory_read;
input [6:0] address;
begin
read = 0;
addr = address;
data_in = 0;
#cycle;
read = 1;
repeat (2) #cycle;
read = 0;
#cycle;
$display ("Completed reading memory at address
%h. Data is %h", addr, data_out);
end endtask
memory memory_inst (addr, data_in, data_out, write, read, clock, reset);
endmodule
Figure 4.35 is a diagram showing the waveform results of Verilog test bench module “memory_tb.”
Referring to Figure 4.35:
MEMORY ARRAY 131
Task “memory_read” for reading memory from location “address”
A B C D E E D C B A
clock
A B C D E 0
data_in[7:0]
0 E D C B A
data_out[7:0]
read reset write
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
addr[6:0]
FIGURE 4.35. Diagram showing simulation waveform for Verilog test bench module
“memory_tb”
1. On rising edge of clock 1, 3, 5, 6, 8, 10, 11, and 13, read and write is at logical “0”. No reading or writing to memory occurs.
2. On rising edge of clock 2, 4, 7, 9, and 12, write is at a logical “1”. A memory write occurs at address addr(6:0) with data data_in(7:0).
• On rising edge of clock 2, addr(6:0) = “A”, data_in(7:0) = “A”, write= ‘1’ Æ memory write at address “A” with data “A”.
• On rising edge of clock 4, addr(6:0) = “B”, data_in(7:0) = “B”, write= “1” Æ memory write at address “B” with data “B”.
• On rising edge of clock 7, addr(6:0) = “C”, data_in(7:0) = “C”, write= “1” Æ memory write at address “C” with data “C”.
• On rising edge of clock 9, addr(6:0) = “D”, data_in(7:0) = “D”, write= “1” Æ memory write at address “D” with data “D”.
• On rising edge of clock 12, addr(6:0) = “E”, data_in(7:0) = “E”, write= “1” Æ memory write at address “E” with data “E”.
3. On rising edge of clock 15, 16, 18, 20, 21, 23, and 25 read and write is at logical “0”. No reading or writing to memory occurs.
4. On rising edge of clock 14, 17, 19, 22, and 24, read is at a logical “1”. A memory read occurs at address addr(6:0) and output data_out(7:0) is driven with data from the memory module.
• On rising edge of clock 14, addr(6:0) = “E”, read = “1” Æ memory read at address “E”. Data read is “E” and is shown on data_out(7:0).
• On rising edge of clock 17, addr(6:0) = “D”, read = “1” Æ memory read at address “D”. Data read is “D” and is shown on data_out(7:0).
• On rising edge of clock 19, addr(6:0) = “C”, read = “1” Æ memory read at address “C”. Data read is “C” and is shown on data_out(7:0).
• On rising edge of clock 22, addr(6:0) = “B”, read = “1” Æ memory read at address “B”. Data read is “B” and is shown on data_out(7:0).
• On rising edge of clock 24, addr(6:0)= “A”, read = “1” Æ memory read at address “A”. Data read is “A” and is shown on data_out(7:0).