Análisis de la factibilidad de la aplicación de los instrumentos metodológicos

The SYS68K/CPU-60 may be used as system controller when plugged into slot 1 but the slot-1 functions (see below) are only enabled when the SYS68K/CPU-60 is detected as slot-1 device. The slot-1 functions are also called system controller functions.

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IMPORTANT Malfunction

If not on an active backplane,

• remove the jumper on the backplane connecting BG3IN and BG3OUT for the SYS68K/CPU-60 slot.

• assemble the jumpers for BGIN and BGOUT on lower and higher slots on the backplane where no board is plugged.

Hardware VMEbus Slot-1

3.17.1 Slot-1 (System Controller) Functions

When the CPU board is a slot-1 device, the hardware of the SYS68K/CPU-60 sets up the required system controller functions: • drive SYSCLK to VME (see section 3.17.4 “The SYSCLK Driver” on

page 88),

• use VMEbus arbitration level 3, instead of the level selected by SW6-3 and SW6-4 (default “OFF OFF = level 3 (BR3*)”, see page 12), • drive floating bus grant levels 0, 1, and 2 to a high level signal,

• and allow the SYS68K/CPU-60 bus timer to terminate VME cycles (timeout), if it is enabled (see section 3.17.5 “VMEbus Timer” on page 89).

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IMPORTANT The arbiter of the FGA-002 will not automatically be set by hardware when detecting slot-1 by switch setting or auto-detection. It must be en- abled by software if the CPU board is system controller (e.g., FGA Boot enables the arbiter automatically). For more information on the FGA-002 arbiter, see the FORCE Gate Array FGA-002 User’s Manual.

3.17.2 Slot-1 Detection

Auto-detection The board’s slot-1 auto-detection mechanism probes the VMEbus bus- grant-in-level-3 pin (BG3IN) during power up to see whether it is possi- ble to pull this signal down to a low signal level.

• When the SYS68K/CPU-60 is plugged into slot 1, it will succeed in pulling the VME signal to a low signal level, because BG3IN is float- ing on slot 1. Hence, the CPU board detects slot 1.

• When the CPU-60 is not plugged into slot 1, it will receive the BG3IN from a board plugged into a lower slot. It will fail trying to pull the VME signal to a low signal level. Hence, the CPU board does not detect slot 1.

Manual detection The following situation may cause the SYS68K/CPU-60 to conclude that slot-1 is detected although being in a different slot:

A VMEbus system begins with the highest daisy-chain priority at slot 1, the left most slot. As the slots move right they lose daisy-chain priority, so slot 2 has higher daisy-chain priority over slot 3, and slot 3 has higher daisy-chain priority over slot 4, and so on. After powering up, auto-detection may fail when another board is plugged into a slot with lower daisy-chain priority. This results in the board (incorrectly) not driving its bus-grant-out-level-3 (BG3OUT) on the VMEbus to the high signal level as defined by the VME specification.

VMEbus Slot-1 Hardware 2040 77 J une 1999; las t doc um ent at ion c hange wit h S Y S 68K /C P U -6 0 P CB Rev . 0. 1

In this situation the SYS68K/CPU-60 probes its BG3IN at a low signal level and concludes that slot 1 is detected. However, the conclusion does not fit the actual system setup. To prevent this mismatch you can

• disable the auto-detection by setting SW6-1 appropriately: ON = dis- abled (also called manual mode) (default “OFF”, see page 12)

• and enable the slot-1 functions manually by setting SW6-2 appropri- ately: ON = enabled (default “OFF”, see page 12). For SW6-2 to take any effect SW6-1 must be ON = disabled (also called manual mode).

3.17.3 Slot-1 Status Register

The status of the slot-1 detection or manual mode SW6-2 configuration may be read via the slot-1 status register atFF80.1000₁₆. It is a read- only register.

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IMPORTANT Malfunction

Writing to the slot-1 status register may cause malfunctions of the CPU board.

• Never write to the slot-1 status register.

S1STAT S1STATindicates whether slot-1 has been detected (by auto-detection or because of switch setting, see "SW6-1" and “SW6-2” on page 12). =0 Slot 1 has been detected.

=1 Slot 1 has not been detected.

3.17.4 The SYSCLK Driver

The CPU board contains all necessary circuits to support the SYSCLK signal. The output signal is a stable 16 MHz signal with a 50% duty cy- cle. The driver circuitry for the SYSCLK signal can source a current of 64 mA.

The SYSCLK signal will be enabled if slot-1 has been detected (by auto- detection or because of switch setting, see "SW6-1" and “SW6-2” on page 12).

Table 49 Slot-1 status register (RO)

FF80.1000₁₆

Bit 7 6 5 4 3 2 1 0

Hardware Serial I/O – SCC AM 85C30

3.17.5 VMEbus Timer

The FGA-002 disposes of a bus timer to terminate VME transfers gener- ating a bus error when no acknowledge can be detected after a timeout period.

In addition to the FGA-002 bus timer, the SYS68K/CPU-60 provides a VMEbus timer. This timer can only be enabled when the CPU board pro- vides system controller functions. The SYS68K/CPU-60 VMEbus timer is controlled by the timer within the memory controller. The timeout peri- od can be configured by the register for the timer within the memory con- troller (see section 3.8.2 “Memory Configuration Register” on page 54).