In this section we return to an earlier idea of virtual gate [4]. In ref. [4], focus was laid on understanding VDS SAT in BAVETs for different InAlAs. It should be recalled that the phenomenon of virtual gate was derived when LGA = 0 µm in BAVETs. Another aspect of the analysis was that virtual gate was derived for the case of ID MAX increasing
present study wherein ID MAX remains fixed despite the change in RON - a phenomenon identified as drain-resistance effect.
ID MAX not changing with LGA is a clear evidence that virtual gate has not changed with LGA. If it is assumed that virtual gate and drain-resistance are not interdependent, then in removing the drain resistance, or the corresponding VX, we essentially remove the LGA dependence from BAVETs. The result of this is that, firstly VDS SAT for the case of LGA MAX is similar to that shown in ref. [4], wherein LGA was 0. Secondly, BAVETs with LGA MAX show a dependency of VDS SAT on InAlAs doping which is identical to that of ref. [4]. One can then argue that virtual gate may exist in BAVETs with LGA MAX as they do in those with no LGA.
A.11
Conclusion
LGA extension of the gate electrode in i-BAVETs was shown to have incremental effects on VKNEE and RON. An explanation was availed in parallelism drawn with drain resistance of FETs. In increasing LGA in BAVETs, a parasitic drain resistance of RX was introduced. The voltage absorbed by RX amounted to the voltage by which VKNEE increases as a function of LGA.
The investigation then focused on finding the part of the conduction path contributing to this resistance. Between RCH,LGO, RCH,LAP and RWBI,LAP, we succeeded in eliminating the first two as the possible factors by means of two experiments. The constant nature of ID MAX for different LGA supported the argument of RXbeing unrelated to RCH,LGO. For the role of RCH,LAPin inducing RX, two boundary conditions were formulated and checked for in i- and p-BAVETs. The test of the boundary conditions yielded results contrary to expectations, and thus challenged the likelihood that RX appeared as RCH,LAP. By the
resistance in question. The same resistance also leads to the anomalous factor of VX in VKNEE.
Had it not been for the gate-potential affecting the boundary conditions of RCH,LAP and RWBI,LAP in different ways, it would have been difficult to recognize RXas RWBI,LAP. The experimental approach can be a method determining the resistance of a WBI.
Reducing LGAin i- and p-i-BAVETs reduces the impact of RWBI,LAP. LGA dependence was made non-existent by using p-doping for the entirety of InAlAs thickness in BAVETs. Studying the impact of LGA in conjunction to InAlAs doping variations thus addressed another significant aspect that RWBI,LAP can be controlled in BAVETs. And as RWBI,LAP represents aperture conductivity, the latter can be influenced as well. A hypothesis was proposed that links the control mechanism to the behavior of traps at WBI. On the basis of which it was stated that the presence of traps is the reason for LGA dependence observed in BAVETs. Mitigating traps is the way to reducing RWBI,LAP.
In general, BAVETs can be impacted in their VKNEE through two parasitic effects, namely virtual gate and drain resistance. Both of which can be overcome by the method of p-doping in gate-barrier layer.
Further studies are needed to accurately model resistance and distribution of elec- trostatic field in the aperture regions of the channel, and WBI. One of the studies on RWBI,LAP in devices with different aperture widths is presently ongoing and will be pre- sented in a future work. Additionally, breakdown in BAVETs with different LGA needs to be reviewed as we expect drain resistance to influence the breakdown. How doping the gate barrier impacts passivation of traps at WBI is an interesting phenomenon that, too, will be presented in a future study.
However, this study has succeeded in answering the following questions: (a) Which one of the factors, resistance or threshold voltage, makes VDS SAThigh as LGAis increased?
whether it is in the channel or aperture? It is the region of WBI sandwiched between channel and aperture. (c) What mechanism explains relationship between resistance of WBI with electrostatic field and gate-barrier doping? The impact arises in both modifying the activity of traps at WBI.
References
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Appendix B
Higher Gate-Aperture Overlap for
Improved Pinch-off
B.1
Introduction
A transistor design aimed at achieving power-switching operation at high frequencies was developed in the form of a Bonded Aperture Vertical Electron Transistor (BAVET) (see Fig. B.1) [1]. The design is based on a current aperture vertical electron transistor (CAVET) in which the drain-layer is buried underneath the channel region [2, 3]. Using the technique of wafer-bonding in a CAVET enables integration of epitaxially distinct material systems for the channel and drift-regions. Thus, the advantages offered by the physical properties of two material-systems can be favorably adopted into a wafer- bonded transistor. In this work, an In0.53Ga0.47As (InGaAs) channel and a III-Nitride (III-N) based drift-region are chosen to simultaneously achieve a high-injection velocity (injection velocity ' 2.75 × 107 cm/sec for InGaAs field-effect transistors) and a high- breakdown voltage (breakdown-field for GaN = 3.3 MV/cm) (see Fig. B.1(a)) [4, 5].
source, and drain electrodes marked by G, S, and D, respectively. Electron-conduction in the device is shown by solid arrows. The specified dimensions are the aperture length (LAP), gate-CBL overlap (LGO), and gate-aperture overlap (LGA).
the InGaAs channel, and then vertically through the III-N drift-region (see Fig. B.1(b)). In the III-N region, ion-implanted current-blocking regions (referred to as current-blocking- layer or CBL) confine the current path to a narrow conductive region called the aperture (defined by LAP in Fig. B.1(b)). In addition to isolating the current-path, the CBL also acts as a back-barrier for the InGaAs channel. Owing to the vertical topology of the device, the gate-electrode can be lithographically defined such that it controls the charge in two regions of the InGaAs channel, wherein one part of the gate-dimension overlaps with the CBL-region (LGO) and the remainder overlaps with the aperture-region (LGA) (see Fig. B.1(b)). The LGOdimension enforces channel-modulation, and the LGA controls the electric-field profile in the vicinity of the aperture-CBL edge, and thus, functions as a field-plate. We investigate herein the factors impacting the channel-pinch-off by studying its dependence on the LGO and LGA dimensions.