These are the more complex colour transformations, which are better models for human colour perception. These colour spaces decouple the colour information from the intensity and the saturation information in order to preserve the values after non-linear processing. They include;
Karhunen-Loeve Colour Coordinate System
HSV Colour Coordinate System
HSI/LHS/IHS Colour Coordinate System
We will focus on the HSI and HSV colour spaces in this section.
The architecture for the conventional RGB2HSI described in [] is depicted in Figure 6.4(i).
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Figure 6.4(i) – RGB2HSI colour converter hardware architecture
The results for HSI implementation are shown in Figure 6.4.
For further information on this implementation, refer to references at the end of the chapter. The conventional HSI conversion for a hardware synthesis is extremely difficult to implement accurately in digital hardware without using some floating point facilities or large LUTs.
The results of the implementation are shown in Figure 6.4(ii) where the last two images show the results when the individual channels are processed and recombined after being output and the latter is before being output.
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From visual observation, the hardware simulation results are quite good.
Figure 6.4(ii) – Software and hardware simulation results of RGB2HSI converter
The equations for conversion to HSV space are :
(6.4-5)
(6.4-6)
(6.4-7)
The diagram of the hardware architecture for RGB to HSV colour space conversion is shown in Figure 6.4(iii). Note the division operations and the digital hardware constraints and device a solution for implementing these dividers in a synthesizable circuit for typical FPGA hardware.
)
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Figure 6.4(iii) – Hardware architecture of RGB2HSV converter
The synthesizable HSV conversion is relatively easy to implement in digital hardware without floating point or large LUTs.
The results of VHDL implementation are shown in Figure 6.4(iv). Compare the hue from the HSV to the HSI and decide which one is better for colour image processing.
(a) (b) (c)
Figure 6.4(iv) – (a) Software and hardware simulation results of RGB2HSV converter for (b) individual component channel processing and (c) combined channel processing
95
The implementations of these non-linear colour converters are quite involved and much more complicated than the VHDL implementations of the other colour conversion algorithms. architectures to form a hardware image processing pipeline.
It should also be kept in mind that the architectures developed here are not the most efficient or compact but provide a basis for further investigation by the interested reader.
References
W. K. Pratt, Digital Image Processing, 4 ed.: Wiley-Interscience, 2007.
R. C. Gonzalez, R. E. Woods, and S. L. Eddins, Digital Image Processing Using MATLAB: Prentice Hall, 2004.
R. C. Gonzalez and R. E. Woods, Digital Image Processing, 2 ed.: Prentice Hall, 2002.
U. Nnolim, “FPGA Architectures for Logarithmic Colour Image Processing”, Ph.D. thesis, University of Kent at Canterbury, Canterbury-Kent, 2009.
MathWorks, "Image Processing Toolbox 6 User's Guide for use with MATLAB," The Mathworks, 2008, pp. 285 - 288.
Weber, "The USC-SIPI Image Database," University of South Carolina Signal and Image Processing Institute (USC-SIPI), 1981.
E. Welch, R. Moorhead, and J. K. Owens, "Image Processing using the HSI Colour space," in IEEE Proceedings of Southeastcon '91, Williamsburg, VA, USA, 1991, pp. 722-725.
T. Carron and P. Lambert, "Colour Edge Detector using jointly Hue, Saturation and Intensity," in Proceedings of the IEEE
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International Conference on Image Processing (ICIP-94), Austin, TX, USA, 1994, pp. 977-981.
Andreadis, "A real-time color space converter for the measurement of appearance," Journal of Pattern Recognition vol. 34 pp. 1181-1187, 2001.
EETimes, "PLDs/FPGAs," 2009.
Xilinx, "XST User Guide ": http://www.xilinx.com, 2008.
97 Circuit Schematics
Appendix A contains the schematic design files and the device usage summary generated from the synthesized VHDL code (relevant sample code sections are also included) using the Xilinx Integrated Software Environment (ISE) synthesis tools.
.
APPENDIX A
98 .
Figure A1 – Demosaicking RTL schematic1
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Figure A2 – Demosaicking RTL schematic2
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Figure A3 – Demosaicking RTL schematic3
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Figure A4 – Demosaicking RTL schematic4
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Figure A5 – Demosaicking RTL schematic5
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Figure A6 – Demosaicking RTL schematic6
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Figure A7 – Demosaicking RTL schematic7
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Figure A8 – Colour Space Converter RTL schematic
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Creating Projects/Files in VHDL Environment Appendix B contains the continuation guide of setting up a project in ModelSim and Xilinx ISE environments.
APPENDIX B
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Figure B1 – Naming a new project
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Figure B2 – Adding a new or existing project file
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Figure B3 – Creating a new file
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Figure B4 – Loading existing files
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Figure B5 – Addition and Selection of existing files
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Figure B6 – Loaded files
Figure B7 – inspection of newly created file
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Figure B8 – Inspection of existing file
Figure B9 – Compilation of selected files
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Figure B10 – Compiling Loaded files
Figure B11 – Successful compilation
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Figure B12 – Code Snippet of newly created VHDL file
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Figure B13 – Adding a new VHDL source in an open project
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Figure B14 – Adding an existing file to an open project
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VHDL Code
Appendix C lists samples of relevant VHDL code sections.
APPENDIX C
119 example_file.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
----TOP SYSTEM LEVEL DESCRIPTION--- entity example_file is
port ( ---the collection of all input and output ports in top level
Clk : in std_logic; ---clock for synchronization
rst : in std_logic; ---reset signals for new data
input_port : in bit; ---input port output_port : out bit); ---output port end example_file;
---architecture and behaviour of TOP SYSTEM LEVEL DESCRIPTION in more detail
architecture behaviour of example_file is
---list signals which connect input to output triggered by clock or reset pin
begin
if rst = '0' then --reset all output ports intermediate_port <= '0'; --initialize output_port <= '0'; --initialize elsif clk'event and clk = '1' then --operate on rising edge of clock
intermediate_port <= not(input_port); --logical inverter
output_port <= intermediate_port or input_port; --logical or operation
end if;
end process; --self-explanatory
end behaviour; --end of architectural behaviour
120 ---NTSC CONVERSION COEFFICIENTS USING Y, I, Q --- constant coeff0 : std_logic_vector(15 downto 0):= "0001001100100011"; -- 0.299
constant coeff1 : std_logic_vector(15 downto 0):= "0010010110010001"; -- 0.587
constant coeff2 : std_logic_vector(15 downto 0):= "0000011101001100"; -- 0.114
constant coeff3 : std_logic_vector(15 downto 0):= "0010011000100101"; -- 0.596
constant coeff4 : std_logic_vector(15 downto 0):= "1110111001110111"; -- -0.274
--- constant coeff5 : std_logic_vector(15 downto 0):= "1110101101100100"; -- -0.322
constant coeff6 : std_logic_vector(15 downto 0):= "0000110110000001"; -- 0.211
constant coeff7 : std_logic_vector(15 downto 0):= "1101111010000111"; -- -0.523
constant coeff8 : std_logic_vector(15 downto 0):= "0001001111111000"; -- 0.312
--- --End colour Coefficients--- constant data_width : integer := 16;
end colour_converter_pkg;
---
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Data_out_valid : out std_logic );
end colour_converter;
architecture struct of colour_converter is
signal x11, x12, x13, X21, x22, x23, x31, x32, x33 : std_logic_vector(data_width-1 downto 0);
signal m0, m1, m2, m3, m4, m5, m6, m7, m8 :
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m4 <= signed('0'&x22)*signed(coeff4);
m5 <= signed('0'&x23)*signed(coeff5);
m6 <= signed('0'&x31)*signed(coeff6);
m7 <= signed('0'&x32)*signed(coeff7);
m8 <= signed('0'&x33)*signed(coeff8);
----addition---
a10 <= (m0(32)&m0)+m1+m2;
a20 <= (m3(32)&m3)+m4+m5;
a30 <= (m6(32)&m6)+m7+m8;
----output---
Data_out_valid <= '1';
X <= conv_integer(a10(24 downto 14));
Y <= conv_integer(a20(24 downto 14));
Z <= conv_integer(a30(24 downto 14));
end struct;
123 averaging filter ... 75
background ... 68
Bayer Colour Filter Array ... 38
Bilinear ... 42
circularly symmetric ... 75
CMY ... 79, 81 colour filter array ... 37, 40 colour image processing ... 94
Colour Image Processing .. 1, 2, 23, 36, 68, 77, 95 derivative filters ... 70, 73, 74 display range ... 73 Edge-sensing Bilinear ... 42
Edge-sensing Bilinear 2 ... 42
embossing... 73 Floating point calculations .... 21
floating point cores ... 21
foreground ... 68
Fourier transform ... 3
Fourier Transform... 3
FPGAs ... 6
frame rate ... 56
Frequency . 2, 23, 36, 56, 65, 86 Domain ... 2
Gamma Correction ... 37, 62, 63 Gaussian 30, 32, 43, 44, 75, 76,
hardware simulation . 52, 53, 89 HDL ... 6, 18 high boost filtering ... 77
high frequency components . 64, 73, 75 Histogram Clipping 37, 62, 63 histogram equalization... 78
Homomorphic filter ... 66, 67, 68 HSI/LHS/IHS ... 91
HSV ... 91, 93, 94 ICC profiles ... 80
IEEE libraries ... 11
Illuminance/Reflectance ... 66
124 Image Enhancement ... 1, 59, 69 Image Reconstruction ... 1 image scene ... 66, 68 integration ... 74 interpolating filter ... 38 Karhunen-Loeve ... 91 kernel coefficients ... 64, 74 Laplacian ... 44, 64, 70, 77 line buffers ... 27, 47 linear 21, 22, 35, 39, 44, 45, 47, 53, 57, 59, 64, 65, 78, 91, 95 linear interpolation... 57 logarithm transform ... 60, 65 logarithmic ... 62, 64, 65, 69 look-up-table (LUT) ... 22 low frequency components... 74 LUT ... 22, 60, 61 mat2gray ... 73 MATLAB ....vi, 6, 19, 20, 23, 36,
44, 45, 46, 63, 69, 72, 73, 77, 82, 85, 95
maximum frequency ... 56 mean filters ... 75 median ... 5 median and variance filters .... 5 ModelSim .... 6, 7, 8, 14, 15, 16,
18, 54, 106
morphological ... 78 multipliers ... 27, 48 multiply-accumulate . 28, 30, 32,
34
natural logarithm ... 60 Nearest Neighbour ... 42 neighbourhood ... 1, 64, 75
kernel ... 4 Non-linear ... 4 open source ... 6 partial differential equations .. 70 passband ... 73 shift registers ... 27, 47 signal . 2, 13, 14, 21, 22, 26, 46, Smooth Hue Transition ... 42 smoothing ... 44, 70, 74, 75, 77 Sobel ... 44, 70, 71, 72, 74, 77 Spatial ... 2, 4, 5, 25, 69 Domain ... 2 Spatial domain ... 4, 5 Spatial domain filtering ... 5 spatial filtering ...4, 6, 25, 26, 65 spatially varying ... 65
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sRGB ... 79
Symmetric filter ... 32
textio... 18
tone ... 59
Unified Model Language (UML) ... 19
un-sharp masking ... 64
Unsharp masking ... 64
unsigned ... 54, 73 Variable Number Gradients .. 42
Verilog ... 6
window generator 26, 27, 29, 47 Xilinx .... 6, 7, 14, 15, 16, 17, 18, 23, 24, 36, 54, 56, 68, 69, 96, 97, 106 Xilinx Project Navigator . 14, 15, 17 YCbCr ... 82, 88 YIQ NTSC ... 82
YUV ... 82