of the oxide wall is almost nullified. The substrate capacitance is now deter- mined by the capacitance of the buried layer to the substrate. As the isolation wall is now oxide it is allowed to touch the buried layer and consequently the transistor size can be considerably reduced and the substrate capacitance re- duces even further. When the high-doped isolation wall touches the high-doped buried layer, a junction is formed which is highly doped at both sides. Conse- quently, the breakdown voltage can be as low as just a few volt. For low-voltage circuits (1 V) this does not need to be a problem and this can thus be used to reduce the parasitic substrate capacitance when no oxide isolation is available.
The (MOS)FET The effective transit frequency, of the (MOS)FET can be defined as [16]:
where is the gate-source capacitance, is the gate-bulk capacitance and is the transconductance of the (MOS)FET. The gate-source capacitance depends on the mode of operation of the MOSFET. For moderate and strong inversion it is about 60 % of the gate-oxide capacitance whereas it reduces to almost zero for weak inversion.
The (MOS)FETs are self-isolating devices and, consequently, they do not have the corresponding relatively large substrate capacitance as the bipolar transistor does. The parasitic capacitances to the bulk are found at the drain and source contact. A part of these parasitics is caused by the channel-to-bulk capacitance for the MOSFET.
For the JFET it depends on the type whether the parasitic from the channel to the bulk is absent or not. When the gate of JFET completely encloses the channel, the channel is isolated from the bulk and consequently the parasitic capacitance from the channel to bulk is zero. The parasitic from the gate to the bulk can be relatively large now, as the gate-bulk junction now has a relatively large area.
The JFET is, compared with the MOSFET and bipolar transistor, a rather bulky element and, consequently, relatively slow. Its application is therefore mostly in the field of low-frequency controlled resistance.
Resistors The bandwidth of resistors also reduces when a low current con- sumption is required. When currents are in the region and the voltages required across resistors are still in range of several volt, resistances become very high. When these resistances are realized on chip, the resistors get relatively large and, consequently, the parasitic capacitances to the substrate are consid- erable. Analogous to interconnects on a chip, these relatively large resistors
64 CHAPTER 3. LOW-VOLTAGE LOW-POWER DESIGN
can be modeled by a distributed RC network, see figure 3.15. In the literature a lot has been published concerning approximations of distributed networks in order to predict the step-response of an interconnect modeled as a distributed RC network [17], [18] and [19]. The approximations are based on time-domain considerations. Analog design, however, is preferably done in the frequency do- main and does not use the step-response but instead uses phase and amplitude of signals. Therefore, these approximations are not the appropriate ones. Other publications deal with frequency domain approximations [20]; however, these approximations assume a frequency much lower than the first pole. For low- current applications this does not need to be true. Therefore, some attention is paid here to the frequency behavior of high-ohmic resistors modeled as dis- tributed RC networks. The analysis is based on the calculations done by Deily [18] and Zurada [21].
Resistors can be used in four ways, see figure 3.16: one-port configuration V/I;
two-port configuration I/V;
two-port configuration, voltage divider; two-port configuration, current divider.
3.4. LOW CURRENT 65
The current divider can be seen as the resistor as one-port for which the port impedance is important and is therefore not separately analyzed. The influence of the distributed parasitics is different in the other three situations. For the one-port configuration, the impedance can readily be found as:
where is the Laplace variable, is the DC resistance and C is the total parasitic capacitance. Calculating the poles and zeros, one ends up with the following expression:
This impedance has an alternating sequence of poles and zeros on the negative real axis. The bode plots of this impedance are depicted in figure 3.17. From the equations follows that the pole with the lowest frequency can be found at:
in which the magnitude is about 2.5 times higher than when the time constant is used. The corresponding -3 dB point also follows from the plot3. A closer look at the plot shows that the roll-off equals 10 dB/dec and the phase shift limits to 45°. This is result of the alternating sequence of poles and zeros.
3
It is permissible to say that the pole of equation (3.26) determines the -3 dB point as the magnitude of the next pole is a factor 9 higher and of the first zero is a factor 4 higher.
66 CHAPTER 3. LOW-VOLTAGE LOW-POWER DESIGN
When the resistor is used as a two-port V-to-I converter, the following trans- fer can be found:
Again, calculating poles and zeros the following expression is found:
The impedance has a sequence of infinite countable poles on the negative real axis and the one with the lowest frequency can be found at:
The bode plots are depicted in figure 3.18. For this situation the order of the conductance steadily increases as a function of the frequency, resulting in a phase shift not limited to 90° but steadily increasing for increasing frequency.
The third situation is in which the resistors are used as voltage divider. This voltage division cannot be derived from the impedance found for the one-port resistor by calculating a voltage division with because for both the resistors the parasitic capacitances are connected to the substrate. As one of the resistors has no terminal connected to the small-signal ground (which is also the substrate), the influence of the parasitics is different for both resistors. For calculating the transfer to the output of the voltage divider, the complete divider has to be visualized as a single distributed network with a tap as the output of the voltage divider. The transfer of this network can be written as:
3.4. LOW CURRENT 67
where is the voltage ratio. For the poles and zeros, the following expression is found:
For the poles and zeros cancel, which may be expected as the input and output are then completely in parallel. The Bode plots of this transfer are depicted in figure 3.19. Again, the roll-off increases for higher frequencies, however, less fast than for the previous case. The same holds for the phase, it is steadily increasing for higher frequencies. The difference with respect to the resistor as one port is that the zeros and poles do not alternate. The axis on which the zeros are located, compared with the axis on which the poles are, can be said to be scaled by Therefore, the phase is not limited as for the one-port situation, however it does not drop as fast as for the two-port V-to-I transfer, as the zeros have completely vanished for that transfer.
In the previous expressions the capacitances due to a contact were ignored as the size of the resistors was assumed to be relatively large. The influence of the contact parasitics can be studied by adding them to the resistor and using expressions for capacitive loaded distributed networks; see, for instance, [22]. It was also assumed that one of the terminals of the networks was grounded. If the resistive networks are floating, the influence of the parasitics will increase as was seen in section 3.4.3.3.
From previous consideration it follows that when the resistor is used as a two port, the phase and frequency behavior can be very inconvenient. When these high resistances are required, the resistor may be replaced by a MOSFET or JFET of which the channel is almost depleted. The size of these components is considerably smaller and the resulting influence of the parasitics is at relatively high frequencies [20]. Also, active structures may be used at the cost of an increased current consumption; for example, the method as depicted in figure
68 CHAPTER 3. LOW-VOLTAGE LOW-POWER DESIGN
3.20 [23]. The voltage is converted into a current by a relatively low resistance
R. The resulting current is attenuated by means of a current attenuator and
the resulting impedance equals:
where is the attenuation factor.
3.5
Low power
3.5.1 Minimization
Low-power design means both low-current design and low-voltage design. There- fore, low-power design has to do with the combined difficulties of low-voltage and low-current design. On top of that, when assuming low-power design, the orthogonality is terribly disturbed. As was seen all the quality aspects of elec- tronic circuits improve when more current is allowed to be consumed. Now one has to find answers on questions as: do I use an additional to improve the noise performance? or: do I use this power to improve the bandwidth of my circuit? To be able to answer this question, at least a weighting function must be available which relates noise performance and bandwidth to parameters hav- ing the same dimension such that they can be compared objectively. In this weighting function factors are found representing subjective aspects such as, for instance, the intelligibility of an audio signal is larger when the bandwidth is en- larged than when the noise level is reduced. Besides these subjective weighting factors, which depend on the application and consumer, also objective weighting factors are found, for instance, when the current of the input stage is increased by the noise level only reduces by 0.1 dB whereas the bandwidth increases by 50%. This type of factors is independent of the situation and can be coped with in general design methods.