APUNTES SOBRE OTROS TIPOS DE ALOJAMIENTOS: CAMPOS DE DETENCIÓN.

can be variations on this. For example, RAM memory could be interfaced to the bus, rather than directly onto the CPU bus (or both).

Figure 7.7: PC&-CPU--ISA bridges.

bridge _cardsPC1

I PCI-bus

I

bridge _cardsISA

I ISA-bus

The bridge is a chip, and although it is not obvious the figure, there are different kinds of chips for different bridges, such as between and PCI-ISA. Also, the plug-in cards themselves will have a chip. One great advantage of having a special bridge chip between buses is that they allow address translation, so that a memory or I/O address on the CPU bus will be a different address on the bus. In fact, chip is highly programmable and has its own configuration memory that, most importantly, is independent of the main memory and I/O map.

With PC systems, the standardized method of accessing the configuration memory of a chip is by two reserved I/O ports, and OCFCh. The former is used for addressing a location in configuration memory and the latter for reading/writing it.

The former, is called and the latter,

OCFCh, is called

It is important to know that these two ports can allow you to access the configuration memory on any of the interface chips

(on any adaptor card). The data that you write to is formatted as in Figure 7.8.

Figure 7.8: CONFIG_ADDRESS write format.

31 24 23 16 15 11 10 8 7 2 0

0 Device Function Register

Enable Translation Type

Bit-3 1 has to be set, otherwise the OUT instruction is treated like a normal I/O operation (not accessing the bridge chip).

is for use in systems with multiple buses, Device selects a particular adaptor card, Function selects a function that the card understands, and Register selects a register in the configuration

memory. An OUT to would be followed by

an IN or OUT to

BIOS Fortunately, a BIOS extension has been defined to give programmers a slightly less hardware-dependent mechanism for accessing the chips. One point to be careful about, however, is that not all implement the new specification fully, or, maybe, they may not have implemented the latest version of the specification (2.1 at time of writing).

Of particular interest is that version 2.1 specifies entry points for Real mode, 16-bit Protected mode, and 32-bit Protected mode. The 386 and later can operate in 16-bit Protected mode, which is what Windows 3.x applications run in, and they can also operate in 32-bit Protected mode, which is what “native” Windows NT and Windows 95 applications run in.

Reference A further source of information about this is PCI S y s t e m source Architecture (third edition) by Tom Shanley and Don Anderson,

Addison-Wesley, USA, 1995. Protected

mode BIOS

The normal BIOS that we have considered so far in this book is designed, at least originally, for an 8088 CPU, which only runs in Real mode. In a nutshell, Real mode uses the now-familiar form of addressing, which has a upper limit. The 286 and 386 are able to operate in Protected mode, which uses a different addressing mechanism and is able to address extended memory beyond (as explained in Chapter 1). One of the greatest criticisms of Windows 3.x, is its reliance on DOS and BIOS to call any of these software interrupts, the CPU must switch back into Real mode (which takes time).

It is possible to write code that can execute in either Real or 16-bit Protected mode, and BIOS has done this via

function Blh (Table 7.2). Great you can call this from a Windows 3.x application, and the CPU will not have to switch back to Real mode.

The BIOS requires an entirely different set of routines for 32-bit Protected mode.

Table 7.2: BIOS access.

Real mode. Use MT-1 Ah, AH = B lh, like any other software interrupt 16-bit Protected mode . . . ditto . . .

Virtual-86 mode . . . ditto . . .

32-bit Protected mode BIOS is scanned, for a signature, indicating presence of 32-bit BIOS, and an entry point is located. The services are accessed by a FAR CALL.

Note that, technically, it is possible, if you are writing a 32-bit application, to get it to call the Real Protected mode BIOS services, but this is starting to get too involved at this stage.

Here are some of the highlights of the architecture:

Multiple independent buses in the one PC.

32-bit data bus at up to and 64-bit

at up to

Fully synchronous with CPU bus up to

connector can be mounted alongside an

connector, so either type can occupy that physical space on the motherboard/chassis.

Processor independent Support for addressing

Support for supply

Full multi-master capability, allowing any master peer-to-peer access to any other master/target.

Postamble

I have introduced PC hardware, but so much remains to be explained. I covered the keyboard interface and expansion bus, but these are only “samplers”. What about parallel and serial, disk drive, timer, real-time clock, and other interfaces? Some of these I do touch on in later chapters, however this book will grow into something enormous if I try to cover everything.

I could cover these in the next edition though. Let me know if you really like the idea.

Choice of keyboard interface and expansion bus serve as case studies, so that you can see how the principles earlier in the chapter are applied.