Aspectos generales de la empresa 1. Historia de la EPyCT

The scaling of CMOS has result in a strong improvement in the RF performance [38].

Consequently, CMOS has become a variable option for analog RF application and RF system-on-chip.

Recently, studies of MOSFET and JL SNW FET for RF application have been reported. However, no investigation of the substrate-related components in RF regime such as the substrate resistance (Rsub) and drain-to-substrate capacitance (C_sub) of VJL SNW FETs has been reported yet. For accurate RF modeling of the realistic VJL SNW FETs, substrate-related parameters are important in the high-frequency operation regime [39–43]. In this part, we propose an extraction method of R_sub and C_sub of VJL SNW FETs and investigate the substrate effects in the high-frequency regime based on rigorous three-dimensional (3D) device simulation. An analytical extraction of parameters has been performed using Y-parameter analysis on the quasi-static (QS) small signal model, which is good enough to extract the substrate-related parameters of vertical devices accurately in the off-state regime, even though our previous work used the non-quasi-static (NQS) model in terms of the model accuracy for the intrinsic parameters [44].

A 2D cross-sectional view of VJL SNW FET in Fig. 2-5 is shown in Figs. 2-8(a). In the case of vertical SNW FETs, the substrate-related components are connected only to the drain side, while those

(a) (b)

Figure 2-8. 2D cross sectional view with small signal model: (a) VJL SNW FET and (b) conventional MOSFET

of planar MOSFETs are connected to both the source and drain sides by junction capacitances, as shown in Fig. 2-8(b). Therefore, the extraction method for Rsub and Csub has to be different from the conventional method [45].

Quasi-static small signal model

Figures 2-9(a) and 2-9(b) show the off-state QS model of the VJL SNW FET with substrate components, Csub and Rsub, for drain bottom and source bottom structures, respectively [46]. Using small signal components in Fig. 2-8(a), the equivalent circuit at the off-state can be derived as in Fig.

2-9(a). C_gde and C_gse are the extrinsic gate-to-drain and gate-to source capacitances, respectively. C_sub is the drain-substrate junction capacitance. Rs, Rd, and Rsub are the source, drain, and substrate resistances in sequence. In the case of devices with the source bottom structure, substrate-related components have negligibly small effects on RF performance as well as DC current characteristics (Fig. 2-6). This will be discussed later by using extracted parameters. The parameter extraction and

(a)

(b)

Figure 2-9. Quasi-static small signal model of VJL SWN FET at an off state (VGS=0V). (a) Drain bottom structure. (b) Source bottom structure

modeling in this work focus mainly on the VJL SNW FETs with the drain bottom structure when the bottom electrode is assigned as the drain. For the VJL SNW FETs with the drain bottom structure, the equivalent circuit at the off-state can be analyzed in terms of Y-parameters as follows:

Y = C + C + C + C , (1) Y = − C ( + C ) − C , (2) Y = − C ( + C ) − , (3)

Y = C + C + C + C + C . (4)

Model parameters R_s, R_d, R_sub, C_gde, C_gse, and C_dsub can be expressed by the following equations:

= Re(Y )

( + ), (5)

=Re(Y ) − ω

, (6)

=Re(Y ) − ω ( + )

, (7)

= −Im(Y )

, (8)

=Im(Y ) + Im(Y )

, (9)

=Im(Y ) + Im(Y )

. (10)

Figure 2-10 shows the equivalent circuit at the strong inversion region (V_GS > V_th). R_g is the effective gate resistance, which consists of the gate electrode resistance and the distributed channel resistance. This R_g in Fig. 2-10 represents only the distributed channel resistance in the on-state regime owing to the negligibly small gate electrode resistance as in our previous work with metal gate assumption [44]. Therefore, the off-state RF model in Fig. 2-9 can neglect the effective gate resistance

component since there is no distributed channel resistance owing to the absence of the inversion layer in the off-state regime [47]. The values of R_s, R_d, R_sub, C_gde, C_gse, and C_sub are extracted at the off-state. After de-embedding the off-state parameters, Rs, Rd, Rsub, Cgde, Cgse, and Csub, the equivalent circuit components at the on-state can be analyzed in terms of Y-parameters as follows:

Y = C + C + C + C , (11) Y = − C C + C − C , (12)

= − C C + C − , (13)

(a)

(b)

Figure 2-10. Quasi-static small signal model of VJL SWN FET in strong inversion region (V_GS > V_th): (a) Drain bottom structure. (b) Source bottom structure

Y = + C + ( − ) (14)

As shown in Fig. 2-10 and eq. (14), the drain conductance (gds) with delay (τgds) has been considered based on the NQS formalism since it can be significant in the linear region [48]. From eq.

(14), we can extract the delay from the imaginary part of Y22 as = 1/ × Im(− / + ).

The model parameters of R_g, C_gs, C_gd, g_m, and g_ds can be expressed by the following equations:

R = Re(Y )

Im(Y ) , (15)

C = −Im(Y )

ω , (16)

C =Im(Y ) + Im(Y )

ω , (17) g = Re(Y )| , (18) g = Re(Y )| . (19)

Using the extracted values of capacitance, resistance, and conductance, the f_t, f_max, and transport delay (τ) of the channel charge can be derived. To verify the model, the result from HSPICE circuit simulation using parameters extracted from eqs. (5)–(10) and (15)–(19) will be compared with the device simulation result.

Result and discussion The Y-parameters can be extracted by 3D device simulation and the complete quasi-static small signal parameters are extracted using the method described in the previous section. Figure 2-11 shows the small-signal parameters at the off-state and compares the result with different T_si. In Fig. 2-11(a), C_sub decreases as V_DS increases owing to the expansion of the depletion width between the drain and the substrate. Csub has also been influenced by Tsi. The w/o Sub. case has no junction capacitance between the drain and the substrate. In the case of Thin Sub., we chose the substrate thickness so that the p-type substrate is fully depleted before reaching its expected width and full depletion width can be obtained owing to low substrate doping concentrations [49]. Therefore, Csub of the Thick Sub. case is smaller than that of the Thin Sub. case. On the other hand, Cgde and Cgse are maintained as nearly constant values despite the different T_si and V_DS. In Fig. 2-11(b), R_sub decreases with the increase in VDS and the decrease in Tsi because the current path length through the

substrate is reduced by the expansion of the depletion width, while R_s and R_d are kept as constant values. Figure 2-12 shows the small signal parameters in the strong inversion region (VGS = 1 V). The capacitance, resistance, and conductance show little change with the variation of T_si in the on-state. In Fig. 2-12(a), Cgd is larger than Cgs at VDS = 0V owing to the parallel capacitance with a relatively thick oxide between the drain and gate, as shown in Fig. 2-5. When V_DS increases, C_gd decreases owing to the reduction of charge at the near drain side, whereas Cgs increases owing to the increase in charge at the near source side. At the saturation voltage, C_gd and C_gs remain constant. The total gate input capacitance (Cgg) is simply extracted by the summation of Cgd and Cgs. In Fig. 2-12(b), the trans-conductance g_m and conductance g_ds show the current drivability. Using the extracted parameters, the

0.0 0.2 0.4 0.6 0.8 1.0

Figure 2-11. Smal-signal parameter extraction results of VJL SNW FETs with Thick Sub., Thin Sub., and w/o Sub. at an off state: (a) C_gde/C_gse/C_sub and (b) R_sub/R_s/R_d

0.0 0.2 0.4 0.6 0.8 1.0

Figure 2-12. Small-signal parameter extraction results of VJL SNW FETs with Thick Sub., Thin Sub., and w/o Sub. in strong inversion region: (a) Cgg/Cgd/Cgs/Rg and (b) gm/gds

Figure 2-13. Time constant according to VDS and Tsi

transport delay (τ) of channel charge can be calculated by Cgg×VDD/Id, as shown in Fig. 2-13, which indicates that T_si has no effect on τ since the gate capacitance and channel resistance remain constant with various Tsi values [46]. To estimate the RF performance, ft and fmax are considered in Figs. 2-14 and 2-15, respectively. In 3D device simulation, f_t and f_max are extracted using the dBPoint method, which has extrapolation of experimental data to the unit gain point [50]. In Fig. 2-14, ft remains constant with various T_si values. On the other hand, f_max results in a significant difference between the devices with and without a substrate owing to substrate-related component effects, as shown in Fig. 2-15. The parameters for VJL SNW FETs at VGS = 1V are summarized in Table I. In the case of the VJL SNW FETs with the source bottom structure, the effect of R_sub and C_sub is generally very small. The impedance caused by Rs, Rsub, and Csub in Fig. 4(b) can be expressed as follows:

Figure 2-14. Cut-off frequency with variations of Tsi: (a) gate voltage VGS and (b) drain voltage VDS.

0.0 0.2 0.4 0.6 0.8 1.0

Figure 2-15. Maximum oscillation frequency with variations of Tsi: (a) gate voltage VGS and (b) drain voltage VDS

Table I. Values of the parameters for VJL SNW FETs with the drain bottom structure operating at the

Table II. Values of the ω²-terms for VJL SNW FETs with the source bottom structure.

Device JL SNW FET on Thick Sub. JL SNW FET on Thin Sub.

extracted parameters of Table I. Those for the VJL SNW FET with the source bottom structure are summarized in Table II. As shown in Table II, ω -terms are much smaller than 1. Therefore, the effect of the substrate-related parameters can be neglected in the VJL SNW FET with the source bottom structure and the effect of R_s is dominant.

To confirm the accuracy of the proposed RF models considering Rsub and Csub, the off-state and on-state Y-parameters obtained by HSPICE simulation were compared with the values obtained from 3D

device simulation, as shown in Figs. 2-16 and 2-17, respectively. In addition, the proposed model was verified at the on-state in terms of the S₂₂-parameters by HSPICE simulations. Figure 2-18 shows the comparison between the proposed RF model with Rsub and Csub and the model without Rsub and Csub. S₂₂-parameters from the proposed model with R_sub and C_sub (solid line) demonstrate well-matched results with 3D device simulation data (symbol) up to 100GHz in both Thin Sub. and Thick Sub., while the conventional model without considering R_sub and C_sub (dashed line) cannot reproduce the results of 3D device simulation (symbol) in phase space. The output characteristics of transistors in the RF region can be definitely influenced by R_sub and C_sub. Therefore, the substrate components should be considered in the realistic vertical SNW devices for the accurate modeling of the RF substrate coupling signal at the output node.

0 5 10 15 20

Vertical JLSNW FET with large Tsi Proposed model at an off-state Model without C_w & R_sub

Vertical JLSNW FET with large Tsi Proposed model at an off-state Model without C_w & R_sub

Imaginary part of Y 22 [μS]

Frequency [GHz]

(b)

Figure 2-16. Model verifications forY22-parameters by using extracted parameters and model of Fig. 2-9 at an off state:

(a) real Y22 and (b) imaginary Y22

Figure 2-17. Model verifications for Y-parameters by using extracted parameters and model of Fig. 2-10 in strong inversion region: (a) Y11 parameter, (b) Y12 parameter, (c) Y21 parameter, and (d) Y22 parameter

0 20 40 60 80 100 120 140 160 -1.0

-0.8 -0.6 -0.4 -0.2 0.00.6 0.8 1.0 1.2 1.4

L_G = 30 nm D_n = 10 nm

V_GS = 1 V ^{x 5 (VDS = 0.5 V)} x 2.5 (V_DS = 1 V) x 1.5 (V_DS = 0.5 V) x 1.0 (V_DS = 1 V) x 0.7 (V_DS = 0.5 V) x 0.8 (V_DS = 1 V) x 0.9 (V_DS = 0.5 V) Magnitude

Phase

x 1.0 (V_DS = 1 V)

Magnitude & Phase [rad] of S 22

Frequency [GHz]

S₂₂ of thick sub. S₂₂ of thin sub.

Proposed model Model w/o C_w & R_sub

Figure 2-18. Comparison between proposed RF model (solid line) and model without Csub and Rsub (dashed line), and 3D simulated (symbol) S22-parameters up to 100GHz at VGS=1.0V

Summary

A novel RF model for the VJL SNW FETs with a substrate has been proposed in consideration of the substrate-related components of R_sub and C_sub. The vertical structure with the inherent substrate effects has been investigated through analyses of model parameters with variation of bias conditions and substrate thickness. The proposed model was well matched with the Y-parameters and the S₂₂ -parameter from the 3D device simulation. The results of -parameter extraction and model verification have shown that the proposed RF model is accurate and reliable for the description of the substrate effect on the vertical structure.