Bosetaje de la Portada del Cd

The objective of the stochastic bitstream permuter circuit is to shuffle the bits of a stochastic bitstream (b0. . . bN −1) in order to eliminate correlation. Figure 8.4 shows

the design of the Spintronic Stochastic Bitstream Permuter (Spin-SBP). It consists

C

C

I

_I

T

_T

_R

SE

S

C

C

C

C

Fig. 8.4.: Spintronic Stochastic Bitstream Permuter

magnet domains, a Spin-RNG with peripheral circuitry, and NMOS transistors. The input nanomagnet is connected to the two end domains of the nanowire (domains D1 and D5) and the output nanomagnet is connected to domain D3 using spin channels. The domains D1 and D5 are also connected to the drain terminal of the TRS and TLS transistors respectively. As shown in Figure 8.4, the gate terminal of the

transistors are connected to the random bit output R, after feeding it through a low- overhead control logic comprising of 2 control inputs viz. Set(S), Set Enable(SE). This arrangement facilitates the domains in the nanowire to be partially shifted in either direction based on the random bit output. For example, when the random bit output is 0 (R = 0) and the control inputs are set to appropriate values (SE = 0, S = X,C2 = 1), the transistor TRS is turned ON and a current (ISR) flows from the

middle domain (D3) of the nanowire through the domains to the left of it viz. D1 and D2. Due to the phenomenon of domain wall motion, the bits stored in the domains D1 and D2 shift to the right i.e. the magnetic orientation of D2 is shifted to D3, while that of D1 is propagated to D2. Similarly, when the random bit is 1 (R = 1, SE = 0, S = X, C2 = 1), the domains D4 and D5 are left shifted due to the flow of

current ISL in the right half of the nanowire. Thus, based on the random bit output,

the orientation of either D2 or D4 can be propagated to D3, which is subsequently read at the output of the Spin-SBP by asserting C3.

The operation of the Spin-SBP is explained below. The Spin-SBP takes one bit of the stochastic bitstream as its input and produces one bit of the permuted bitstream at the output in each cycle of operation. First, each input bit to the Spin-SBP is latched to both the ends of the DWM nanowire (domains D1 and D5) through the spin channels by connecting C1 to VDD. The following control sequence is carried out

in the first two execution steps. In the first execution step, after latching the first bit to end domains (D1 and D5), the control inputs C2, S and SE are asserted and

therefore TLS is turned ON irrespective of the random bit output. This results in

a left shift of the domains in the nanowire and the first stochastic bit input (b0) is

input (b1) is first stored in the end domains and then shifted to domain D2 by setting

the control inputs to C2 = 1, S = 0 and SE = 1. From the third step onwards, we

latch the input bit to domains D1 and D5, and then set C2 = 1, S = 0, and SE = 0.

Therefore, the random bit output (R) determines the direction in which the bits in the nanowire is shifted. For example, if R = 0 in the third cycle, the stochastic input bit b1 is shifted to domain D3, which is subsequently produced as the first shuffled

bit output. Consequently, because of the right shift, the third stochastic bit latched in the domain D1 replenishes D2. Therefore, the next shuffled bit output could be either b0 or b2 depending on the random bit output. This process is repeated until

N − 2 shuffled output bits are produced by the Spin-SBP. Then the control sequence described above for the first two cycles of operation is repeated to read out the last two output bits.

Head

Head

Tail

Tail

Left Deck

Right Deck

Fig. 8.5.: Logical view of Spintronic Stochastic Bitstream Permuter

This randomization process can be thought analogous to shuffling a deck of cards using a toss of coin as shown in Figure 8.5. If the coin toss results in a ‘Head’, then

the card at the top of the deck is placed on the top of the left deck and the card at the bottom of the left deck is moved to the bottom of output deck. Similarly, if the coin toss results in a ‘Tail’, the card at the top of the input deck is placed on the top of the right deck and that at its bottom is moved to the bottom of output deck. This process is repeated until all the cards in the input deck is moved to the output deck. The proposed Spin-SBP has a number of advantages. Since, each bit (bi) of

the stochastic bitstream can occupy a position between i − 1 and N − 1 in the shuffled bitstream, the Spin-SBP can produce N(N!) permutations of the possible NN _{permutations of the input bitstream. The number of the possible permutation}

outcomes can be further improved by having domain wall tapes of larger length. In contrast, a LFSR-based implementation can produce only N different shuffled bitstreams based on the value of its seed. Another key benefit of the proposed SBP is that it is extremely compact and is based on highly energy efficient domain wall motion [21]. In comparison, a conventional CMOS design of a permuter involves a combination of an SBC and an SNG, leading to large area and energy overheads. Further, since the proposed SBP does not involve stochastic-to-binary conversion, it does not require all the bits of the stochastic bitstream to be available before generating the first output bit, which leads to improvement in performance.