C ONCLUSIONES P ARCIALES

In order to detect data in a spread spectrum transmission, the signal first has to be despread, that is, the spreading code must be removed. To do this, the locally produced spreading code must be phase aligned with the code of the incoming signal. In Figure 3.9, the correlator receives the downconverted baseband spreading code and the locally generated code. During normal communication, it may not be important to know the time when the local code generator begins its sequence, but this time must be known for distance measurement. Figure 3.10 shows the output of the correlator as the local code generator slides the phase of the replica code in relation to the incoming signal. In this figure the phase changes by a discrete value of 1/10 of a chip per sequence period. Figure 3.10 differs from Figure 3.5 in which phase changes are continuous. Output is maximum when phases match, and decreases stepwise linearly to minimum when the phases differ by plus or minus one bit. As the phases continue to differ by larger and larger amounts, the output of the correlator remains low. The actual form of the correlator output

Time Time

−0.20 0 0.2 0.4 0.6 0.8

10 20 30 40 50 60

1.0

Figure 3.10 Correlator output with a code phase changes of one-tenth chip for each correlator integrating period.

depends on the autocorrelation properties of the particular code sequence. During acquisition, the local phase is changed by one bit or a fraction of a bit, then the correlator output is checked in the decision block for a level that exceeds a given threshold. The chip clocks of transmitter and receiver are not synchronized at this stage, and chip boundaries can differ, preventing a perfect lineup of local replica and received chips. The threshold value that is set to detect the best correlation point must take into account the worst-case skew between the transmitter and receiver clocks. The correlator presents a new output to the threshold comparator at the end of every code sequence period. If the threshold is not exceeded, the local code generator phase is changed by one chip or a fraction of a chip. When threshold is reached, the local code generator phase is left at its present value. Local code and received code are then in line to within one half of the phase change that was forced on the local code generator after each sequence period. Maximum threshold values, covering worst-case chip boundary skew between transmit and receive clocks for phase shift trials of one bit and one half bit are shown in Figure 3.11 for an m-sequence spreading code. These thresholds are

y₁= (1/2)(1 − 1/N) (3.6)

y₂= (1/4)(3 − 1/N) (3.7)

where y₁ is the threshold for 1-chip phase shifting and y₂ is the threshold for 1/2-chip phase shifting. When whole chip shifting is used, the lowest output level, y₁, occurs when the phase difference between received and replica sequences is a whole number of chips plus 1/2 chip. Similarly, half-chip shifting can achieve a maximum correlator output level of y₂ when the phase difference between the sequences is 1/4 chip.

In a real system, noise, interference, and fading affect the correlator output.

Because of these effects, the correlator output could be below the theoretical

worst-Figure 3.11 Correlator output threshold levels for one bit and one-half bit incremental shifts.

case output, and the decision circuit will not detect that code synchronization is within the coarse range and will continue phase shifting. This is called a miss. On the other hand, the correlator output may exceed the threshold at the wrong time, causing the coarse search to stop when synchronization has not been achieved.

This is a false alarm. Therefore, the threshold values y₁or y₂should be increased or decreased according to whether a miss or a false alarm is most detrimental to system operation. A 1/2-chip increment gives a higher output on correlation and a better signal to noise ratio that will decrease the probability of a miss and of a false alarm. However, the average acquisition time is greater when a fractional increment is used, as shown below.

Figure 3.12 shows two ways of representing implementation of the correlator block in Figure 3.9. The integration form of correlation given by (3.4) is shown in Figure 3.12(a). The sample and hold element presents the results of the integration of the product of the two input sequence streams to the output where it is held for the duration of a sequence. At the end of a sequence, the integrator is reset and the signal product is integrated again. Another way of showing the accumulate and dump operation of the correlation is illustrated in Figure 3.12(b). It consists of a multiplier that receives the two bipolar sequences, a delay line of N− 1 cells (can be clocked flip-flops), each with a delay of chip period T_c, a summing device, lowpass filter, and sample and hold function. The circuit performs the correlation according to the discrete formulation for the continuous correlation function in (3.3):

Figure 3.12 Correlator implementation. (a) Continuous configuration, and (b) discrete configuration.

where k is the phase difference in number of chips, j is the position of the chip, x_j is a bipolar chip value, and K is a scaling factor. The LPF in Figure 3.13 is typically an FIR digital filter with 6-dB cutoff frequency 1/2T_c(T_cis the chip period). The sample and hold control line outputs the correlation result once per sequence period, NT_c.

The threshold comparator block in Figure 3.9 makes a decision once every sequence period T= NTc. If the correlator output is below the threshold, the code generator phase is increased (or decreased, depending on system implementation) by one chip, or a fraction of a chip if so designed. Otherwise, when the output is at or above the threshold, acquisition has been obtained, and the system starts the tracking mode where phase is fine-adjusted for closer correlation and synchroniza-tion is maintained during data demodulasynchroniza-tion.

In case the received code happens to be within the coarse acquisition phase difference from the replica code, tracking may commence immediately after one complete sequence period from the beginning of the acquisition mode. However, if the incoming sequence lags the replica by n chips, then n sequences will have to be tested until coarse correlation is detected (assuming one chip phase decrement each time). If 1/2-chip increments are used, the maximum duration of acquisition mode will be 2n sequences. Misses or false alarms will cause additional delays.

Data demodulation in the DSSS system cannot commence until coarse acquisition has been obtained, so the system message protocol has to take into account the maximum coarse acquisition time. The message may have a preamble, during which the chipping sequence is sent without data. If this preamble must be kept short, to increase data throughput for example, parallel correlators may be used to reduce the time needed to check all phase difference positions. An arrangement where N correlators are used is shown in Figure 3.13. Since all possible phase shifts are tried at the same time (using 1-chip shifts), a decision on which of the N phase-shifted replicas of the code should be selected is made at the end of only one sequence by comparing the outputs of the individual correlators and selecting the maximum. The different shifted sequences are taken from taps on the local code

x t( ) x _c) x t N( (− − t1)c)

Output Correlator

Correlator Correlator Down

converter

Local code generator

Decision

(t t−

Figure 3.13 Parallel correlators.

generator—generally a shift register. All N shifts do not have to be used, and the number of correlators will divide the maximum number of sequences needed accordingly.

3.2.1.1 Code Rate Control

The circuit of Figure 3.9 is based on the sliding correlator concept where the phase of the locally generated code replica is varied by a control signal from a threshold comparator until its phase approaches that of the received signal code sequence by closer than one chip. The replica code is created in a LFSR (using the example of m-sequences), of which Figure 3.6 is an example, and the code rate is governed by the rate of the shift register clock. The clock rate can be sped up by inserting an additional pulse into the clock input pulse stream once during every sequence period, or slowed down by inhibiting one pulse during that period. Another way of controlling the clock rate is shown in Figure 3.14. The clock pulses for the local code shift register are generated in a pulse generator driven by a VCO, and divided by the number of pulses in the code sequence, N, to create a control signal. This control is used for the correlator sample and hold (Figure 3.12). It also triggers a second pulse generator in Figure 3.14, which outputs a pulse of width⌬t. This pulse switches a voltage pulse V_⌬tinto the VCO frequency control line causing a brief frequency change of the VCO output. The result is to cause the phase of the replica sequence to jump by plus or minus 1 chip during a sequence period. The relationship between frequency and phase is

⌬␾ = 2␲ ⭈ 冕^⌬t

0

⌬f ⭈ dt (3.9)

where⌬f is the incremental VFO frequency during a period of ⌬t. In this case, the phase difference⌬␸is created by an abrupt VFO frequency jump±⌬f during an interval⌬t, so from (3.9) the phase change in radians is:

÷N

∆t

V_∆f

VCO Pulse

generator

Pulse generator

Clock

Control Frequency

control

Figure 3.14 Code rate control by pulsing VCO control line.

⌬␸= 2␲⌬f⌬t (3.10)

The required phase is one chip, or 2␲ radians in terms of the chip rate, so:

2␲= 2␲⌬f⌬t (3.11)

⌬f = 1/⌬t

⌬f can be either positive or negative for phase lead or lag. The value of V_⌬f in Figure 3.14 is determined by the VCO control sensitivity, k_v, in Hz/volt, so

V_⌬f= (1/k_v)⌬f (3.12)

In this example,⌬␸ is a whole chip, but phase increments of a fraction of a chip, for better code synchronization during acquisition, can be obtained by choosing ⌬␸< 2␲^. ⌬t is generally chosen to be one chip period, T_c, although it can be any time span up to the sequence period, T_s. When ⌬t = Ts, the replica code sequence slides smoothly against the received sequence during the test of correlation.

The VCO block in Figure 3.9 can be implemented by a frequency synthesizer referenced to the system clock. In this case the designated VCO control input would digitally switch the synthesizer divider to accurately change the clock frequency by the desired amount. Another implementation based on a numerically controlled oscillator (NCO) is described below in Section 3.3.