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We now have a design, and have defined the pattern in the chosen resist. The next step is to transfer the pattern into the hard mask (if used), and etch into the sample. We can again divide this section into heterostructure and silicon based processes, as these are significantly different. As with previous sections, the intent here is not the detailed discussion of chemical processes, but instead

to explain the parts where significant development work has been done, and where my processes provide substantial benefits.

3.5.1

Heterostructure devices

For this project, two significant heterostructure devices are involved, namely a PhC y-splitter et al. (chapter 6) on AlGaAs, and a surface grating coupler on InP (chapter 4). The techniques used in etching these two devices are fairly similar. In both cases, we use PMMA as the resist, and transfer into a hard mask using RIE (Reactive Ion Etching) in a fluorine chemistry, and then etch the pattern into the heterostructure using CAIBE (Chemically assisted ion beam etching) in chlorine chemistry. For the AlGaAs patterns our concern is to maximise the etch depth, whereas achieving exactly the target etch depth is important in the InP case.

The pattern transfer step is the most standardised of all the fabrication processes used here; and poor results are usually due to external effects. There are two limits to this, firstly that the RIE machine is used with other etch gases which can cause contamination that affects the etch recipes, and secondly mask thickness. Although the standard recipe is consistent, the selectivity is 1:1 at best. Using a thicker hard mask to get a greater CAIBE etch depth requires a thicker resist, and this lowers resolution in the pattern. The etching is done in CHF3 gas, taking about 15 minutes for 300nm of silica hard mask.

CAIBE is a more variable process, and requires continuous optimisation to achieve the desired results. This is particularly true for AlGaAs heterostruc- ture, as the layers with high aluminium concentration are sometimes found to act as etch stops for recipes optimised for pure GaAs. Usually, one tries to achieve the maximum possible etch depth with vertically edged holes, and our machine is very successful at this [34, 35, 36]. To do this, one controls the

sample temperature, the velocity and number of argon ions for the mechanical etching component (via beam voltage and current)and the relative number of argon and chlorine ions available for etching. There are several regimes that can be optimised to give good results, some examples of which are shown in figures 3.8 and 3.9. For a detailed discussion of this, refer to M.V. Kotlyar’s thesis [37], and L. O’Faolain’s thesis [38].

Figure 3.8: Good quality AlGaAs etching in CAIBE for the Y-splitter devices in

chapter 6. The etch depth and sidewall verticality are the critical parameters to optimise.

3.5.2

Silicon etching

The silicon etching here is primarily SOI rather than silicon wafers, and the typical SOI is a 220nm Si guiding layer on 1µm buried oxide (BOX), over a silicon substrate. For PhC devices, Bogaerts et al. [28] have shown that simply etching holes into the top silicon layer, and neglecting the BOX, gives the best results consistent with the additional difficulty in transferring the pattern into the oxide. One can also make a silicon membrane, by using a wet HF process to undercut the PhC device. Although there are arguments for and against this, it has not been done in this project.

Figure 3.9: Shallow InP etching in CAIBE, for an attempt to realise the 1D gratings in chapter 4. The etch depth in the figure is close to 95nm. In this case, we have to accurately hit a target etch depth while maintaining good etch-floor roughness and sidewall verticality. This is the best result I could achieve, which manages two of the three requirements. However, CAIBE is not well suited to shallow etching, and so we have changed to an ICP system for these devices. This is discussed further in chapter 4.

and SF6 gases. The SF6 gas etches the silicon, but it does so in an isotropic

fashion which is not very conducive to PhC holes with vertical sidewalls. CHF3

is added to provide directionality; it reacts with the product gases to form a polymerisation layer, and so prevents etching outwards.

The challenge with silicon etching in this kind of process is in the masking. In the pattern transfer process, we can use 200nm of PMMA and etch for 15 minutes, which indicates that PMMA resists CHF3 gas well [39]. Using a

similar etch pressure but replacing half of the CHF3 flow with SF6, we find

that the 200nm mask lasts less than a minute, and the silicon is only etched to around 100nm. All values given here are very approximate, as it depends strongly on hole size, and the accuracy of depth measurement is limited - the SiO2BOX layer is an insulator, so charging effects in the SEM reduce precision.

By using over 600nm of PMMA, an etch depth of 200nm is achievable for holes of diameter greater than 250nm. Using this much resist makes it difficult to

make small holes, and difficult to accurately control hole size. Clearly, an alternative solution is desired.

Although several attempts were made to alter the etch chemistry, none were successful. Instead, the resist type was changed, from PMMA to ZEP, following the practice of several other groups fabricating PhCs in Si. This improves the situation somewhat, although the result still is not perfect. We can reliably etch holes of diameter greater than 200nm all the way through the top Si layer. For a typical target r/a of 0.27, this gives a minimum period of 370nm, which is acceptable for devices designed to operate at 1550nm, but only just. Further increases in resist thickness are not desirable, so work is in progress on further improving the process. An example of etching is shown in figure 3.10.

Figure 3.10: RIE etching of PhCs in SOI, using a mixture of SF6 and CHF3

gasses. The aim is to etch through the 220nm top Si layer only, while maintaining sidewall verticality.

With SOI fabrication, there is one other etch process of critical importance, namely substrate removal. This is necessary to achieve good quality cleaved facets, which are often the limiting factor in characterising SOI devices. This can be done either mechanically using an alumina paste, or chemically in a solution of KOH; both require a huge degree of care and attention in relation to the perceived simplicity of the process! However, the yield of the process

has improved with the experience of the group, by learning which details must be taken care of3

, and now only a few samples are lost.