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CAMBIOS EN LA ARQUITECTURA VENTRICULAR
times to acquire data of 15,000 pixels per frame (at a resolution of 150x100 pixels). The source chosen for MCU clock is a 6 MHz crystal module and is programmed in such a way that this frequency is multiplied by 16 via an internal phase-locked loop to give an operating frequency of 96 MHz which is subsequently divided by 4 to allow the device to run at 24 Mips, yielding single instruction execution time of 42 ns. Fast clock sources require special RF considerations. For example, a 48MHz external clock could be multiplied by 2 internally by the on chip PLL to give the same results. The problem with this approach is that more careful considerations for RF and board layout are required to accommodate such a high frequency clock. So the best solution is to use a combination of a low external clock source and a high PLL multiple to achieve the desired result. The maximum PLL multiple on the device is x16. Although the MCU internal frequency runs at 96MHz it is designed with these considerations in mind to have little effect externally.
Figure 2.3 : MCU reset and ICSP schematic [2].
Figure 2.3 shows the reset pin and In Circuit Serial Programming (ICSP) circuit implemented in the system. The ICSP becomes necessary because the MCU is a surface mount device which is soldered directly into the system board and therefore is programmed in circuit as opposed to being removed
DATA are isolated from the system by the means of two 10 K
resistors. VDD has a decoupling capacitor to ground and the zener diode gives protection from spurious signals by clamping them at 5.6 V. R1 and C1 form the RC reset network to the MCLR pin with D1 giving protection at point x should it rise 0.6 V above the 5 V supply. Figure 2.3 shows how this circuitry was integrated into the system.The dsPIC30F6014 has 84 easily configurable I/O pins arranged in various bit widths in the format of PORTA-PORTG. The I/O pins can have multiple functions, e.g. can be used for A/D input, PWM output, etc. This application of the MCU requires that all I/O used should be configured for straightforward digital I/O. Figure 2.4 shows how the I/O pins were configured for use within the system. The two sixteen bit ports available were selected for both 8 bit data busses and the 16 bit address bus. This was to speed up data transfer and addressing. The remaining allocation of the I/O pins were chosen with PCB design in mind allowing for shorter tracks and simplicity of board layout.
2.4 Graphic Controller
Very early on in the project it became apparent that direct control of the LCD display by the microprocessor would require a huge overhead in processing power, and would therefore not be practical. This is due to the non-static nature of the LCD module which continually needs to have each pixel point “refreshed”, regardless of if a change at a particular pixel point is required – somewhat analogous to dynamic memory. A dedicated LCD matrix controller was therefore procured which would enable much simplified interfacing of the microcontroller to the LCD display. The chosen device used for graphic control in the system was the S1D13706 manufactured by Epson research and development [3]. The main attraction to the device is its ability to produce 64 shades of grey on various panel types i.e. STN, TFT, D-TFT and HR-TFT. It’s on chip 80 Kbytes of video random access memory (RAM) make it adequate as a maximum of 76 Kbyte of RAM is required for the 320x240 panels used. The S1D13706 requires hardware and software configuration in order for it to be used successfully in the system. This section will cover hardware configuration and how the graphic controller was implemented into this system.
IC1
Figure 2.4: MCU clock circuit , Pin I/O configuration and ICSP/Reset circuitry
2.4.1 S1D13706 Bus Configuration
The device can be used with a host of microprocessors or microcontrollers and is engineered for ease of use with fast, powerful devices such as Motorola 32-bit 68030, Motorola 16-bit 68000, Motorola Dragonball, Hitachi SH3 and SH4 and many others. These devices are optimised for use in more
configured for generic bus interfacing to a microcontroller which is the method used within this system, in either 8 or 16 bit data transfer mode. The configuration chosen was 8 bit data transfer. Addressing of the graphic controller was configured by means of a 17 bit data interface to the MCU. The generic bus used is shown in figure 2.5. Bus start (BS#) and Read/Write (RD/WR#) are not used in the generic interface bus mapping and are tied to HIO/VDD. The memory mapping of the device is separated into two 128 Kbyte blocks, one of which is occupied by the internal registers and the other block is occupied by the 80 Kbyte display buffer. Pulsing M/R# high selects the display buffer memory and a low selects the register memory. Address bus 16:0 allows addressing to each of the 128 Kbyte of memory with the least significant bit of the bus selecting either the low byte or high byte of data, A0 low onto BHE# enables the high byte and a logic high enables the low byte. This is how 8 bit interfacing becomes possible. The RD# and WR# pins instruct whether data is read from the device or written to it. Reset to the graphic controller is controlled by an I/O pin enabling a software controlled reset.