13.4.1 MCUCR – MCU Control Register
• Bit 4 – PUD: Pull-up Disable
When this bit is written to one, the I/O ports pull-up resistors are disabled even if the DDxn and PORTxn Registers are configured to enable the pull-up resistor ({DDxn, PORTxn} = 0b01). See
“Configuring the Pin” on page 71 for more details about this feature.
13.4.2 PORTA – Port A Data Register
13.4.3 DDRA – Port A Data Direction Register
13.4.4 PINA – Port A Input Pins Address
13.4.5 PORTB – Port B Data Register
13.4.6 DDRB – Port B Data Direction Register
13.4.7 PINB – Port B Input Pins Address
Bit 7 6 5 4 3 2 1 0
0x35 (0x55) JTD – – PUD – – IVSEL IVCE MCUCR
Read/Write R/W R R R/W R R R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
0x02 (0x22) PORTA7 PORTA6 PORTA5 PORTA4 PORTA3 PORTA2 PORTA1 PORTA0 PORTA
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
0x01 (0x21) DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 DDRA
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
0x00 (0x20) PINA7 PINA6 PINA5 PINA4 PINA3 PINA2 PINA1 PINA0 PINA
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value N/A N/A N/A N/A N/A N/A N/A N/A
Bit 7 6 5 4 3 2 1 0
0x05 (0x25) PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 PORTB
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 0x04 (0x24) DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 DDRB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0
0x03 (0x23) PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 PINB
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
13.4.8 PORTC – Port C Data Register
13.4.9 DDRC – Port C Data Direction Register
13.4.10 PINC– Port C Input Pins Address
13.4.11 PORTD – Port D Data Register
13.4.12 DDRD – Port D Data Direction Register
13.4.13 PIND – Port D Input Pins Address
13.4.14 PORTE – Port E Data Register
13.4.15 DDRE – Port E Data Direction Register
Bit 7 6 5 4 3 2 1 0
0x08 (0x28) PORTC7 PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 PORTC
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 0x07 (0x27) DDC7 DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 DDRC Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0
0x06 (0x26) PINC7 PINC6 PINC5 PINC4 PINC3 PINC2 PINC1 PINC0 PINC
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value N/A N/A N/A N/A N/A N/A N/A N/A
Bit 7 6 5 4 3 2 1 0
0x0B (0x2B) PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 PORTD
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 0x0A (0x2A) DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 DDRD Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0
0x09 (0x29) PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 PIND
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value N/A N/A N/A N/A N/A N/A N/A N/A
Bit 7 6 5 4 3 2 1 0
0x0E (0x2E) PORTE7 PORTE6 PORTE5 PORTE4 PORTE3 PORTE2 PORTE1 PORTE0 PORTE
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
0x0D (0x2D) DDE7 DDE6 DDE5 DDE4 DDE3 DDE2 DDE1 DDE0 DDRE
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
13.4.16 PINE – Port E Input Pins Address
13.4.17 PORTF – Port F Data Register
13.4.18 DDRF – Port F Data Direction Register
13.4.19 PINF – Port F Input Pins Address
13.4.20 PORTG – Port G Data Register
13.4.21 DDRG – Port G Data Direction Register
13.4.22 PING – Port G Input Pins Address
13.4.23 PORTH – Port H Data Register
Bit 7 6 5 4 3 2 1 0
0x0C (0x2C) PINE7 PINE6 PINE5 PINE4 PINE3 PINE2 PINE1 PINE0 PINE
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value N/A N/A N/A N/A N/A N/A N/A N/A
Bit 7 6 5 4 3 2 1 0
0x11 (0x31) PORTF7 PORTF6 PORTF5 PORTF4 PORTF3 PORTF2 PORTF1 PORTF0 PORTF
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 0x10 (0x30) DDF7 DDF6 DDF5 DDF4 DDF3 DDF2 DDF1 DDF0 DDRF Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0
0x0F (0x2F) PINF7 PINF6 PINF5 PINF4 PINF3 PINF2 PINF1 PINF0 PINF
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value N/A N/A N/A N/A N/A N/A N/A N/A
Bit 7 6 5 4 3 2 1 0
0x14 (0x34) – – PORTG5 PORTG4 PORTG3 PORTG2 PORTG1 PORTG0 PORTG
Read/Write R R R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 0x13 (0x33) – – DDG5 DDG4 DDG3 DDG2 DDG1 DDG0 DDRG Read/Write R R R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0
0x12 (0x32) – – PING5 PING4 PING3 PING2 PING1 PING0 PING
Read/Write R R R/W R/W R/W R/W R/W R/W
Initial Value 0 0 N/A N/A N/A N/A N/A N/A
Bit 7 6 5 4 3 2 1 0
(0x102) PORTH7 PORTH6 PORTH5 PORTH4 PORTH3 PORTH2 PORTH1 PORTH0 PORTH
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
13.4.24 DDRH – Port H Data Direction Register
13.4.25 PINH – Port H Input Pins Address
13.4.26 PORTJ – Port J Data Register
13.4.27 DDRJ – Port J Data Direction Register
13.4.28 PINJ – Port J Input Pins Address
13.4.29 PORTK – Port K Data Register
13.4.30 DDRK – Port K Data Direction Register
13.4.31 PINK – Port K Input Pins Address
Bit 7 6 5 4 3 2 1 0
(0x101) DDH7 DDH6 DDH5 DDH4 DDH3 DDH2 DDH1 DDH0 DDRH
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
(0x100) PINH5 PINH5 PINH5 PINH4 PINH3 PINGH PINH1 PINH0 PINH
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value N/A N/A N/A N/A N/A N/A N/A N/A
Bit 7 6 5 4 3 2 1 0
(0x105) PORTJ7 PORTJ6 PORTJ5 PORTJ4 PORTJ3 PORTJ2 PORTJ1 PORTJ0 PORTJ
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 (0x104) DDJ7 DDJ6 DDJ5 DDJ4 DDJ3 DDJ2 DDJ1 DDJ0 DDRJ Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0
(0x103) PINJ5 PINJ5 PINJ5 PINJ4 PINJ3 PINGJ PINJ1 PINJ0 PINJ
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value N/A N/A N/A N/A N/A N/A N/A N/A
Bit 7 6 5 4 3 2 1 0
(0x108) PORTK7 PORTK6 PORTK5 PORTK4 PORTK3 PORTK2 PORTK1 PORTK0 PORTK
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 (0x107) DDK7 DDK6 DDK5 DDK4 DDK3 DDK2 DDK1 DDK0 DDRK Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0
(0x106) PINK5 PINK5 PINK5 PINK4 PINK3 PINGK PINK1 PINK0 PINK
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
13.4.32 PORTL – Port L Data Register
13.4.33 DDRL – Port L Data Direction Register
13.4.34 PINL – Port L Input Pins Address
Bit 7 6 5 4 3 2 1 0
(0x10B) PORTL7 PORTL6 PORTL5 PORTL4 PORTL3 PORTL2 PORTL1 PORTL0 PORTL
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 (0x10A) DDL7 DDL6 DDL5 DDL4 DDL3 DDL2 DDL1 DDL0 DDRL Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0
(0x109) PINL5 PINL5 PINL5 PINL4 PINL3 PINGL PINL1 PINL0 PINL
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W