VII. RESULTADOS DE LA INVESTIGACIÓN
4. Categoría general: garantizar la convivencia y participación de la comunidad escolar
5.1 INTRODUCTION
In this chapter, and in the next chapter, we will take a comprehensive look at various building blocks used to design more complex combinational circuits. Generally, digital circuits are divided into two categories:
1. Combinational logic circuit, and 2. Sequential logic circuit.
Combinational Logic Circuits
In combinational logic circuits, output at any instant of time depends only on the inputs present at that instant of time. The logic gate is the most basic building block of combinational logic. Combinational logic circuits do not have memory elements (storage device). It can be designed using gates or available ICs.
Adder, subtractor, ALU comparators, parity generator and checker, multiplexer, demultiplexer, encoder, and code converters are the examples of combinational logic circuits.
Sequential Logic Circuits
The other category of logic circuits, called sequential logic circuits, in which the output depends upon not only the present but also the past state of inputs. Sequential circuits comprise both logic gates and memory elements such as flip-flops. Basic building blocks of sequential logic circuits are described in detail in Chapters 10 and 11.
5.2 DESIGN PROCEDURE FOR COMBINATION LOGIC CIRCUITS
The block diagram of a combinational circuit is shown in Figure 5.2.1. It has n input variables and m output variables or simply outputs. Since the number of input variables is n, there are 2n possible combinations of bits at the input. Each output can be expressed in terms of input variables by a Boolean expression.
Figure 5.2.1: Block diagram of a combinational circuit
EXAMPLE OF SEQUENTIAL CIRCUIT Flip-flops, counters and registers are the examples of sequential logic circuits.
READER NOTE
Also, each of the input variables may be available as only the normal input on the input line. In that case, the complemented input, if desired, can be generated by using an inverter.
Chapter 5 Combinational Arithmetic Circuits Page 291
Inputs Output
A B C D Y
1 1 1 0 0
1 1 1 1 1
Step 2: Now using the truth table, we represent the given function on
K-map as shown. To obtain a minimized POS expression, we make groupus of adjacent 1’s. Here, no grouping is possible, we have 8 isolated minterms on K-map.
POS expression for the logic
Y =A B C D+ABC D+ABC D+AB C D+A BCD
+ABCD+ABCD+ABCD
C D A B AB C D AB AB CD A B AB = _ + i+ _ + i+ _ + i +CD AB_ +ABi A9B C D CD C D CD A5B =_ i_ + i+_ + i_ i A9B C9D A5B C5D =_ i_ i+_ i_ i
Step 3: Now, we implement the above function using Ex-OR and Ex-
NOR gates as shown in the logic diagram.
5.3 ARITHMETIC CIRCUITS
Now, we will study those combinational logic building blocks that can be used to perform addition and subtraction operations on binary numbers. Addition and subtraction are the two most commonly used arithmetic operations, since the other two, namely multiplication and division, are respectively the processes of repeated addition and repeated subtraction.
We start with the basic building blocks that form the basis of all hardware used to perform the arithmetic operations on binary
Page 292 Combinational Arithmetic Circuits Chapter 5
Digital Electronics by Ashish Murolia and RK Kanodia For More Details visit www.nodia.co.in numbers. These include half-adder, full-adder, half-subtractor, full
subtractor etc.
5.4 ADDERS
The most basic arithmetic operation is the addition of two binary digits. Only four cases can occur in adding two binary bits. There are,
0+ =0 0, 0+ =1 1, 1+ =0 0 and 1+ =1 10
The first three operations produce a sum whose length is one digit, but in the fourth case, the binary sum consists of two digits. The higher significant bit of this result is called a carry, which may get added to the next higher bit addition.
A combinational circuit that performs the addition of two 1-bit numbers is called as half-adder, and the logic circuit that adds three 1-bit numbers is called as full-adder.
5.4.1 Half-Adder
The logic circuit that performs the addition of two 1-bit numbers is called as half-adder. It is the basic building block for addition of two single bit numbers. This circuit has two outputs namely Carry _ iC
and Sum _ iS . Figure 5.4.1 shows the block diagram of half adder. The truth table of half-adder is given in Table 5.4.1, where A and B are the inputs, and sum and carry are the outputs.
Table 5.4.1 Truth table for half-adder
Inputs Outputs A B Sum _ iS Carry _ iC 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1
K-map Simplification for Carry and Sum
Using the table above, we construct K-maps for carry and sum outputs of half-adder. Boolean expressions for the sum ^ hS and carry
C
^ h output may be obtained from the K-maps as given below.
Sum, S =AB+AB =^A5Bh (5.4.1)
Figure 5.4.1: Block diagram of a half- adder
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Half-Adder Using NOR Gates
For implementation of half-adder using NOR gates only, we write the expression of carry and sum in the form of NOR logic as shown below. Sum, S=AB+AB =AB+AA+AB+BB A A B B A B = _ + i+ _ + i A B A B =_ + i_ + i A B A B =_ + i_ + i A B A B = + + + Carry, C =AB=AB=A+B
The above expressions of sum and carry can be implemented using NOR gates as shown in Figure 5.4.5 below.
EXAMPLE 5.2
For the half-adder circuit of Figure E5.2(a), the inputs applied at A
and B are as shown in Figure E5.2(b). Plot the corresponding SUM and CARRY outputs for the half-adder.
Figure 5.4.4: Logic diagram of half-adder using only 2-input NAND gates
Figure 5.4.5: Logic diagram of half-adder using only 2-input NOR gates
Chapter 5 Combinational Arithmetic Circuits Page 295
SOLUTION :
The SUM and CARRY waveforms can be plotted by keeping in mind the truth table of the half-adder. For a half-adder, we know that 0+0
gives a ‘0’ as the SUM output and a ‘0’ as the CARRY. 0+1 or 1+0
gives ‘1’ as the SUM output and ‘0’ as the CARRY. 1+1 produces a ‘0’ as the SUM output and ‘1’ as the CARRY. The output waveforms are as shown in Figure .
5.4.2 Full-Adder
A full adder circuit is an arithmetic circuit block that can be used to add three bits to produce a sum and a carry output. Let us consider A
and B as two 1-bit inputs. Cin is a carry generated from the previous order bit additions; S(sum) and Cout (carry) are the outputs of the full-adder.
The block diagram and the truth table of a full-adder are shown in Figure 5.4.6 and Table 5.4.2 respectively.
Table 5.4.2 Truth Table of Full-Adder
Inputs Outputs
A B Cin Sum _ iS Carry Cout
0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1
K-map Simplification For Carry and Sum
We draw K-maps for sum and carry output with the help of truth Table 5.4.2. Simplified Boolean expressions for the sum ^ hS and carry
Cout
^ h output may be obtained from the K-maps as given below. Sum, S =A BCin+ABCin+ABCin+AB Cin
( ) ( ) C A Bin AB Cin AB AB = + + + ( ) ( ) C Ain 9B Cin A5B = + ( ) ( ) C Ain 5B Cin A5B = + S =Cin5A5B (5.4.3) Carry, Cout =AB+ACin+BCin (5.4.4) Logic Diagram
Considering equation (5.4.3) and (5.4.4) we can realize logic diagram of a full-adder using gates as shown in Figure 5.4.7.
READER NOTE
A half-adder has two 1-bit inputs and there is no provision to add a carry which could have been generated from lower bit order additions. This limitation of half-adder is overcome in full-adder.