Colectivos jóvenes y adolescentes en grave riesgo

W

L æ

èç ö ø÷ =æ

èç ö ø÷ =

1 2

40

The output Vo is

(A) -2.5 V (B) 2.5 V

(C) 5 V (D) 0 V

23. If the ratio is W L æ èç ö

ø÷ =

1

40 and W L æ èç ö

ø÷ =

2

15, then Vois

(A) 2.91 V (B) 2.09 V

(C) 3.41 V (D) 1.59 V

24. In the circuit of fig. P3.324. the transistor parameters are VTN = 1 V and ¢ =kn 36mA / V². If ID= 0 5. mA, V1= V and V5 2 = V then the width to-length2 ratio required in each transistor is

W L æ èç ö

ø÷

1

W L æ èç ö

ø÷

2

W L æ èç ö

ø÷

3

(A) 1.75 6.94 27.8

(B) 4.93 10.56 50.43

(C) 35.5 22.4 8.53

(D) 56.4 38.21 12.56

25. The transistors in the circuit of fig. P3.3.25 have parameter VTN = 0 8. V, k¢ =n 40mA / V² and l = 0. The width-to-length ratio of M2 is

( )

^WL 2= . If V1 o= 0 10. V when V_i= 5 V, then

( )

^WL 1 for M1 is

(A) 47.5 (B) 28.4

(C) 40.5 (D) 20.3

Statement for Q.26–27:

All transistors in the circuit in fig. P3.3.26–27 have parameter VTN = 1 V and l = 0.

The conduction parameter are as follows:

Kn1 =400mA / V² Kn 2 =200mA / V² Kn 3=100mA / V² Kn 4 =80mA / V² 26. ID1 = ?

(A) 0.23 mA (B) 0.62 mA

(C) 0.46 mA (D) 0.31 mA

27. ID4 = ?

(A) 0.62 mA (B) 0.31 mA

(C) 0.46 mA (D) 0.92 mA

UNIT 3 Analog Electronics

M1

V1

V2

+5 V

M₂

M3

Fig. P3.3.24 M1

V_o +5 V

M2

Fig. P3.3.22-23

M₁ V_o V_i

+5 V

M₂

Fig. P3.3.25

+5 V

M1

I_D1

I_D4

-5 V

R_D

R_G

M4

M3

M2

Fig. P3.3.26–27 GATE EC BY RK Kanodia

28. For the circuit in fig. P3.3.28 the transistor parameter are VTN = 0 8. V andk¢ =n 30mA / V². If output voltage is Vo= 0 1. V, when input voltage is Vi= 4 2. V, the required transistor width-to length ratio is

(A) 1.568 (B) 0.986

(C) 0.731 (D) 1.843

29. For the transistor in fig. P3.3.29 parameters are VTN = 1 V and Kn = 12 5. mA / V². The Q-point (ID,VDS) is

(A) (1 mA, 8 V) (B) (0.2 mA, 4 V) (C) (1.17 mA, 8 V) (D) (0.23 mA, 3.1V) 30.For an n-channel JFET, the parameters are IDSS = 6 mA and VP = -3 V. If VDS>VDS sat( ) and VGS = -2 V, then ID is

(A) 16.67 mA (B) 0.67 mA

(C) 5.55 mA (D) 1.67 mA

31. For the circuit in fig. P3.3.32 the transistor parameters are Vp= - 35. V, IDSS = 18 mA, and l = 0. The value of VDS is

(A) 7.43 V (B) 8.6 V

(C) -1.17 V (D) 1.17 V

32. A p-channel JFET biased in the saturation region with VSD= 5 V has a drain current of ID= 2 8. mA, and ID= 0 3. mA at VGS = 3 V. The value of IDSS is

(A) 10 mA (B) 5 mA

(C) 7 mA (D) 2 mA

Statement for Q.33–34:

For the p-channel transistor in the circuit of fig.

P3.3.33–34 the parameters are IDSS = 6 mA, VP = 4 V and l = 0.

33. The value of IDQ is

(A) 8.86 mA (B) 6.39 mA

(C) 4.32 mA (D) 1.81 mA

34. The value of VSD is

(A) -4.28 V (B) 2.47 V

(C) 4.28 V (D) 2.19 V

35. The transistor in the circuit of fig. P3.3.35 has parameters IDSS = 8 mA and VP= -4 V. The value of VDSQ

is

(A) 2.7 V (B) 2.85 V

(C) -1.30 V (D) 1.30 V

******************

Chap 3.3 Basic FET Circuits

20 kW

10 kW +10 V

Fig. P3.3.29.

+15 V

-15 V I_Q= 8 mA 0.8 kW

Fig. P3.3.32

1 kW

0.4 kW

-5 V Fig. P3.3.33–34 10 kW

+5 V

V_o V_i

Fig. P3.3.28

+20 V

140 kW 2.7 kW

60 kW 2 kW

Fig. P3.3.35 GATE EC BY RK Kanodia

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SOLUTIONS

Assume that transistor in saturation region

I V Assume transistor in saturation

I V Assume transistor in saturation

I V 10. (C) Assume transistor in saturation.

ID= 0 4. mA, 0 4. =K VP( GS +VTP)² Assume transistor in saturation.

I V

VGS is positive. Thus (D) is correct option.

13. (D) I V

= 2 52. mA, Therefore (D) is correct option.

14. (B) 5=I RD( S+ RD)+VDS -5

UNIT 3 GATE EC BY RK Kanodia Analog Electronics

VGS= 152. V, VGS =VDS 21. (B) Assume transistor in saturation

I V

VDS>VGS -VTN Therefore both transistor are in saturation.

24. (A) Each transistor is biased in saturation because VDS =VGS and VDS >VGS-VTN

25. (D) M2 is in saturation because VGS2=VDS2>VGS2-VTN

M1 is in non saturation because VGS1 =Vi= V, V5 DS1=VD= V0

Basic FET Circuits GATE EC BY RK Kanodia

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1. If the transistor parameter are b = 180 and Early voltage VA= 140 V and it is biased at ICQ = 2 mA, the values of hybrid-p parameter gm, rp and ro are respectively

(A) 14 A V, 2.33 kW, 90 kW (B) 14 A V, 90 kW , 2.33 kW (C) 77 mA V, 2.33 kW , 70 kW (D) 77.2 A V, 70 kW, 2.33 kW

Statement for Q.2–3.

Consider the circuit of fig. P3.4.2–3. The transistor parameters areb = 120 and VA= ¥.

2. The hybrid-p parameter values of gm ,r_pand ro are (A) 24 mA V, ¥, 5 kW

(B) 24 mA V, 5 kW , ¥

(C) 48 mA V, 10 kW , 18.4 kW (D) 48 mA V, 18.4 kW, 10 kW

3. The small signal votlage gain Av=v vo s is

(A) -4.38 (B) 4.38

(C) -1.88 (D) 1.88

4. The nominal quiescent collector current of a transistor is 1.2 mA. If the range ofb for this transistor is 80£ £b 120 and if the quiescent collector current changes by ±10 percent, the range in value for r_p is (A) 1.73 kW < <rp 2 59. kW

(B) 1.93 kW < <rp 2 59. kW (C) 1.73 kW < <r_p 2 59. kW (D) 1.56 kW < <rp 2.88 kW

Statement for Q.5–6:

Consider the circuit in fig. P3.4.5.6. The transistor parameter areb = 100 and VA= ¥.

5.If Q-point is in the center of the load line and ICQ = 0 5. mA, the values of VBB and RC are

(A) 10 kW , 0.95 V (B) 10 kW , 1.45 V (C) 48 kW , 0.95 V (D) 48 kW , 1.45 V

CHAPTER

3.4

AMPLIFIERS

v_s

2 V

v_o 250 kW

+5 V

4 kW

~

Fig. P3.4.2–3

v_s

v_BB

R_C

50 kW +10 V

~

Fig. P3.4.5–6 GATE EC BY RK Kanodia

Statement for Q.14–15:

Consider the common Base amplifier shown in fig.

P3.4.14–15. The parameters are gm = 2 mS and ro= 250 kW. Find the Thevenin equivalent faced by load resistance RL .

14. The Thevenin voltage vTH is

(A) 263vi (B) 132vi

(C) 346vi (D) 498vi

15. The Thevenin equivalent resistance RTH is

(A) 384 kW (B) 697 kW

(C) 408 kW (D) 915 kW

Statement for Q.16–17:

The common-base amplifier is drawn as a two-port in fig. P3.4.16–17. The parameters are b = 100, gm = 3 mS, and ro= 800 kW.

16. The h-parameter h21 is

(A) 2.46 (B) 0.9

(C) 0.5 (D) 0.67

17. The h-parameter h12 is

(A) 3.8´10^-4 (B) 4.83´10^-3 (C) 3.8´10⁴ (D) 4.83´10³

18.For an n-channel MOSFET biased in the saturation region, the parameters are Kn = 0 5. mA V², VTN = 0 8. V andl =0 01. V , and I^-1 DQ= 0 75. mA. The value of gm and ro are

(A) 0.68 mS, 603 kW (B) 1.22 mS, 603 kW (C) 1.22 mS, 133 kW (D) 0.68 mS, 133 kW

19.For an n-channel MOSFET biased in the saturation region, the parameters are VTN = 1 V,¹2mnC =ox 18mA V² andl =0 015. V^-1 and IDQ= 2 mA. If transconductance is gm = 3 4. mA V, the width-to-length ratio is

(A) 80.6 (B) 43.2

(C) 190 (D) 110

20. In the circuit of fig. P3.4.20, the parameters are gm = 1mA / V, ro= 50 kW. The gain Av=v vo s is

(A) -8.01 (B) 8.01

(C) 14.16 (D)-14.16

Statement for Q.21–23:

For the circuit shown in fig. P3.4.21–23 transistor parameters are VTN = 2 V, Kn = 0 5. mA / V² and l = 0.

The transistor is in saturation.

21. If IDQ is to be 0.4 mA, the value of VGSQ is

(A) 5.14 V (B) 4.36 V

(C) 2.89 V (D) 1.83 V

22. The values of gm and ro are

(A) 0.89 mS, ¥ (B) 0.89 mS, 0 (C) 1.48 mS, 0 (D) 1.48 mS, ¥ 23. The small signal voltage gain Av is

(A) 14.3 (B) -14.3

(C) -8.9 (D) 8.9

Chap 3.4 Amplifiers

i2

v2

v1

+ +

_ _ i1

3.9 kW 18 kW

Fig. P3.4.16–17 v_i

270W

Thevenin equivalent

R_L

~

Fig. P3.4.14–15

V_DD

2 kW v_s

60 kW 10 kW

300 kW

~

Fig. P3.4.20

v_o

vi

VGG

10 kW +10 V

~

Fig. P3.4.21–23 GATE EC BY RK Kanodia

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(A) 4.44 (B) -4.44

(C) 2.22 (D) -2.22

Statement for Q.33–34:

Consider the source-follower circuit in fig.

P3.4.33-34. The values of parameter are gm = 2 mS and ro= 100 kW.

33. The voltage gain Av is

(A) 0.89 (B) -0.89

(C) 2.79 (D) -2.79

34. The output resistance R_o is

(A) 100 kW (B) 0.498 kW

GATE EC BY RK Kanodia

The small-signal equivalent circuit is as shown in fig.

11. (B) Since the B–C junction is not reverse biased, the transistor continues to operate in the forward-active -mode

UNIT 3 Analog Electronics

v_s

GATE EC BY RK Kanodia

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12. (C) r V

14. (D) The equivalent circuit is shown below

Removing the RL , - =

15. (A) The equivalent small-signal circuit is shown in fig. S3.4.15

16. (B) The equivalent small-signal circuit is shown in fig. S3.4.16

p can be neglected

h i GATE EC BY RK Kanodia

RS = 4 kW, vgs = 0 84. vi , 30. (C) From the DC analysis:

VGSQ= 15. V, IDQ= 0 5. mA

gm =2K Vn( GS -VTN) =2 1( m) ( .15-0 8. )=1 4. mA V ro=[lIDQ]^-1= ¥

The resulting small-signal equivalent circuit is shown in fig. S5.4.30

vo= -g v Rm gs D, vi=vgs+ g v Rm gs S

The transistor is therefore biased in the saturation region. The small-signal equivalent circuit is shown in fig.S3.4.31.

32. (A) The small-signal equivalent circuit is shown in fig. S.3.4.34

33. (A) The small-signal equivalent circuit is shown in fig. S3.4.33 GATE EC BY RK Kanodia

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1. A v

v vo i

= = ?

(A) -10 (B) 10

(C) -11 (D) 11

2. A v

v vo i

= = ?

(A) -10 (B) 10

(C) 13.46 (D) -13.46

3. The input to the circuit in fig. P3.5.3 is vi= 2 sin w mV. The current it o is

(A) -2 sin wt m A (B) -7 sin wt m A (C) -5 sin wt m A (D) 0

4.In circuit shown in fig. P3.5.4, the input voltage vi is 0.2 V. The output voltage vo is

(A) 6 V (B) -6 V

(C) 8 V (D) -8 V

5. For the circuit shown in fig. P3.5.5 gain is Av=v vo i= -10. The value of R is

(A) 600 kW (B) 450 kW

(C) 4.5 MW (D) 6 MW

CHAPTER

3.5

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