COMITÉS DE APOYO DE LA JUNTA DIRECTIVA

4H-SiC is a wide band gap semiconductor which is able to operate in high temperature [24] and harsh environments [6]. Many applications require 4H-SiC MOS devices to operate at high temperatures such as in the military and outer space sectors. Thus, MOS devices must be very reliable and stable at high temperatures in order to ensure that performance is not compromised under such hostile conditions.

In this section, p-type and n-type MOS capacitors with gate oxides fabricated using a low thermal budget method and 1150 °C oxidation technique are examined in order to observe their behaviour over a wide range of temperatures. Gate oxides were grown at 600 °C and 800 °C for 3 min using low thermal budget method followed by Al2O3 deposition. For comparison,

gate oxides which were grown in the furnace at 1150 °C for 180 min are also shown. Measurements at room temperature show that the low temperature gate oxides exhibit lower values of Dit compared to 1150 °C devices, as described in 4.3.4. Figure 4.20 shows the density

of oxide capacitance (Cox) for the fabricated (a) p-type and (b) n-type MOS capacitors extracted

from their C-V characteristics at 1 MHz in the accumulation region as a function of temperature between 25 °C and 300 °C. Each point of the Cox value is the average from 5 different devices.

Cox values of approximately 126 nf/cm2 which correspond to an EOT of 28 nm were obtained

over wide range of elevated temperatures. The results indicate that all of the fabricated devices with both p-type and n-type MOS capacitors exhibit excellent oxide stability during high temperature conditions.

Figure 4.20: Density of oxide capacitance measured at 1 MHz for (a) p-type and (b) n-type MOS capacitor as a function of temperature.

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Figure 4.21 shows the C-V characteristics for the forward sweep n-type MOS capacitors with gate oxide growth at 600 °C for 3 min + 40 nm of Al2O3 and 1150 °C for 180 min against

elevated temperature. The C-V curve for the MOSFET with gate oxide grown at 600 °C for 3 min shifts towards positive as the measured temperature increases up to 100 °C before changing its direction to a negative shift with further increases in temperature up to 300 °C. Overall, the C-V curves for both devices shift towards zero gate voltage with increasing temperature, and the device with gate oxide grown at 600 °C for 3 min demonstrates significant changes over the measured temperature range compared with the 1150 °C device. These changes were observed as a flatband voltage (Vfb) change in elevated temperatures and will discuss in detail

later.

Figure 4.21: C-V characteristics for forward sweep of fabricated n-type MOS capacitor with oxide growth at (a) 600 °C for 3 min and (b) 1150 °C for 180 min plotted against

elevated measured temperature.

Data from Figure 4.22 shows the Vfb during the forward and reverse sweeps for gate

oxides grown at 600 °C and 800 °C for 3 min as well as at 1150 °C for 180 min versus elevated temperature measured up to 300 °C. Each point of the Vfb value is the average from 5 different

devices. The Vfb at each temperature was extracted from C-V characteristics during the

accumulation region as discussed in section 3.3.1. The Vfb for the forward and reverse sweeps

of the p-type MOS with gate oxide grown at 1150 °C was stable over the measured temperature range. Both sweeps show a Vfb of approximately - 10 V at room temperature which changes

by ± 2 V up to the measured temperature at 300 °C. In contrast, the Vfb of gate oxide from the

low thermal budget process were significantly increased from - 14 V and - 9 V at room temperature to - 2 V at 300 °C for devices with oxide grown at 600 °C and 800 °C respectively.

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A similar trend could be observed in Vfb for n-type MOS devices in both the forward and

reverse sweeps. The devices with gate oxide grown at high temperature demonstrate a slight reduction towards 0 V from 4 V at 25 °C to about 2 V at the high temperature of 300 °C. However, a substantial decrease by 5 V was observed in low thermal budget devices over the measured temperature range up to 300 °C.

d

Figure 4.22: Vfb measured at 1 MHz for (a) forward sweep and (b) reverse sweep for p-type

and (c) forward and (d) reverse sweep for n-type MOS capacitor versus temperature These changes in Vfb over the temperature range can be attributed to the charges present

in the bulk oxide including fixed charge, Qf, oxide trap charge, Qot and mobile charge, Qm, as

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Figure 4.23: Effective oxide charge Neff, measured at 1 MHz for (a) forward sweep and (b)

reverse sweep for p-type and (c) forward and (d) reverse sweep for n-type MOS capacitors versus temperature

Figure 4.23 shows the Neff of the fabricated MOS capacitors extracted from C–V

characteristics measured at 1 MHz using equation 3.29 as a function of temperature. Each point of the Neff value is the average from 5 different devices and the gate metal work function,

ϕAl = 4.1 eV. These results indicate that the values of Neff in devices with an ultrathin layer of

SiO2 decreased significantly with increasing temperature from about 9.0 × 1012 cm-2 for those

grown at 600 °C and 5.0 × 1012 cm-2 for those at 800 °C to 6.0 × 1011 cm-2 with increasing temperature up to 250 °C before changing polarity to – 3.0 × 1011 cm-2 at 300 °C for both sweeps of the p-type MOS capacitors. In contrast, devices with gate oxide grown at 1150 °C displayed more or less similar values of Neff at around 6.0 × 1012 cm-2 at various elevated

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measured temperatures. Similar behaviour also could be noticed in n-type MOS capacitors for low thermal budget and standard high temperature gate oxide devices. These substantial changes Neff for low thermal budget devices may be due to the nature of bulk Al2O3, which

can have 5 stable charge states of O vacancy [126].

Figure 4.24: Change in flatband voltage, ΔVfb extracted at 1 MHz for fabricated (a) p-type and (b) n-type MOS capacitors as a function of temperature.

Figure 4.24 shows the hysteresis of flatband voltage (ΔVfb) calculated from the

differences in Vfb between the forward and reverse sweeps for (a) p-type and (b) n-type MOS

capacitors as a function of elevated temperature. Each point of the ΔVfb value is the average

from 5 different devices. For p-type MOS capacitors having an ultrathin SiO2 layer of gate

oxide, ΔVfb was relatively stable with values less than 0.7 V with increasing temperature.

Conversely, ΔVfb increased steadily by 1 V from 25 °C to 300 °C for ultrathin gate oxide n-

type devices, This variation in trends can be explained by the effect of electron trapping and de-trapping, which are known to happen in the Al2O3 [126]. For gate oxide grown at 1150 °C,

the values of ΔVfb were stable at less than 0.5 V from 25 °C before significantly surging at 200

°C and 300 °C for p-type and n-type devices respectively. This suggests that the electron trapping and de-trapping effect is also present in thermally grown SiO2 gate oxide but started

to rise beyond a certain temperature.

Figure 4.25 shows the density of interface traps, Dit at the 0.2 eV energy level near to

(a) the valence and (b) conduction band edges as a function of elevated temperature. Each point of the Dit value is the average from 5 different devices. The high–low method was used to

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n-type MOS devices demonstrated a slight reduction in Dit with increasing temperature up to

300 °C. This suggests that the interface trap charges are electrically excited at elevated temperature. In addition, as the temperature increases, the bandgap shrinks and becomes narrow so as to reduce the concentration of interface traps at the band edges [127]. The reduction of bandgap with temperature is shown in Figure 3.3. This effect also occurs in Si- SiO2 systems as temperature increases [128].

Figure 4.25: Values of Dit at the 0.2 eV energy level near to the (a) valence and (b)

conduction band edge versus temperature.