Comparación de modelos aerodinámicos

The NSC developed in this work synthesises circuits that are based upon the

Generic Neuron architecture, developed as part of another PhD thesis [190]. The Generic Neuron architecture has been devised to encompass the main features of the existing neural models into a single building block. The architecture provides: generality to implement the wide range of available neural models; and simplicity to optimise the processing element’s silicon area.

Generality is required by inspecting the spectrum of different neural network models, shown in Table 6.1. These models differ on several aspects: network topology, recall phase, and learning phase.

Network topology ranges firom single layer, feed-forward models, such as the Perceptron [122], through single layer with feedback connections, as the Hopfield model [86], to more complex interconnection patterns, found in the multi-layer networks

Chapter 6 NSC and Target Architecture 103

with back propagation of errors [161], and two-dimensional grid of neurons of the Self-Organising Map [99]. Neural Network Model Network Topology Range of input values Recall/Learning Phase

/ l - Recall Phase Learning Phase

Propagation Rule Activation Function f i - Weight Updating /3 - Error Calculation Hopfield/ Kohonen single-layer with feedback

binary net = Y,s.w hard

limiter Aw.. = s^.Sj X

Perceptron single-layer feed-forward

binary or

continuous net = y^s.\v

hard limiter Cj = t j - S j Widrow- Hoff (Delta Rule) single-layer

feed-forward continuous net=Y.s.w linear Awy = r\.Si.ej e j = t j - S j

Back Propagation

multi-layer bidirectional

links

continuous net='Zs.w sigmoid Awij = Ti.j,..e^. ej, = r(net).(tj-s,)_{e^ = T(net)flE .W}

Boltzman Machine

multi-layer or randomly

connected

binary net='Zs.w sigmoid Aw..= T|.8^. <v = n((pv)-(p.v)) Counter

Propagation

multi-layer

feed-forward binary net='Zs.w

hard limiter Aw.. Self Organising Map 2-dimensional grid of output PEs

continuous net = Y,s.w sigmoid AWij =

Neocognitron

hierarchical multi-layer feed-forward

continuous linear Aw^j = TI'Ey X

Table 6.1 — Characteristics of Some Popular Neural Network Models

The recall phase / j , formed by the propagation rule and activation function,

presents some variations among these neural models. With the exception of the Neocognitron model [56,57], the propagation rule basically calculates the weighted sum of the input states. The Neocognitron model applies a more complex function of input states and weight states, which are classified into excitatory % , W^) and inhibitory

(%, W/j) values. The activation function is usually restricted to either a threshold function, pseudo-linear function, or sigmoid families function.

The learning phase ( /2, /3> differs considerably among the models. In algorithms

such as Hopfield/Kohonen’s associative memories [86,99], the learning phase does not involve any error calculation (shown in Table 6.1 as x ), updating the weight values based upon the Hebbian rule [106]. Other models generally depend upon an error calculation.

They can be as simple as the difference between a target value and the neuron’s output state (Perceptron [122] and Delta Rule [106]), or can involve more complex

104 NSC and Target Architecture Chapter 6

computations, such as the Back Propagation model [161] in which the error calculation requires the derivative of the activation function (T(net)).

Simplicity is necessary to integrate as many PEs into a single integrated circuit as the technology permits. The search for generality and simplicity has resulted in a structure as shown in Figure 6.3a. The Generic Neuron model performs the neural computation based on: the set of state inputs S (received from other neurons); the state output s (sent to other neurons); and the group of error inputs E and error output e, provided to cope with models with backward propagation of errors. Internally, this model comprises a memory block for holding the weight values (W), and three basic functional blocks for implementing the specific computation required by the majority of neural models: the recall function / j , the weight updating function /2, and the error calculation function /g (see

Table 6.1). Input Bus (state inputs) output) inputs) output) (a) tkmUnit ' r Neuron Unit Weight Unit Forward Blocks B ackward Blocks Output Bus

Figure 6.3 — The Generic Neuron Model

The simplicity of the Generic Neuron model is extremely suitable for sihcon compilation, since neural models differ from each other essentially on the functions performed by / j , /2, and /g, along with the network’s topology. The correspondent

architectural framework of the Generic Neuron model is represented by the processing element (PE) shown in Figure 6.3b. The PE comprises three logical units, namely

communication, weight, and neuron unit. The communication unit interfaces with the other two units and performs the reading and writing of input and output data. The weight unit executes the weight update during the learning phase, while the neuron unit calculates the neuron outputs (state and error).

The communication between PEs is accomplished through a broadcast bus (Figure 6.4a), which provides the system with important features such as flexibility, expandability, and scalability [190]. Firstly, flexibility is achieved since the bus interconnection can handle all possible complex topologies. Secondly, expandability on the

Chapter 6 NSC and Target Architecture 105

number of PEs is obtained by simply plugging new PEs onto the bus. Finally, scalability is attained since increasing the number of PEs integrated into the same chip does not affect its pin count. Moreover, to improve the bus performance, the system can be further expanded into several busses (Figure 6.4b), clustering together into the same bus PEs that receive the same data input.

Control Address Data

Bus Bus Bus Bus1

Bus 2 Bus3 Bus 4 Central Controller PE, in P E , PE, in P E . Hidden Layer 1 in PE in P E oulj"» —» in P E Hidden Layer 2 In P E out in P E OUI In P E oui Output Layer in P E out —* In P E out In P E out

(a)

Figure 6.4 — Processing Elements Interconnection: (a) Single Bus; (b) Multi-busses The PEs are commanded by the central controller through three busses (Figure 6.4a): data, address, and control. The data bus is used in two basic situations: (i) initialisation phase, during which the central controller loads into the PE’s internal memory all necessary data values, including algorithm-dependent parameters and architecture-dependent parameters; and (ii) execution phase, when PEs send states and error values to other PEs in the network.

The address bus carries an identification of the PE that has exclusive access to the data bus. This arbitration is performed by the central controller in conjunction with the

control bus according to a polling mechanism. Through this mechanism, the central controller waits for a ready signal from the PE, after which a new value is placed onto the

address bus (the address of the PE in question). Therefore, the central controller can only modify the contents of the address bus after the PE has processed its output data (state or error value), and has activated the ready control signal.

The control bus contains all significant signals that direct the network’s behaviour. It comprises signals from the central controller to each PE and vice-versa. These include signals such as reset, forward/backward phase definition, the PE’s ready signal, etc.

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