--- --- -- Module Name : Celda
--- --- library IEEE; use IEEE.STD_LOGIC_1164.ALL; --- entity Celda is
Port ( -- Señales Globales clk : in STD_LOGIC; reset : in STD_LOGIC; en : in STD_LOGIC;
sel_datos : in STD_LOGIC_VECTOR(2 downto 0); sel_vecinos : in STD_LOGIC_VECTOR(3 downto 0); Data_in : in STD_LOGIC_VECTOR(7 downto 0); --> Acumulador acc_en : in STD_LOGIC; clr_acc : in STD_LOGIC; --> Orientación de la Información clr_info : in STD_LOGIC; orient_info : in STD_LOGIC;
--> Mod Memoria - Filtros
dir_memoria : in STD_LOGIC_VECTOR(5 downto 0); wen : in STD_LOGIC;
--> Autómata NO Lineal
sel_ca_no_lineal : in STD_LOGIC; wen_2 : in STD_LOGIC;
address_ca_no_lineal : in STD_LOGIC_VECTOR(8 downto 0); data_no_lineal : in STD_LOGIC_VECTOR(7 downto 0); --> Vecinos
arr : in STD_LOGIC_VECTOR(7 downto 0); abj : in STD_LOGIC_VECTOR(7 downto 0); izq : in STD_LOGIC_VECTOR(7 downto 0); der : in STD_LOGIC_VECTOR(7 downto 0); dul : in STD_LOGIC_VECTOR(7 downto 0); dur : in STD_LOGIC_VECTOR(7 downto 0); ddl : in STD_LOGIC_VECTOR(7 downto 0); ddr : in STD_LOGIC_VECTOR(7 downto 0); --> Estado de la celda
estado : out STD_LOGIC_VECTOR(7 downto 0)); end Celda;
--- architecture arq_Celda of Celda is
-- =================================== -- -- == Módulos que componen la celda == -- -- =================================== -- --> Memoria RAM 512bits
component Mod_Memoria is
Port ( address : IN STD_LOGIC_VECTOR(5 DOWNTO 0); clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR(7 DOWNTO 0); wren : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); end component;
--> Multiplexor selector de vecinos component Mux_Vecinos is
Port ( data0x : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
data1x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); data2x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); data3x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); data4x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); data5x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); data6x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); data7x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); data8x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); sel : IN STD_LOGIC_VECTOR (3 DOWNTO 0); result : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)); end component;
--> Multiplexor para direcciones de memoria del autómata No Lineal component Mux_Mem_No_Lineal is
Port ( data0x : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
data1x : IN STD_LOGIC_VECTOR (8 DOWNTO 0); sel : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (8 DOWNTO 0)); end component;
--> Autómata NO Lineal component Mem_NO_Lineal is
Port ( address : IN STD_LOGIC_VECTOR (8 DOWNTO 0); clock : IN STD_LOGIC ;
wren : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)); end component;
--> Multiplicador
component Multiplicador is
Port ( dataa : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (7 DOWNTO 0); result : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)); end component;
--> Acumulador
component Acumulador is
Port ( reset : in STD_LOGIC;
ck_en : in STD_LOGIC;
x : in STD_LOGIC_VECTOR(15 downto 0); Acc : out STD_LOGIC_VECTOR(15 downto 0)); end component;
--> Meddida de Orientación de la Información component Med_Orient_Info is
port ( clk : in STD_LOGIC;
reset : in STD_LOGIC; orient_info : STD_LOGIC;
Entrada : in STD_LOGIC_VECTOR(15 downto 0); Salida : out STD_LOGIC_VECTOR(15 downto 0)); end component;
--> "Binarización" de la imagen component Binarizado is
Port ( dato_a : in STD_LOGIC;
dato_b : out STD_LOGIC_VECTOR(7 downto 0)); end component;
--> Multiplexor de entrada al registro de estado component Mux_Reg_estado is
Port ( data0x : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
data1x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); data2x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); data3x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); data4x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); sel : IN STD_LOGIC_VECTOR(2 downto 0); result : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)); end component; --> Registro de Estado component Reg_Estado is Port ( clk : in STD_LOGIC; reset : in STD_LOGIC; en : in STD_LOGIC; D : in STD_LOGIC_VECTOR(7 downto 0); Q : out STD_LOGIC_VECTOR(7 downto 0)); end component;
-- ========================= -- -- == Señales de Conexión == -- -- ========================= -- signal s_clr_acc : STD_LOGIC; signal s_clr_info : STD_LOGIC;
signal s_factor_1 : STD_LOGIC_VECTOR(7 downto 0); signal s_factor_2 : STD_LOGIC_VECTOR(7 downto 0); signal s_prod : STD_LOGIC_VECTOR(15 downto 0); signal s_acc : STD_LOGIC_VECTOR(15 downto 0);
signal s_orient_info : STD_LOGIC_VECTOR(15 downto 0); signal s_reg_estado : STD_LOGIC_VECTOR(7 downto 0); signal s_estado : STD_LOGIC_VECTOR(7 downto 0); signal s_binarizado : STD_LOGIC_VECTOR(7 downto 0);
signal s_no_lineal_mux : STD_LOGIC_VECTOR(8 downto 0); signal s_no_lineal_in : STD_LOGIC_VECTOR(8 downto 0); signal s_no_lineal_out : STD_LOGIC_VECTOR(7 downto 0); begin
-- ================================= -- -- == Conexión de los Componentes == -- -- ================================= -- C0: Mux_Vecinos
port map ( data0x => s_estado, data1x => arr, data2x => abj, data3x => izq, data4x => der, data5x => dul, data6x => dur, data7x => ddl, data8x => ddr, sel => sel_vecinos, result => s_factor_1); C1: Mod_Memoria
port map ( address => dir_memoria, clock => clk, wren => wen, data => Data_in, q => s_factor_2);
s_no_lineal_in <= s_estado(0) & arr(0) & abj(0) & izq(0) & der(0) & dul(0) & dur(0) & ddl(0) & ddr(0);
C2: Mux_Mem_No_Lineal
port map ( data0x => s_no_lineal_in,
data1x => address_ca_no_lineal, sel => sel_ca_no_lineal,
result => s_no_lineal_mux); C3: Mem_NO_Lineal
port map ( clock => clk,
wren => wen_2,
address => s_no_lineal_mux, data => data_no_lineal, q => s_no_lineal_out); C4: Multiplicador
port map ( dataa => s_factor_1,
datab => s_factor_2, result => s_prod); s_clr_acc <= clr_acc or reset;
C5: Acumulador
port map ( reset => s_clr_acc, ck_en => acc_en, x => s_prod, Acc => s_acc);
s_clr_info <= reset or clr_info; C6: Med_Orient_info port map ( clk => clk, orient_info => orient_info, reset => s_clr_info, Entrada => s_acc, Salida => s_orient_info); C7: Binarizado
port map ( dato_a => s_orient_info(7), dato_b => s_binarizado); C8: Mux_Reg_estado
port map ( data0x => s_orient_info(15 downto 8), data1x => s_orient_info(7 downto 0), data2x => s_binarizado, data3x => s_no_lineal_out, data4x => Data_in, sel => sel_datos, result => s_reg_estado); C9: Reg_Estado port map ( clk => clk, reset => reset, en => en, D => s_reg_estado, Q => s_estado); --> Datos de Salida estado <= s_estado; --- end arq_Celda;