The IGBT die-attach solder scans produced 3D results which were processed and analysed by out WMG co-operators in this study. This was associated with some difficulties due to the nature of the objects scanned: with the x- and y- dimensions (length and width – about 7mm) orders of magnitude larger than the z- dimension (thickness – around 100 μm or less – meaning it could be represented by only around 10-11 voxels). Figure 69 below shows examples of side view thickness of the solder layer. It was produced in theVGStudio Max 2.2.5 software package and shows some large pores penetrating the whole die-attach solder layer. This is prior to the modules being power cycled, meaning that significant defect in the die- attach can potentially exist in brand new modules.
Scan Results
Figure 69. Side view examples – cross section of the thickness of die-attach solder: a/Module 1 – top IGBT; b/Module 2- bottom IGBT.
Despite this difference in dimensions, it was possible to process the results and provide 3D imaging and further analysis of the die-attach porosity. The photo images below represent the immediate scanning results visualised using theVGStudio Max 2.2.5 software package. They are 2D view of the 3D scans taken around mid-thickness of the die-attach layer. In each case image a/ represents the die-attach before power cycling and image b/ – after power cycling. What is immediately visible in these images is that there is significant porosity inside the solder layer to start with, as well as some gaps at edge and corner position. What is not immediately visible is the change this porosity undergoes after power cycling.
Scan Results
Figure 70. Module 1 – top IGBT die attach a/before power cycling; b/after power cycling.
Scan Results
Figure 71. Module 1 – bottom IGBT die attach a/before power cycling; b/after power cycling.
Figure 72. Module 2 – top IGBT die attach a/before power cycling; b/after power cycling.
a b
Scan Results
Figure 73. Module 2 – bottom IGBT die attach a/before power cycling; b/after power cycling.
Figure 74. Module 3 – top IGBT die attach a/before power cycling; b/after power cycling.
a b
Scan Results
Figure 75. Module 3 – bottom IGBT die attach a/before power cycling; b/after power cycling.
The scan images were further processed using Avizo 9.0.0, which allowed extracting numerical area and volume data of the pores. The word pore here means any void surrounded by solder material (so unfortunately the Avizo analysis excludes the edge located voids with opening outside the solder). The images below prepared in Avizo, (Figure 76, Figure 77, Figure 78, Figure 79, Figure 80 and Figure 81) present a visual comparison between the die-attach solder of each IGBT chip before power cycling and after power cycling. The pores or voids shown in them are colour-coded by volume size according to the same logarithmic scale in all images:
Lighter blue – 0.000005 – 0.00001 mm3
Scan Results
Darker blue – 0.00001 – 0.0001 mm3
Red – 0.0001 – 0.001 mm3
Green – 0.001 – 0.01 mm3
The minimum object size allowed by the scan is double the voxel size, but after the scan results have been cleared of noise, the smallest pore objects left are 0.000005 mm3. Even from these 2D images, a couple of things can be observed
straight away:
The few very largest voids seem be decreasing in size in the second scan – after the power cycling;
The middle-sized and smaller voids seem to be increasing in size and number after the power cycling;
Generally the pores tend to preserve their shape.
In some cases smaller pores seem to be merging into larger pores (e.g. Figure 79) and thus new pores seem to appear, while the old smaller ones are disappear (Figure 78).
The reasons for the above changes are discussed in more detail in the following section, but similar phenomena in solder layers – i.e. growth in size, merging of pores, etc. – have been previously observed to happen during the solder reflow process [104]. The principle cause of pore formation discussed there is the trapping of flux or solvent residue inside the solder layer. The pore growth is then mainly driven by the evaporation of those volatile components and the increase of pressure of the gases pushing on the sides of the pore bubble as solder is being
Scan Results
heated. When the gas pressure inside the pore reaches equilibrium with the opposing pressure components the pore stops growing.
In our case the heating during the power cycling of the module, although not sufficient to melt the solder, most likely resembles a succession of multiple reflow cycles at a relatively low temperatures. Heating is known to increase the diffusivity of metals and it encourages the mobility of particles within the solid material. It may allow small pores to migrate and agglomerate towards the solder interfaces in an attempt to escape.
With this is mind, the changes that have occurred in the die-attach solder layers of the power-cycled IGBT chips are not so surprising, even though the modules were subjected to a relatively small number of cycles with relatively low
Scan Results
b a
Figure 76. Scans of Module 1 – top IGBT die-attach: a/before power cycling; b/after power cycling.
a b
Figure 77. Scans of Module 1 – bottom IGBT die-attach: a/before power cycling; b/after power cycling.
Scan Results
a b
Figure 78. Scans of Module 2 – top IGBT die-attach: a/before power cycling; b/after power cycling.
a b
Figure 79. Scans of Module 2 – bottom IGBT die-attach: a/before power cycling; b/after power cycling.
Scan Results
a b
Figure 80. Scans of Module 3 – top IGBT die-attach: a/before power cycling; b/after power cycling.
a b
Figure 81. Scans of Module 3 – bottom IGBT die-attach: a/before power cycling; b/after power cycling.
Further Analysis of Scan Results