CONTEXTO: EL APRENDIZAJE ORGANIZATIVO EN LA SOCIEDAD DEL CONOCIMIENTO

2.6.6 A Summary of High-Performance Intra-Chip Signalling

Different approaches contributing to the on-chip signalling and communication which are listed and summarized for comparative purposes in Table 2.4. Each approach is classified according to the several defining features described below:

• Is the proposed signalling method analyzed through analytic or simulation-based means?

• What technology process is used?

• What kind of scheme is employed for cross-clock domain communication?

• What is the throughput achieved?

2.7 Summary

This chapter has provided a background to previous, concurrent, and ongoing work in the field of architectural design and circuit techniques for on-chip communication systems. A survey has been given of the architectures and taxonomy of to classify the architectures based on their struc-tures, such as “soft” and “hard” communication architecstruc-tures, and functionalities are presented. It has been noted that there is a gap between the ever increasing communication demand from the multiple on-chip modules or cores, and the available bandwidth provided by the existing hardware architectures.

The major design criteria for on-chip communication systems have been briefly reviewed, and a detailed survey and summary have been made of the existing published approaches to the problems of on-chip signalling and routing. On-chip signalling and routing are the two important concepts to design an efficient communication system. The on-chip communication bandwidth is determined by the signalling throughput whereas routing determines the utilization of the overall bandwidth.

FPGAs provide a flexible platform to realise hardware architectures and systems. Due to the complex programmable interconnect architecture, circuit design and optimization for on-FPGA signalling and routing are challenging, and have not been studied. To directly adapt on-chip com-munication architectures that are proposed for ASIC design can result in significant hardware cost

ProposedmethodAnalytic/SimulationTechnologyHand-shakeprotocolThroughputa Princetonwave-pipeliningsimulation(Cadence)250nmsourcesynchronous3.45GHzon10mm [XW02,XW03] GITwave-pipelininganalyticalandsimulation130nmtimedivisionmultiplexing2.5GHzon1cm [VD05,JDD06] KAISTwave-pipeliningsimulation(HSPICE)130nmWAFT800MHz [LKK+ 05] Newcastlephaseencodingsimulation(HSPICE)90nmasynchronousclockrecovery800MHz [DSBY05,DMBY07] Thisthesiswave-pipelininganalyticalandsimulation90nmsourcesynchronous1.3GHz (Chapter4)andrealFPGAtesting Cambridgepulse-basedsignalingsimulation(Cadence)90nmasynchronoushand-shake1.2GHz [HM06] Table2.4:Acomparisonofhigh-performanceintra-chipsignallingmethods. a Thethroughputforon-chipsignallingisaffectingbyvariousfactors,suchasbufferdesign,interconnectionlength,voltageetc.,aswillbediscussedinChapter5.Thevalues presentedhereareforreferenceonlyandnotforacomparativepurposes.

2.7 Summary 58

and limited improvement in communication bandwidth. This thesis provides an in-depth analytical study of the FPGA interconnect architecture. Novel signalling techniques and routing methodolo-gies that can exploit the programmable interconnect fabrics are proposed and these techniques can substantially enhance the on-FPGA communication performances.

Chapter 3

Fringed Interconnects and Bandwidth Degradation in Communication Links

3.1 Introduction

On-chip communication system, such as hierarchical bus and network-on-chip, always comprises of multiple instances of high-performance communication links. These links are fundamental to the overall system and serves as a backbone to interconnecting modular blocks, embedded processors, DSP modules and memories. They are also responsible for delivering bandwidth as on-chip communication channels. The bandwidth of these links determines the inter-modular communication speed and is critical to the overall system performance.

3.1.1 Degraded Bandwidth in Communication Links

The basic realization of a communication link uses parallel lines or buses. When considering a synchronous system, ideally, the bandwidth of a bus is proportional to the bit-width. Mathemati-cally, the bandwidth is given by β = S · α where S is the bit-width and α is the throughput of a single line. However, this assumption may not be valid, especially when these lines are long and are implemented in a complex programmable architecture. The interconnections in a communi-cation link have different lengths. Increase in bit-width can potential create routing congestions and, thus, adversely affect the delay and bandwidth of the link. An example is shown in Fig. 3.1, which sketches a general observation of the bandwidths of parallel lines for different bit-widths.

Dashed line represents the ideal bandwidth and the solid line represents the degraded bandwidth

3.1 Introduction 60

Ban dw idth (b its/

seco nd )

Figure 3.1: The ideal and degraded bandwidths against bit-width of a communication link in FPGAs.

after the place-and-route in a reconfigurable architecture. The bandwidth degradation increases with bit-widths. This would eventually hamper the overall performance of communication sys-tems and diminish the utilization of hardware resources for bandwidth delivery. This chapter aims to investigate the cause of bandwidth degradation and to understand the impact of the underlying reconfigurable architecture to high-performance links implementation.

3.1.2 Interconnection Length Prediction

Delay and bandwidth of a link is determined by interconnection length. Estimation of interconnect length can be used to predict the bandwidth of parallel lines and provides an in-depth understand-ing on the bandwidth degradation issues. Although there are a number of methods to estimate the interconnection lengths and distribution for general circuits [Str01, BB03, MCSB06], a method to accurately characterise and predict communication link bandwidth is still missing. The spe-cific difference in assumptions for “generic logic” and communication links is that the routing endpoints for generic logic are generally evenly distributed over an area, whereas communication

links involve S wires that are routed in parallel between two endpoint regions.

A heuristic approach based on the bounding box method [BB03] has been proposed. This method can provide an approximation for generic logic delay in FPGAs. In [MCSB06], by studying a number of large design examples and applying statistical methods, an estimate on delay distribu-tions can be inferred. However, all of these approaches target delay prediction for generic logic and the linear relationship assumption for bandwidth-bitwidth is still applied. To accurately pre-dict the bandwidth of communication links, a more detailed routing model is required. Early work by Brown [BRV93], proposed an analytical model to predict the routability of a particular FPGA architecture for a given channel width is particularly interesting. Although the analytical model presented in [BRV93] aims to compute the circuit routability and to evaluate the FPGA architec-ture, the model provides a solid framework for extension to communication link modeling and bandwidth prediction.

In [MSCL07], a simple method to approximate the interconnection length in a communication is presented (See Appendix A). This approach greatly simplifies the routing configuration, by re-garding the utilization of number of long interconnects in routing channels is a constant, in the interconnect channels and, thus, can provides a simple and fast approximation for the interconnec-tion lengths.

In this chapter, methodology to model communication links and to predict the length of the inter-connections and, subsequently, the link bandwidth is presented. Analytical model and expressions of the interconnection length and variance of a link have been rigorously derived. The model is ver-satile, engendering the exploration of a wide range of communication link designs, and is readily applicable to explore and investigate the bandwidth degradation issue for different architectures.

FPGA architecture parameters, such as channel width and number of tracks in the channel, are also captured in this model and, thus, the theory could be extended to study alternative FPGA routing architectures. This model improves the simple approximation in [MSCL07] by considering a more realistic and comprehensive routing architecture. Furthermore, a general phenomenon, which is termed here “interconnect fringing”, has been identified in communication link implementation.

This introduces additional delay to a link because of the dispersed routing of the “fringed” inter-connections. The proposed model can also effectively captures the fringing phenomenon in order to provide a more accurate delay estimate.