CONTROL FITOSANITARIO

■ Setting partitions

■ Estimating digital delays

■ Simulating the design

In this design example, you also view the analog backannotated parasitics.

Extracting Analog Parasitics

You can extract parasitics from cells in the design below the first level of hierarchy. You can run the extraction process on blocks within the design or on the entire design.

The analog parasitic extraction process consists of extracting parasitics, running LVS (layout versus schematic comparison for terminal mapping), and creating an analog extracted view.

You repeat this process for each block in your design where you want parasitics extracted.

In this design example, you build an analog extracted view for the4-bit DAC cell.

Extracting Parasitics

1. If a Library Manager window is not already open, start the library manager from the CIW by choosing Tools – Library Manager.

2. In the Library Manager window, select mixSigLib as the library, 4_bit_DAC as the cell, and schematic as the view.

3. Choose File – Open.

A schematic window opens, displaying the 4-bit DAC schematic. This is an analog-only design.

4. From the Library Manager window, open the layout view of the 4-bit DAC. (Select layout as the View and choose File – Open).

5. In the layout window, choose Verify – Extract.

The Extractor form appears.

6. Choose Join Nets With Same Name.

This ensures that nets with the same names are automatically joined.

7. Click on Set Switches to select the parasitics to be extracted.

The Set Switches form appears, showing the parasitics defined for your design.

8. Select parameters, Rparasitics, and Rpoly.

9. Click OK.

The Switch Names field updates with the parasitics you selected.

10. Ensure that the Extractor form is filled in as shown.

11. Click OK to start the extraction process.

You can follow the extraction process in the CIW. When the extraction completes successfully, the following message appears in the CIW:

***Summary of rule violation for cell

"

"

Total errors found: 0

12. Close the 4-bit DAC layout window. Do not save changes.

Comparing Views

In this procedure, you run LVS, which compares the schematic view with the extracted view you just created. Any mismatches are identified at the end of the run.

1. In the Library Manager window, select the extracted view of the 4-bit DAC cell.

2. Choose File – Open.

A new window opens with the extracted view.

3. In the extracted view window, choose Verify – LVS.

The LVS form appears.

4. Ensure that the fields are filled in as shown above.

If the Create Netlist section of the form is not filled in as shown, you must identify the schematic and extracted views that you want to compare.

❑ Click Sel by Cursor on the schematic side and click again in the 4-bit DAC schematic window. The Library, Cell, and View fields are updated automatically.

❑ Click Sel by Cursor on the extracted side, then click in the 4-bit DAC extracted view window. The Library, Cell, and View fields are updated automatically.

5. Click the Run button at the bottom of the LVS form to begin the comparison.

6. Click the Info button to view the log file while LVS is running.

The Display Run Information form appears.

7. Click Log File.

A log file window opens and the LVS run information appears.

Running simulation in directory: "/user1/msps/LVS".

Begin netlist: Aug 4 22:35:15 1997

view name list = ("msps" "auLvs" "extracted") stop name list = ("msps" "auLvs")

library name = "mixSigLib"

cell name = "4_bit_DAC"

view name = "extracted"

globals lib = "basic"

Upon successful completion of the LVS run, the log file displays information about the netlist comparison.

Backannotating Parasitics

During extraction, Assura^™Diva^®calculated the parasitics associated with the 4-bit DAC and stored this information in the extracted view. In this procedure, you use the backannotation and parasitic probing features of LVS to display the parasitic information on the schematic.

1. Bring the schematic view to the front. Zoom in on the upper left corner of the schematic.

2. On the LVS form, click Backannotate.

The Parasitic Backannotation form appears.

3. Click Add Parasitics.

The parasitic information associated with each net displays on the schematic. This information is for illustrative purposes only. The resistors and capacitors are not actually added to the schematic.

4. Click Remove Parasitics.

5. Click Cancel to close the Parasitic Backannotation form.

Parasitic Probing

1. In the LVS window, click Parasitic Probe.

Backannotated parasitics

The Parasitic Probing form appears.

Clicking Whole Net dumps all parasitics on the net, up to the Max list size designated on the form. Clicking Point to Point dumps the parasitics between two terminals you select on the schematic. Clicking Net to Net shows the parasitics between two different nets.

2. Click Whole Net.

3. On the schematic, select the output of the 4-bit DAC.

A form appears, displaying the parasitics for the net you selected.

4. Select one of the presistors on this form.

In the top right corner of the extracted view, the corresponding presistor highlights. If you select another presistor on the form, the highlight on the extracted view changes

accordingly.

5. Click Cancel to close the form.

6. In the Parasitic Probing form, click Cancel to close the form.

7. Close the schematic, layout, and extracted view windows. Do not save the data.

Leave the LVS form open.

Building an Analog Extracted View

To include the analog parasitics for simulation, you must first create an analog extracted view.

This view contains the analog parasitic information. For more information, refer to Chapter 1,

“Diva Flow: Simulating Analog Circuits with Parasitics.”

1. On the LVS form, click Build Analog.

The Build Analog_Extracted View form appears.

2. For Extracted Parasitics, ensure that Include All is selected.

This option selects all extracted analog parasitics for simulation.

3. Click OK to build the analog extracted view.

The analog extracted view is built when the CIW displays

Building analog_extracted view for 4_bit_DAC Done

You can now simulate the 4-bit DAC with parasitics.

4. Choose Commands – Close Window to close the LVS window.